Lecture 5 (system clock crossbar and gpio) rv012

Lecture 5
System Clock, Crossbar and GPIO

2
System Clock, Crossbar and GPIO
 Introduction to system clock
 Internal oscillator
 External oscillator
 Initializing system clock
 Watchdog timer
 Port pin
 Output modes
 Configuring port pins as digital inputs
 Crossbar
 Crossbar pin assignment and allocation priority
 Enabling the crossbar
 XBR0 (Crossbar Register 0)

3
Introduction to the System Clock
 The system clock can be considered the
“heart-beat” of the microcontroller
 The C8051F020 microcontroller may be
operated from either an internal or an
external clock source
 Max system clock: 25 MHz
 Internal oscillator: 16 MHz  20%
 External oscillator options
 Crystal, capacitor, RC, CMOS clock

4
Internal Oscillator
 Upon reset, the MCU operates from the internal oscillator at
a typical frequency of 2.0 MHz by default
 It may be configured by software to operate at other typical
frequencies of 4.0 MHz, 8.0 MHz or 16 MHz
 The accuracy of the internal oscillator is  20%
 Many applications that do not need a very accurate clock
source will find the internal oscillator sufficient

5
Internal Oscillator Control Register (OSCICN)
 Upon reset, the
value in this
register is set to
00010100b
 This configures
the internal
oscillator to
generate a
frequency of
2 MHz
Bit Symbol Description
7 MSCLKE
Missing Clock Enable Bit
0: Missing Clock Detector Disabled
1: Missing Clock Detector Enabled. The reset is
triggered if clock is missing for more than 10ms
6-5 Unused Read = 00b, Write = don’t care
4 IFRDY
Internal Oscillator Frequency Ready Flag
0: Internal Oscillator Frequency not running at
speed specified by the IFCN bits.
1: Internal Oscillator Frequency is running at
speed specified by the IFCN bits.
3 CLKSL
System Clock Source Select Bit
0: Uses Internal Oscillator as System Clock
1: Uses External Oscillator as System Clock
2 IOSCEN
Internal Oscillator Enable Bit
0: Internal Oscillator Disabled
1: Internal Oscillator Enabled
1-0
IFCN1-
IFCN 0
Internal Oscillator Frequency Control Bit
00: Internal Oscillator typical frequency is 2 MHz

6
External Oscillator
 The external oscillator circuit supports four types of external
clock sources
 Crystal
 Used if accurate clock is needed
 Capacitor
 Used for low-power operation at low frequencies
 Inexpensive
 Resistor-capacitor (RC)
 Same as capacitor
 CMOS Clock
 Used if an external CMOS clock is available
 Helpful if used as a common clock for multiple devices that need to
communicate synchronously

7
External Crystal
 An external crystal is installed on the ToolStick MCUniversity
daughter card when shipped from the factory
 Crystals have a typical frequency accuracy of 0.1% or better
 The frequency of the crystal installed on the ToolStick DC is 22.1184
MHz
 This specific crystal frequency is chosen because it is especially
useful in providing a system clock frequency suitable for high baud
rate generation for serial port communication (UART)

8
External Oscillator Control Register (OSCXCN)
7 XTLVLD
Crystal Oscillator Valid Flag
0: Crystal Oscillator is unused or not yet stable
1: Crystal Oscillator is running and stable
6-4 XOSCMD2-0
External Oscillator Mode Bits
00x: Off. XTAL1 pin is grounded internally.
010: System Clock from External CMOS Clock
on XTAL1 pin.
011: System Clock from External CMOS Clock
on XTAL1 pin divided by 2.
10x: RC/C Oscillator Mode with divide by 2
stage.
110: Crystal Oscillator Mode
111: Crystal Oscillator Mode with divide by 2
stage
3 Reserved Read = undefined, Write = don’t care
2-0 XFCN2-0 External Oscillator Frequency Control Bit
 Upon reset, the value in
this register is set to
00000000b
 Bits 2-0: A table in the
‘F020 datasheet shows
the appropriate values
for the XFCN bits
based on the desired
external oscillator
frequency
 Bits 6-4: The XOSCMD
bits configure the
external oscillator type
(Crystal, RC, etc.)
 See the ‘F020
datasheet for the
values

9
External Crystal Starting Procedure
Configure the External Oscillator
OSCXCN[6:0]
Wait for at least 1 ms
(Delay loop or timer)
Is
XTLVLD
== 1?
Switch from internal to
External oscillator
(CLKSL bit in OSCICN)
YES
NO

10
Initializing System Clock
void Init_Ext_Clock(void)
{
unsigned int i;
  OSCXCN = 0x67; // 0110 0111b
  // External Osc Freq Control Bits (XFCN20) set
  //   to 111 because crystal frequency > 6.7 MHz
  // Crystal Oscillator Mode (XOSCMD20) set to 110
  // For Crsytal Oscillator Mode with divideby2 stage
  // OSCXCN = 0x77;
for (i=9000; i>0; i); // Wait at least 1 ms
  // Wait till XTLVLD pin is set
  while ( !(OSCXCN & 0x80) );
  OSCICN = 0x88; // 1000 1000b
  // Bit 2 : Internal Osc. disabled (IOSCEN = 0)
  // Bit 3 : Uses External Oscillator as System
  //           Clock (CLKSL = 1)
  // Bit 7 : Missing Clock Detector Enabled (MSCLKE = 1)
}

11
Watchdog Timer
 The MCU has a programmable watchdog timer (WDT)
which runs off the system clock
 An overflow of the WDT forces the MCU into the reset state
 Before the WDT overflows, the application program must
restart it
 WDT is useful in preventing the system from running out of
control, especially in critical applications
 If the system experiences a software or hardware
malfunction which prevents the software from restarting the
WDT, the WDT will overflow and cause a MCU reset

12
Watchdog Timer
 After a reset, the WDT is automatically enabled and starts running at the
default maximum time interval, which is 524 ms for a 2 MHz system
clock
 The WDT consists of a 21-bit timer running from the programmed
system clock
 A WDT reset is generated when the period between specific writes to its
control register exceeds the programmed limit
 The WDT may be enabled or disabled by software
 It may also be locked to prevent accidental disabling.
 Once locked, the WDT cannot be disabled until the next system reset
 It may also be permanently disabled. The watchdog features are
controlled by programming the watchdog timer control register
(WDTCN)
 The last reset source can be checked by reading the reset
sources (RSTSRC) register

13
Watchdog Timer Control Register (WDTCN)
Bit Description
7-0
WDT Control
Writing 0xA5 both enables and reloads the WDT
Writing 0xDE followed within 4 system clocks by 0xAD
disables the WDT
Writing 0xFF locks out the disable feature
4
Watchdog Status Bit (when Read)
Reading this bit indicates the Watchdog Timer Status
0: WDT is inactive
1: WDT is active
2-0
Watchdog Timeout Interval Bits
These bits set the Watchdog Timer Interval. When writing
these bits, WDTCN.7 must be set to 0.

14
Setting WDT Interval
 Bits 2-0 of WDTCN register control the watchdog timeout interval. The
interval is given by the following equation:
43+WDTCN [2-0]
x Tsysclk
 Tsysclk is the system clock period
 For a 2 MHz system clock, the interval range that can be programmed is
0.032 ms to 524 ms
 When the watchdog timeout interval bits are written to the WDTCN
register, the WDTCN.7 bit must be held at logic 0
 The programmed interval may be read back by reading the WDTCN
register
 After a reset, WDTCN[2-0] reads 111b

15
Disabling the WDT
//
// Basic blank C program that does nothing
// other than disable the watch dog timer
//
// Includes
//
#include <C8051F020_defs.h> // SFR declarations
void main (void)
{
   // Disable watchdog timer
   WDTCN = 0xde;
   WDTCN = 0xad;
   while(1);   // Stops program from terminating
}
//

16
Port Pin Output Modes
 The output mode of each port pin on Ports 0 through 3 can
be configured as either Open-Drain or Push-Pull
 The default state is Open-Drain
 In the Open-Drain configuration:
 Writing logic 0 to the associated bit in the Port Data register will
cause the Port pin to be driven to GND
 Writing logic 1 will cause the Port pin to assume a high-impedance
state
 In the Push-Pull configuration:
 Writing logic 0 to the associated bit in the Port Data register will
cause the Port pin to be driven to GND
 Writing logic 1 will cause the Port pin to be driven to VDD

17
Port Pin Output Modes
 The output modes of the Port pins are determined by the
bits in the associated PnMDOUT registers
 For example, a logic 1 in P1MDOUT.6 will configure the
output mode of P1.6 to Push-Pull; a logic 0 in P1MDOUT.6
will configure the output mode of P1.6 to Open-Drain
 Until the Crossbar is configured and enabled, the output
drivers are not enabled
 Example:
P1MDOUT |= 0x40; // Enable P1.6 as pushpull output

18
Configuring Port Pins as Digital Inputs
 A Port pin is configured as a digital input by setting its output
mode to “Open-Drain” and writing a logic 1 to the associated
bit in the Port Data register
 For example, P3.7 is configured as a digital input by setting
P3MDOUT.7 to a logic 0 and P3.7 to a logic 1
 Example:
// Configure P3.7 for input
P3MDOUT &= 0x7F; // Write a logic 0 to set OpenDrain
// Output mode
P3 |= 0x80; // write a logic 1 to P3.7

19
P1MDIN (Port1 Input Mode Register)
7-0 P1MDIN.[7:0]
Port 1 Input Mode Bits.
0: Port Pin is configured in Analog Input
mode. The digital input path is disabled (a
read from the Port bit will always return ‘0’).
The weak pull-up on the pin is disabled.
1: Port Pin is configured in Digital Input mode.
A read from the Port bit will return the logic
level at the Pin. The state of the weak pull-up is
determined by the WEAKPUD bit
 Reset Value: 0xFF (digital input mode)
 Clearing a bit here to enable analog input mode also does
the following:
 Disables output drivers on the corresponding port pin
 Instructs the crossbar to skip the pin for peripheral
assignment

20
Disabling Weak Pull-Ups
 Weak pull-ups are useful for bidirectional data
communication where an external strong pull-up is used
 This enables both sides to be able to drive the wire high or
low
 By default, each port pin has an internal weak pull-up device
enabled which provides a resistive connection (about
100 kΩ) between the pin and VDD
 The weak pull-up devices can be globally disabled by writing
logic 1 to the Weak Pull-up Disable bit (WEAKPUD, XBR2.7)
 The weak pull-up is automatically deactivated on any pin
that is driving a logic 0

22
Crossbar
 Problem: Many peripherals/functions are available inside the MCU
 There are limited number of pins available to connect the peripherals to the
outside world
 Solution: Pick and choose the peripherals that are necessary for an
application, and assign only those to external pins
 This is the function of the crossbar
 Based on the application, the system designer makes the decision as to
which peripherals are enabled, and which pins are used
 The C8051F020 has a rich set of digital resources like UARTs, system
management bus (SMBus), timer control inputs and interrupts
 These peripherals do not have dedicated pins through which they may be
accessed
 They are available through the four lower I/O ports (P0, P1, P2 and P3)
 Each of the pins on P0, P1, P2 and P3 can be defined as a general purpose
input/output (GPIO) pin or can be assigned to a digital peripheral
 :ower ports have dual functionalities
 This flexibility makes the MCU very versatile

23
Crossbar Pin Assignment and Allocation Priority

24
Crossbar Pin Assignment and Allocation Priority
 The crossbar has a priority order in which peripherals are assigned to
pins
 UART0 has the highest priority and CNVSTR has the lowest priority
 There are three configuration registers, XBR0, XBR1 and XBR2, which
are programmed to accomplish the pin allocations
 If the corresponding enable bits of the peripheral are set to a logic 1 in
the crossbar registers, then the port pins are assigned to that peripheral
 Pin assignments to associated functions are done in groups
 For example, TX0 and RX0 for UART0 are assigned together
 Example: If the UART0EN bit (XBR0.2) is set to logic 1, the TX0 and
RX0 pins will be mapped to the port pins P0.0 and P0.1, respectively.
 Since UART0 has the highest priority, its pins will always be mapped to P0.0
and P0.1 when UART0EN is set to logic 1 and will have precedence over
any other peripheral allocation

25
Enabling the Crossbar
 The crossbar should be enabled once all the crossbar registers (XBR0,
XBR1 and XBR2) have been configured
 This is done by setting XBARE (XBR2.6) to a logic 1
 All output drivers are disabled until the crossbar is enabled
// Configures the Crossbar and GPIO ports
void Init_Port(void)
{
P0MDOUT |= 0x01;   // Enable TX0 as a pushpull output
P1MDOUT |= 0x40;   // Enable P1.6 as pushpull output
XBR0 = 0x04; // Enable UART0
XBR1 = 0x00;
XBR2 = 0x40; // Enable Crossbar & weak pullups
                     //   (globally)
}

26
XBR0 (Crossbar Register 0)
 XBR0 SFR,
upon reset, has
a value 0x00
7 CP0E
Comparator 0 Output Enable Bit.
0: CP0 unavailable at Port pin.
1: CP0 routed to Port pin.
6 ECI0E
PCA0 External Counter Input Enable Bit.
0: PCA0 External Counter Input unavailable at Port pin.
1: PCA0 External Counter Input (ECI0) routed to Port pin.
5-3 PCA0ME
PCA0 Module I/O Enable Bits.
000: All PCA0 I/O unavailable at Port pins.
001: CEX0 routed to Port pin.
010: CEX0, CEX1 routed to 2 Port pins.
011: CEX0, CEX1, and CEX2 routed to 3 Port pins.
100: CEX0, CEX1, CEX2, and CEX3 routed to 4 Port pins.
101: CEX0, CEX1, CEX2, CEX3, and CEX4 routed to 5 Port pins.
110: RESERVED
111: RESERVED
2 UART0EN
UART0 I/O Enable Bit.
0: UART0 I/O unavailable at Port pins.
1: UART0 TX routed to P0.0, and RX routed to P0.1
1 SPI0EN
SPI0 Bus I/O Enable Bit.
0: SPI0 I/O unavailable at Port pins.
1: SPI0 SCK, MISO, MOSI, and NSS routed to 4 Port pins.
0 SMB0EN
SMBus0 Bus I/O Enable Bit.
0: SMBus0 I/O unavailable at Port pins.
1: SMBus0 SDA and SCL routed to 2 Port pins.

27
 XBR1 SFR, upon
reset, has a value
0x00
7 SYSCKE
/SYSCLK Output Enable Bit.
0: /SYSCLK unavailable at Port pin.
1: /SYSCLK routed to Port pin.
6 T2EXE
T2EX Input Enable Bit.
0: T2EX unavailable at Port pin.
1: T2EX routed to Port pin.
5 T2E
T2 Input Enable Bit.
0: T2 unavailable at Port pin.
1: T2 routed to Port pin.
4 INT1E
/INT1 Input Enable Bit.
0: /INT1 unavailable at Port pin.
1: /INT1 routed to Port pin.
3 T1E
2 INT0E
/INT0 Input Enable Bit.
0: /INT0 unavailable at Port pin.
1: /INT1 routed to Port pin.
1 T0E
0 CP1E
CP1 Output Enable Bit.
0: CP1 unavailable at Port pin.
1: CP1 routed to Port pin.

28
 XBR2 SFR,
upon reset,
has a value
0x00
7
WEAKPU
D
Weak Pull-Up Disable Bit.
0: Weak pull-ups globally enabled.
1: Weak pull-ups globally disabled.
6 XBARE
Crossbar Enable Bit.
0: Crossbar disabled. All pins on Ports 0, 1, 2, and 3, are forced to Input mode.
1: Crossbar enabled.
5 - UNUSED. Read = 0, Write = don't care.
4 T4EXE
T4EX Input Enable Bit.
0: T4EX unavailable at Port pin.
1: T4EX routed to Port pin.
3 T4E
2 UART1E
UART1 I/O Enable Bit.
0: UART1 I/O unavailable at Port pins.
1: UART1 TX and RX routed to 2 Port pins.
1 EMIFLE
External Memory Interface Low-Port Enable Bit.
0: P0.7, P0.6, and P0.5 functions are determined by the Crossbar or the Port
latches.
1: If EMI0CF.4 = ‘0’ (External Memory Interface is in Multiplexed mode) P0.7 (/WR),
P0.6 (/RD), and P0.5 (ALE) are ‘skipped’ by the Crossbar and their output states are
determined by the Port latches and the External Memory Interface.
1: If EMI0CF.4 = ‘1’ (External Memory Interface is in Non-multiplexed mode) P0.7
(/WR) and P0.6 (/RD) are ‘skipped’ by the Crossbar and their output states are
determined by the Port latches and the External Memory Interface.
0 CNVSTE
External Convert Start Input Enable Bit.
0: CNVSTR unavailable at Port pin.
1: CNVSTR routed to Port pin.

29
Ports 4 Through 7
 All Port pins on Ports 4 through 7
can be accessed as general-
purpose I/O (GPIO) pins by
reading and writing the
associated Port Data registers, a
set of SFRs which are byte-
addressable
 A read of a port data register (or
port bit) will always return the
logic state present at the pin
 The SFRs associated with ports
7 to 4 are P74OUT and the
individual Port Data registers:
P4, P5, P6 and P7
7 P7H
Port7 Output Mode High Nibble Bit.
0: P7.[7:4] configured as Open-Drain.
1: P7.[7:4] configured as Push-Pull.
6 P7L
Port7 Output Mode Low Nibble Bit.
5 P6H
4 P6L
3 P5H
2 P5L
1 P4H
0 P4L

Lecture 5 (system clock crossbar and gpio) rv012

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Lecture 5 (system clock crossbar and gpio) rv012