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ٍحافظ اوتقال
:
AR
DR
Read
Address Register
DR
Write
AR
M[AR]
.
.
:
Read :
AR
M
DR
Write : 1
R
AR
M
AR
Memory
unit
Read
Write
Data in
Data out](https://image.slidesharecdn.com/lecture2rtl-250417081845-ee51d560/85/Lecture2_RTuokcoursertlmemarycomppsL-pdf-17-320.jpg)
Lecture2_RTuokcoursertlmemarycomppsL.pdf
- 1. Department of Computer and IT Engineering University of Kurdistan Computer Architecture Register Transfer Language (RTL) By: Dr. Alireza Abdollahpouri
- 2. 2 Datapath ( ) The ALU, registers and logic to perform operations on them Control unit ( ) Generates signals to control datapath Accepts status signals to perform sequencing Control unit Data Path ٌپزداسوذ یک اساسی بخش دي
- 3. 3 رجيستز اوتقال سبان : RTL datapath RTL RTL RTL (Register Transfer language) Micro Operation Shift , Load , Clear , Inc ,Dec
- 4. 4 قًاويه RTL : MAR=Memory Address Register PC= Program Counter IR= Instruction Register R1=( ) PC 3 4 5 6 7 0 1 2 n 0 n-1 7 15 8 PC(L) PC(H) 0 PC(H)= PC(8-15) PC(L)= PC( 0-7 )
- 5. 5 : R2 R1 R1 R2 R1 R2 R1 . R1 R2 R2 Parallel Load قًاويه RTL R1 R1+R2, R3 0
- 6. 6 تابغ کىتزل ی : P: R2 R1 If (P=1) then (R2 R1) Control Circuit R2 R1 Load n P CLK
- 8. 8 Multiplexer-Based Transfers Consider Which can also be expressed as Block diagram? 2 0 ) 1 2 ( ) 1 0 ( ) 1 1 ( R R then K if else R R then K if 2 0 : 2 1 , 1 0 : 1 R R K K R R K
- 10. 10 2 1 1 ) 1 ( ) 7 1 ( ) 0 1 ( R R R then K if else R then R if Control unit R2 Load n K R1 MUX + n 1 0 7 (0…0111) تمزیه
- 11. 11 ٌگذرگا طزیق اس اوتقال ( BUS ) Bus Bus n n Bus .1 .2
- 12. 12 BUS اس ٌاستفاد با MUX 0 1 2 3 S0 S1 S0 S1 4 line Bus 4x1 MUX A B C D Reg Selected S0 S1 A 0 0 B 0 1 C 1 0 D 1 1 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 4x1 MUX 4x1 MUX 4x1 MUX MUX Mux 0 bus MUX
- 13. 13 طزیق اس اوتقال BUS BUS S1S0 BUS Load A B : BUS : BUS A , B Bus B A
- 14. 14 Output Y Input A Control C Y=A c=1 Y=High Impedance c=0 ساسي ٌپياد BUS گيتُاي اس ٌاستفاد با 3 ٍحالت : TriState Buffer
- 15. 15 Bus Decoder Bus line for bit 0 A0 B0 C0 D0 2x4 Decoder Enable S0 S1 ساسي ٌپياد BUS گيتُاي اس ٌاستفاد با 3 ٍحالت : TriState Buffer
- 17. 17 ٍحافظ اوتقال : AR DR Read Address Register DR Write AR M[AR] . . : Read : AR M DR Write : 1 R AR M AR Memory unit Read Write Data in Data out
- 18. 18 م يکزياپزیشه َا ي محاسبات ی : R3 R1+R2 FA B0 A0 S0 C0 FA B1 A1 S1 C1 FA B2 A2 S2 C2 FA B3 A3 S3 C3 C4
- 19. 19 : INC DEC م يکزياپزیشه َا ي محاسبات ی R3 R1-R2 معادل است با R3 R1+R2+1 R1 R1-1 R1 R1+1 HA x y C S A 0 1 S0 HA x y C S A 1 S1 HA x y C S A 2 S2 HA x y C S A 3 S3 C4
- 20. 20 ٌکىىذ جمغ بایىزي ٌکىىذ تفزیق ي n FA R1 R2 B3 B2 B1 B0 A0 A1 A2 A3 FA FA M S0 S1 S2 S3 C0 C4 C1 C2 C3 FA FA M=0 S=A+B M=1 S=A-B
- 21. 21 S1 S1 B B S1 B Micro Operatioon Add Add With Carry Sub with Borrow Sub Inc Dec Transfor . مذار ياحذ محاسبات ی D= A+Y+Cin Fi S0 S1 0 1 2 3 4x1 MUX Fi X0 S1 0 1 2 3 4x1 MUX Fi S0 S1 0 1 2 3 4x1 MUX Fi S0 S1 0 1 2 3 4x1 MUX C0 C1 Y0 FA X1 C1 C2 Y1 X3 C2 C3 Y3 X3 C3 C4 Y3 Cin Cout A0 A1 A2 A3 S1 S0 B 0 1 S0 B 0 1 S0 B 0 1 S0 B B 0 1 D0 D1 D2 D3 S0 S1 CIN Y D 0 0 0 B A+B 0 0 1 B A+B+1 0 1 0 B A+B 0 1 1 B A+B+1 1 0 0 0 A 1 0 1 0 A+1 1 1 0 1 A-1 1 1 1 1 A S0
- 22. 22 م يکزياپزیشه َا ي مىطق ی Logic MicroOperations . XOR OR AND 2 1 1 : R R R P 2 1 1 : R R R P 2 1 1 : R R R P
- 23. 23 م افشاري سخت ساسي ٌپياد يکزياپزیشه َا ي مىطق ی Ei S1 S0 Ai Bi S0 S1 MUX 0 1 2 0 0 0 1 1 0 1 1 S1 S0 OutPut B A E B A E B A E A E 3
- 24. 24 بزخ ی کاربزدَا ي اپزیشه ميکزي مىطقی َاي Selective Set A B B A A 1110 1100 1010 A B ) A ( A selective clear
- 25. 25 م يکزي اپز یشه َا ي ش يفت 1 1 0 Si Si 0 1 1 0 1 1 0 0 1 1 0 Si Si So So بؼذ اس ش يفت قبل اس ش يفت
- 26. 26 اوًاع ش يفت Logical Shift Si=0 R2 Shr R2 RTL . R1 Shl R1
- 27. 27 اوًاع ش يفت Circular Shift Si So R2 Cir R2 R1 Cil R1
- 28. 28 اوًاع ش يفت Arithmetic Shift 2 2 . asl Rn-1 OverFlow . : asr: Si=0 R n-1 R0 R n-1 R0 asl: Si R1 asl R R asr R در ضرب 2 بر تقسيم 2 R R V n n 2 1
- 29. 29 پ ٌياد ساس ي سخت افشار ي م يکزي اپز یشه َا ي ش يفت 4 S 1 0 S 1 0 S 1 0 S 1 0 A3A2 A1A0 Serial Input IR Serial Input IL S (select) 0 for shift right 1 for shift left H3 H2 H1 H0 MUX MUX MUX MUX
- 31. 31 قسمت يک مدار از محاسباتي قسمت يک مدار از منطقي S1 S0 Bi Ai S1 S0 Bi Ai Di Ei Fi Select 0 1 2 3 4x1 MUX Ai-1 Ai+1 S3 S2 S1 S0 Cin 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 x 0 1 0 1 x 0 1 1 0 x 0 1 1 1 x 1 0 x x x 1 1 x x 0 F Operation A+B A+B+1 A+B A - B A A+1 A -1 A A B A B A B A shl A shr A ALU S2 S3 Ci Ci+1 : ALU اسالیذ 21 اسالیذ 23
- 32. 32 32 Questions