MICROCONTROLLER 8051 ARCHITECTURE BASIC.ppt
- 1. MICROCONTROLLER LAB- 8051 Balaji Ramakrishna
- 2. MICROCONTROLLERS Prof. Cherrice Traver ECE/CS-352: Embedded Microcontroller Systems CPU ROM RAM I/O A single chip Subsystems: Timers, Counters, Analog Interfaces, I/O interfaces Memory
- 3. PIN DIAGRAM
- 4. COMMON MICROCONTROLLERS •Atmel •ARM •Intel •8-bit •8XC42 •MCS48 •MCS51 •8xC251 •16-bit •MCS96 •MXS296 •National Semiconductor •COP8 •Microchip •12-bit instruction PIC •14-bit instruction PIC •PIC16F84 •16-bit instruction PIC •NEC •Motorola •8-bit •68HC05 •68HC08 •68HC11 •16-bit •68HC12 •68HC16 •32-bit •683xx •Texas Instruments •TMS370 •MSP430 •Zilog •Z8 •Z86E02
- 5. THE NECESSARY TOOLS FOR A MICROPROCESSOR/CONTROLLER CPU: Central Processing Unit I/O: Input /Output Bus: Address bus & Data bus Memory: RAM & ROM Timer Interrupt Serial Port Parallel Port
- 6. MICROCONTROLLER ARCHITECTURES CPU Program + Data Address Bus Data Bus Memory Von Neumann Architecture CPU Program Address Bus Data Bus Harvard Architecture Memory Data Address Bus Fetch Bus 0 0 0 2n
- 7. “ORIGINAL” 8051 MICROCONTROLLER Oscillator and timing 4096 Bytes Program Memory 128 Bytes Data Memory Two 16 Bit Timer/Event Counters 8051 CPU 64 K Byte Bus Expansion Control Programmable I/O Programmable Serial Port Full Duplex UART Synchronous Shifter Internal data bus External interrupts subsystem interrupts Control Parallel ports Address Data Bus I/O pins Serial Input Serial Output
- 9. RAM memory space allocation in the 8051 7FH 30H 2FH 20H 1FH 17H 10H 0FH 07H 08H 18H 00H Register Bank 0 (Stack) Register Bank 1 Register Bank 2 Register Bank 3 Bit-Addressable RAM Scratch pad RAM
- 10. Memory space
- 11. BIT ADDRESSABLE RAM Figure 2-6 Summary of the 8051 on-chip data memory (RAM)
- 13. PROGRAM STATUS WORD (PSW)
- 16. INTERFACING WITH EXTERNAL ROM
- 17. EXTERNAL MEMORY
- 18. EXTERNAL MEMORY TIMING DIAGRAM
- 19. THE EA' (EXTERNAL ACCESS) PIN IS USED TO CONTROL THE INTERNAL OR EXTERNAL MEMORY ACCESS. THE SIGNAL 0 IS FOR EXTERNAL MEMORY ACCESS AND SIGNAL 1 FOR INTERNAL MEMORY ACCESS. THE PSEN' (PROGRAM STORE ENABLE) IS FOR READING EXTERNAL CODE MEMORY WHEN IT IS LOW (0) AND EA IS ALSO 0. THE ALE (ADDRESS LATCH ENABLE) ACTIVATES THE PORT 0 JOINED WITH PORT 2 TO PROVIDE 16 BIT EXTERNAL ADDRESS BUS TO ACCESS THE EXTERNAL MEMORY. THE ALE MULTIPLEXES THE P0: ALE=1 FOR LATCHING ADDRESS ON P0 AS A0-A7 IN THE 16 BIT ADDRESS BUSS, ALE=0 FOR LATCHING P0 AS DATA I/O. P0.X IS NAMED ADX BECAUSE P0 IS MULTIPLEXED FOR ADDRESS BUS AND DATA BUS AT DIFFERENT CLOCK TIME. WR' PROVIDES THE SIGNAL TO WRITE EXTERNAL DATA MEMORY RD' PROVIDES THE SIGNAL TO READ EXTERNAL DATA AND CODE MEMORY.
- 20. ACCESSING ROM USING INDEXED ADDRESSING
- 22. PORT 0
- 23. PORT1
- 24. PORT 2
- 25. PORT3
- 26. There are 4 8-bit ports: P0, P1, P2 and P3. All of them are dual purpose ports except P1 which is only used for I/O. The following diagram shows a single bit in an 8051 I/O port. When a program writes a one byte value to a port or a single bit value to a bit of a port, assigning the value to the port as follows: P1 = 0x12; or P1^2=1; P1 represents the 8 bits of port 1 and P1^2 is the pin #2 of the port 1 of 8051 defined in the reg51.h of C51, a C dedicated for 8051 family. When data is written to the port pin, it first appears on the latch input (D) and is then passed through to the output (Q) and through an inverter to the Field Effect Transistor (FET). If you write a logic 0 to the port pin(DFF Q=0), it is inverted to logic 1 and turns on the FET gate. It makes the port pin connected to ground (logic 0). If logic 1 is written to the port pin(DFF Q=1), , then it is inverted to a logic 0 and turns off the FET gate. Therefore the pin is at logic 1 because it is connected to high.
- 27. PORT P1 (Pins 1 to 8): The port P1 is a port dedicated for general I/O purpose. The other ports P0, P2 and P3 have dual roles in addition to their basic I/O function. PORT P0 (pins 32 to 39): When the external memory access is required then Port P0 is multiplexed for address bus and data bus that can be used to access external memory in conjunction with port P2. P0 acts as A0-A7 in address bus and D0-D7 for port data. It can be used for general purpose I/O if no external memory presents. PORT P2 (pins 21 to 28): Similar to P0, the port P2 can also play a role (A8-A15) in the address bus in conjunction with PORT P0 to access external memory.
- 28. PORT P3 (Pins 10 to 17): In addition to acting as a normal I/O port, P3.0 can be used for serial receive input pin(RXD) P3.1 can be used for serial transmit output pin(TXD) in a serial port, P3.2 and P3.3 can be used as external interrupt pins(INT0’ and INT1’), P3.4 and P3.5 are used for external counter input pins(T0 and T1), P3.6 and P3.7 can be used as external data memory write and read control signal pins(WR’ and RD’)read and write pins for memory access.