Microelectronics U4.pptx.ppt

CMOS Digital Integrated Circuits
Chapter 10
Semiconductor Memories
UNIT- 4 Microelectronics
1
Copyright © 2014 McGraw-Hill Education. Permission required for reproduction or display.

10.1 Introduction
Design issue
 Area efficiency cost per bit
 Access time speed
 Power consumption low-power
© CMOS Digital Integrated Circuits – 4th Edition
2

10.1 Introduction
Semiconductor memory types
3
Semiconductor Memories
Programmable ROM
(PROM)
Volatile
Dynamic RAM
(DRAM)
Static RAM
(SRAM)
Non-volatile
Mask (Fuse) ROM
Electrically Erasable
PROM (EEPROM)
Erasable PROM
(EPROM)
• Flash Memory
• Ferroelectric RAM (FRAM)
• Magnetoresistive RAM(MRAM)
• Resistive RAM(RRAM)
• Phase-change RAM(PCRAM)
• Spin Torque Transfer RAM(STT)

Characteristic Summary of Memory Devices
4
Memory type
DRAM SRAM UV EPROM EEPROM Flash FRAM
Data volatility Yes Yes No No No No
Data refresh operation Required No No No No No
Cell structure 1T-1C 6T 1T 2T 1T 1T-1C
Cell size(F2)
(F: min. feature size)
6~8 80~100
4~5(NAND)
9~10(NOR)
Cell density High Low High Low High High
Power consumption High High/low Low Low Low High
Read speed (latency) ~50 ns ~10/70 ns ~50 ns ~50 ns ~50 ns ~100 ns
Write speed ~40 ns ~5/40 ns ~10 μs ~5 ms ~(10 μs-1 ms) ~100 ns
Endurance High High High Low High High
Cost Low High Low High Low Low
In-system writability Yes Yes No Yes Yes Yes
Power supply Single Single Single Multiple Single Single
Application example
Main
memory
Cache/PDAs
Game
machines
ID card
Memory card
solid-state
disk
Smart card,
digital
camera

5
Equivalent Circuits of Memory Cells(1)
(a) DRAM (b) SRAM

(c) Mask ROM (d) EPROM (e) FRAM
6
Equivalent Circuits of Memory Cells(2)

7
Conceptual RAM Array Organization

Typical configuration of DRAM chip
(1.6Gbps 4Gb 30nm LPDDR3 w/ 8 banks)
chip size performance
The number of cells per word and bit lines Pin assignment
8
10.2 Dynamic Random Access Memory

Pin name Definition Function
CLK Clock input
Reference system clock for the operation and data
communication
CKE Clock Enable Control the clock input
CS Chip Select Activate the DRAM device from a memory cluster
RAS Row Address Strobe Latch row address and start the cell core operation
CAS Column Address Strobe
Latch column address and start the data
communication operation
WE Write Enable Activate the write operation
A0 to A14 Address input Select a data bit
DQ0 to DQ15 Data input and output Communicate data with external devices
DQMU/DQML
DQ Mask for Upper
(Lower) Byte
Mask byte data from the operations
VDD/VSS Power pins Power for DRAM core and peripheral circuits
VDDQ/VSSQ Power pins Power for DQ circuits
NC No connection
9
Definition and Function of DRAM Pins

10
Historical Evolution of DRAM Cell(1)
 Four-transistor DRAM cell
 Operations are similar to SRAM cell
 Two storage nodes
 Periodically refresh is required
 Non-destructive read operation
 Three-transistor DRAM cell
 One storage node
 One Tr. each for “read” and “write”
 Two bit lines and two word lines
(additional contacts increase area)

11
Historical Evolution of DRAM Cell(2)
 Two-transistor DRAM cell
 Explicit storage cap.
 Destructive read operation
(share with the bit line)
 Two bit lines and one word line
 One-transistor DRAM cell
 Industry-standard DRAM cell
 Destructive read operation
(share with the bit line)
 Charge restoring operation required

With only one transistor and one capacitor
 Smallest area of the all DRAM cells.
 Destructive “read” operation
major effort : large cap. cell with minimized area
(a) DRAM cell with a stacked cap. (b) DRAM cell with a trench cap.
12
DRAM Cell Types

Feb 12 Lecture on Memories (Continued)
13

Bio-inspired Computing Using ReRAM
14

Typical 3-T DRAM cell and voltage waveforms
15
Operation of Three-Transistor DRAM Cell

Base on two-phase non-
overlapping clock scheme
Φ1 : precharge phase
Φ2 : active phase
Precharge signal PC goes up
MP1 and MP2 are activated
C2 and C3 are charged up
(Steady-state values)
16
Precharge Events

17
Write “1” and Read “1” Operations
 Write “1”
 DATA is low Din remains high
 M1 turns on (WS is high)
C2 shared with C1
 C1 charge up to high
(M2 is conducting)
 Read “1”
 RS is high M3 turns on
 M2 and M3 create conducting
path from C3 to GND
 C3 discharges

18
Write “0” and Read “0” Operations
 Write “0”
 DATA is high Din goes low
 M1 turns on (WS is high)
 C1 discharges
(M2 turns off)
 Read “0”
 RS is high M3 turns on
 No conducting path
 C3 does not discharge

One explicit storage cap. and one access transistor
 The most widely used storage structure
 Bit lines are folded and precharged to half-VDD
improve noise-immunity & reduce power consumption
 Operation : “read”, “write”, “refresh”
19
Operation of One-Transistor DRAM Cell

 DRAM cell array with control circuits
 Latch amplifier to sense the small signal difference
 Bit lines and sensing nodes set to half-VDD through equalizer
20
1-T DRAM Structure

 CS shared with CBL(=initially half VDD)
 CS : VDD ½VDD+ΔV (destructive)
 BL and BLB voltage difference amplified
 BLB GND, BL VDD
storage node is recovered (restoring)
 Column switch is enabled by column
decoder (BL BL_IO, BLB BL_IOB)
 Read Amp. amplifies the voltage difference
 VPP=VDD+Vth for full charge restoration
 PSA and PSAB are sequentially activated to
reduce charge injection and short circuit current
21
DRAM Read Operation
2
S DD
BL S
C V
V
C C
 

PEQ/PSAEQ
PISOi/PISOj
Word Line
BL/BLB
PSA
PSAB
Column Select
Dout_IO/
Dout_IOB
Dout_IO
BL_IOB
BL_IO
BLB
S
VDD
VPP
VDD
VPP
VDD
1/2VDD
VDD
VDD
VDD
VDD
VDD
PISOi
PISOj
BL_IO/BL_IOB
BL
charge sharing between the cell and bit line capacitances
activation of
bit line sense amplifier
cell data restoring
(a)

 Identical sequence to normal
read operation
 Strong write driver (buffer)
to drive BL_IO, BL_IOB line cap.
faster than read operation
 Column switch is selected by
column decoder
 Bit line and cell data changed
22
DRAM Write Operation

 single bit access (different row and column addresses)
 Operation uses address multiplexing scheme (RAS and CAS)
reduce the chip package size
 RAS pull down operation start
 Falling edge of CAS data (from same word line) selected
 RAS, CAS precharge before new data access
 tRAC : memory read latency, time to read data from falling of RAS
 Length of word line is determined by refresh cycle constraint
23
Asynchronous DRAM Mode(1)

 page access
 keep the row address
 read cell of same row address
 faster read operation
 extened data-out(EDO)
 new column address is captured
at rising edge of CAS
 Read data maintain during
precharge time
 Fastest read opertaion
24
Asynchronous DRAM Mode(2)

 Four bit burst read
 Read frequency improve with
use of the system clock
 At falling edge, control signal
and addresses become active
 Pipelined based on clock to
improve throughput
 Use both of edges to improve
bandwidth (Dual Data Rate)
 Serial mode read
 Use small signal swing and
clock recovery scheme to
maximize the frequency
 Send control input as packet
 Send out data in a serial form
25
Synchronous DRAM Mode

 Contact and bit line share by
two adjacent cells
Isub: leakage through cell transistor
Itunneling: tunneling through thin dielectric
Ij: junction leakage at storage node
Icell-to-cell: leakage across the field oxide
 Isub depend on Vth
increase VSB to reduce Isub
 Itunneling is a serious issue
because thickness of
dielectric is reduced to
increase cell cap.
26
Leakage Currents in DRAM Cells
leakage sub tunneling j cell to cell
I I I I I  
   

 ROR(RAS-only refresh) refresh
 Read and restore operation
 Does not send data out
 similar to normal read
operation
 CBR(CAS-before-RAS) refresh
 row address generated by on-
chip counter
 performed periodically
 Self refresh
 period set according to
operating condition
 row address and control signal
generated by internal circuit
27
Refresh Operation
ROR refresh mode
CBR refresh mode
Self refresh mode

 Logic level of system board and memory chip are different
required to convert logic levels input/output buffers
 Input buffers
inverter type latch type differential amp type
28
DRAM Input/Output Circuits(1)

29
Characteristic Comparison of Input Buffers
Buffer type
Inverter Latch Differential
Logic threshold determination
(VIH and VIL)
By WP/WN
ratio
By Vref By Vref
Speed Slow Fastest Fast
Standby current Small Smallest Large
Sensitivity to VDD and
temperature
Large Small Small
Noise immunity Bad Good Good
Constraint None
Precharge and
activation signals
needed
None

Memory output buffers
 Need to drive large cap.
 Keep a high-impedance when chip is not selected
to prevent interference of output
PMOS pull-up structure NMOS pull-up structure
30
DRAM Input/Output Circuits(2)

 To select cell from 22M memory array, M address bits are needed
 Practically, M transistors in series is impossible
decoding scheme is composed of pre and main decoder
31
DRAM Decoder(1)

 VPP for full restoration
 Output of predecoder
boosted by level shifter
 Self-bootstrapped driver for
transferring to highly cap.
without signal degradation
 Voltage of C when main
decoder is selected
32
DRAM Decoder(2)
2
2
MN
C PP DD TN PP
MN Cparasitic
C
V V V V V V
C C
     


To detect signal difference on data lines
 Current-mirror differential
 Popular and good common-mode rejection ratio
 Large area and large power consumption
 Full CMOS latch type
 High speed, small area and low power
 Precharge signal required
 operation cannot be reversed
 Semilatch type
 Between current-mirror type and full CMOS latch type
33
Voltage Sense Amplifiers

Lowering voltage to reduce power consumption
VINT(internal voltage generator)
reduce operating current
34
Internal Voltage Regulator Circuit

Folded bit line structure with half VDD sensing scheme
 Improve noise immunity and low power consumption
 Reduce electric field across thin dielectric
bias ckt driver simulated output waveforms
35
Half VDD Voltage Generator

Subthreshold current is major source of charge decay
 Negative voltage substrate increase threshold voltage
reduce load cap. of bit line
36
Negative Substrate Bias Voltage Generator(1)
T
SB
SB
V
V
V




Timing diagram
Circuit diagram
Simulated waveforms
37
Negative Substrate Bias Voltage Generator(2)

 Stored data can be retained indefinitely
 Simple latch with two stable operating points
 Two access switches to connect 1-bit SRAM
 Poly resistor load inverter structure is more compact cell size
(resistor stack on top of cell)
 Load R trade off : low power wider noise margin, high speed
Symbolic representation Generic topology of SRAM Resistive-load SRAM
38
10.3 Static Random Access Memory(1)

 Depletion-load NMOS SRAM
 Six-transistor
(one poly and one metal layer)
 Cell size relatively small
 Static characteristics and noise margins
better than resistive-load cell
 Static power consumption
 Full CMOS SRAM
 Most popular
 Lowest static power
 Superior noise margins and switching
speed
39
10.3 Static Random Access Memory(2)

 Very small static power dissipation (limited by leakage current)
 High noise immunity (large noise margin)
 Ability to operate at lower supply
 Disadvantage : cell area slightly larger, latch-up phenomena
40
Full CMOS SRAM Cell(1)

Layout of CMOS SRAM cell Layout of a 4-bit X 4bit SRAM array,
consisting of 16 CMOS SRAM cells
41
Full CMOS SRAM Cell(2)

Two basic requirements which dictate W/L ratio
 Non-destructive data read operation
 Modify stored data during write phase
 Read Operation (0 stored)
 M3 and M1 conduct some current
 VCc
drops slightly and V1 increases
 not to turn on M2
 M3 in Saturation and M1 in linear
42
CMOS SRAM Cell Design Strategy(1)
1,max ,2
T
V V

,3 ,1
2 2
1 , , 1 1
( ) (2( ) )
2 2
n n
DD T n DD T n
k k
V V V V V V V
    
,3 , ,
3
2
,1 ,
1
2( 1.5 )
( 2 )
n DD T n T n
n DD T n
W
k V V V
L
W
k V V
L
 
  
 
 

 
 
 

 Write 0 operation (initially, 1 was stored at node 1)
 V1 must be reduced below VT,2 M2 turns off, V2 rises and V1 falls
 When V1=VT,n, M3 in linear
& M5 in saturation
43
CMOS SRAM Cell Design Strategy(2)
,5 ,3
2 2
, , , ,
(0 ) (2( ) )
2 2
p n
DD T p DD T n T n T n
k k
V V V V V V
    
,5 , ,
2
,3 ,
2( 1.5 )
( )
p DD T n T n
n DD T p
k V V V
k V V



, ,
5
2
,
3
2( 1.5 )
( )
DD T n T n
n
p DD T p
W
V V V
L
W V V
L


 
  
 
 

 
 
 

 Word line selected by row address
 Cell data kept during read
operation
 Boosted voltage not required
 Address multiplexing scheme is
not used (fast access time than
DRAM)
 Depend on applications
 ultra low power : load transistor
turns off during read operation
 high speed : remains on
44
Memory Structure of SRAM

 Read operation
 Word line enable
 One bit line discharge
(voltage change of bit line is very small)
 Sense amp. detect the voltage
difference on bit line
 Multi-stage amp. is used to improve
read speed
 Write operation
 Word line selected by row address
 Write buffer write data into cell
 Write buffer has larger current driving
capability than cell
 Write is faster than read
45
Operation of SRAM

TTL level converts into CMOS level signal
Internal voltage regulator to reduce power dissipation
to improve reliability
46
SRAM Read Operation

 Major portion of standby current
 Standby power is key parameter for low power design
 High threshold
reduction of leakage degradation of performance
Ij : junction current
data “1” to substrate
Insub and Ipsub : subthreshold leakage
turn off NMOS and PMOS
Itunneling : tunneling current
cross thin gate oxide
47
Leakage Currents in SRAM Cells

 Current-mode sense amp
widely used in SRAM
improve signal sensing speed
independent of bit line cap.
 Signal line connect to source of
latch transistor
 Current difference appears on
DL and DL
 Open-loop gain
 Current-mode sense amp:
Drawback- larger power
consumption
48
SRAM Read/Write Circuits
( 3) ( 4)
( 1) ( 2)
m m
open loop
m m
g m g m
Gain
g m g m





SRAM Cell at Low Supply Voltage
SRAM cell susceptible to variabilities
 Due to minimum device size to a minimize area
 Threshold voltage variation covered in Ch. 3 plus layout
induced threshold voltage variation
 PMOS pair (M5, M6) in SRAM cell- different VT due to NBTI
 NMOS pair (M1, M2) in SRAM cell- different VT due to PBTI
49
+ Vn -
invL - Vn +
invR
word line
bit line
① ②
bit line
Static noise margin (SNM)
 A noise tolerant voltage before
the stored data flip
 Equivalent ckt to measure SNM
 6-T SRAM cell at low supply
voltage degrades SNM
Vn: DC noise, SNM: min. DC noise which flips the
state of SRAM cell during read operation

SNM Variation due to DC Noise
How to measure SNM graphically
50
 SNM: The length of side of the smaller nested square in the two
openings of butterfly curve
 Before two Vns are fed: SNM=VS
 After Vns are fed: stable point A and unstable point B meets at D
 More Vns are applied: one common point C & the stored bits are flipped

SRAM Cell Writability
Write-trip point
 A metric for writability
 Max. bit line voltage to flip
the state of the SRAM cell
 Primarily determined by the
pull-up ratio of SRAM cell
(Ex: (W/L)5/(W/L)3 )
Variability tolerant 6T
SRAM cell
 Trade off bw. read stability
and writability
 M3 & M4 :
SNM , writability
51

8T SRAM Cell
 No secondary power
supplies
 Decouples the SRAM cell
nodes from the bit line
which enables balancing
the read & write modes
 Read operation doesn’t
affect the stored data
 6T cell has the worst SNM
in read operation where
the pass gate transistor
increases the voltage at
the ‘0’ stored
52

 Simple combinational Boolean network
 Only one word line selected at a time
 Active transistors exist at cross point
 Dynamic ROM
 use periodic precharge signal to reduce static power
53
10.4 Nonvolatile Memory

Initially, NMOS at every row-column intersection
‘1’-bits are realized by omitting drain or source connection
or gate electrode of corresponding NMOS
Layout example of a NOR ROM array
54
Layout of NOR ROM Array(1)

In reality, metal column lines laid out directly on top of
diffusion column to reduce horizontal dimension
Layout of the 4-bit X 4-bit NOR ROM array (pp. 46)
55
Layout of NOR ROM Array(2)

Every two rows share a common ground connection
Every metal to diffusion contact shared by two
adjacent devices
56
Implant-mask Programmable NOR ROM

Based on implant-mask programming
Raised threshold voltage >VOH “1”-bit
Non-implanted “0”-bit
higher core density (smaller silicon area per stored bit)
57
4-bit x 4-bit NOR ROM Array

Bit line : depletion-load NAND gate
Deactivated transistor “1”-bit
Shorted or on transistor “0”-bit
58
4-bit x 4-bit NAND ROM Array

Lowered threshold voltage < 0V “0”-bit
Much more compact than NOR ROM
Access time is slower than NOR ROM
59
Implant-mask layout of NAND ROM

Select a particular memory location in array
Row address decoder example
60
Design of Row and Column Decoders(1)

ROM array and row decoder (two adjacent NOR arrays)
61
Design of Row and Column Decoders(2)

Lower voltage for logic “0”
Realized using same layout strategy as memory array
62
Row Decoder for NAND ROM

Using NOR address decoder and NMOS pass transistor
Only one pass transistor turned on at a time
2M(M+1) transistors required
63
Column Decoder(1)

Binary selection tree decoder
NOR address decoder not needed
Reduce the number of transistors significantly
But, long data access time
64
Column Decoder(2)

Analyze the access time of a 32-kbit NOR ROM array
65
Example 10.1(1)
2
20 /
n ox
C A V
 

2
3.47 /
ox
C F cm


20 /
Poly sheet resistance square
 

 Assume 7 row address bits and 8 column address bits (128
rows and 256 columns)
 Calculate row resistance and capacitance
 Calculate row access time
66
Example 10.1(2)
10.4 /
row ox
C C W L fF bit
   
(# ) ( ) 60 /
row
R of squares Poly sheet resistance bit
   
15.36
T i
all columns
R R k
  

2.66
T i
all columns
C C pF
 

0.38 15.53
row T T
t R C ns
   

 A more accurate delay: Elmore time constant for RC ladder
circuits
 Calculate column access time
128-input NOR gate representation
67
Example 10.1(3)
256
1 1
20.52
k
row jk k jk j
k j
t R C ns where R R
 
  
 
, ,
128 ( )
1.5
column gd driver db driver
C C C
pF
  

, , 0.0118 /
gd driver db driver
where C C pF word line
 

 To calculate column access time, consider the worst-case
signal propagation delay τPHL for below inverter
68
Example 10.1(4)
18
column
t ns

38.5
access row column
t t t ns
  
(using eq. 6.18: tPHL)

 One transistor with floating gate
 Memory cell can have two states (two threshold)
 Electron accumulated at the floating gate higher threshold “1” state
 Electron removed from the floating gate lower threshold “0” state
Hot electron injection mechanism Fowler-Nordheim tunneling mechanism
(Data programming) (Data erasing)
69
10.5 Flash Memory

QFC : charge stored at floating gate
Ctotal : total cap.
CFC : cap. between floating and control gate
CFS, CFB and CFD : cap. between floating gate and source, bulk and drain
VCG and VD : voltage at control gate and drain
VT(FG) : threshold voltage to turn on the floating gate transistor
70
Equivalent Capacitive-Coupling Circuit
FG FC FD
FG CG D
total total total
Q C C
V V V
C C C
  
total FC FS FB FD
C C C C C
   
( ) ( )
total FG FD
T T D
FC FC FC
C Q C
V CG V FG V
C C C
  
( ) FG
T
FC
Q
V CG
C

  
 VFG by capacitive coupling
after VCG & VD applied
 min. VCG to turn on the
control gate transistor

 Low and high threshold voltages for control gate voltage
71
I-V Characteristic of Flash Memory

Bias conditions and configuration of NOR Cells
 F-N tunneling mechanism for erase operation
 Hot-electron injection mechanism for programming operation
72
NOR Flash Memory Cell

73
Bias Conditions of NOR Cell
Signal
Operation
Erase Programming Read
Bit line 1 Open 6V 1V
Source line 12V 0V 0V
Word line 1 0V 0V 0V

Cross-section view and configuration of NAND cells
 F-N tunneling mechanism for erase
 F-N tunneling mechanism for program
 Slower programming and read speed
but smaller area than NOR cell structure
74
NAND Flash Memory Cell

75
Bias Conditions of NAND Cell
Signal
Operation
Erase Programming Read
Select line 1 Open 5V 5V
Select line 2 Open 0V 5V
Source line Open 0V 0V
p-well 2 20V 0V 0V
n-sub 20V 0V 0V

76
Comparison between NOR and NAND
NOR NAND
Erase method F-N tunneling F-N tunneling
Programming method Hot electron injection F-N tunneling
Erase speed Slow Fast
Program speed Fast Slow
Read speed Fast Slow
Cell size Large Small
Scalability Difficult Easy
Application Embedded system Mass storage

Effective memory density can be improved
Possible state number limited by
 Available charge range
 Accuracy of programming and read operations
 Disturbance of state over time
Threshold voltage distribution of 2bits/cell storage
77
Multilevel Cell Concept

 On-chip charge pump used to generate programming voltage
 Chain of diode and cap. to charge or discharge each half cycle
78
Flash Memory Circuit
( ( 1)) ( ( ))
out in DD T DD T
V V V V MN V V MNn
 
     

Hysteresis characteristic of a ferroelectric cap.
Total charge varies as function of applied voltage
79
10.6 Ferroelectric Random Access Memory

Similar to DRAM except plate line
 Step-sensing scheme
C1 and C0 : linearly modeled
ferroelectric cap
80
Structure and Operation of FRAM
1
1
1
0
0
0
DD
BL
DD
BL
C
V V
C C
C
V V
C C
 

 
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Step-sensing scheme cause reliability issues
 Pulse sensing scheme also used with read speed penalty
Fatigue
 Capacitance charge gradually degraded with repeated use
Imprint
 Ferroelectric cap tends to stay at one state preferably when
state maintained for a long time
81
Problems of FRAM

Microelectronics U4.pptx.ppt

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