MIPI DevCon Bangalore 2017: A Developer's Guide to MIPI I3C Implementation and MIPI I3C Beyond Sensors
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The document provides a comprehensive guide to MIPI I3C, an innovative two-wire sensor interface designed to improve upon existing protocols like I2C, SPI, and UART. It covers features such as dynamic addressing, error detection, and high data rate modes, as well as implementation guidelines for integrating legacy devices and ensuring optimal performance in varied system topologies. Additionally, it discusses applications beyond sensing, including camera control and touchscreen interfaces, highlighting the benefits of efficiency and reduced latency.
MIPI DevCon Bangalore 2017: A Developer's Guide to MIPI I3C Implementation and MIPI I3C Beyond Sensors
- 1. Ken Foust Intel A Developer’s Guide to MIPI I3CSM for Sensors and Beyond
- 2. © 2017 MIPI Alliance, Inc. Outline • Introduction to MIPI I3CSM • Usages beyond sensing – MIPI Camera Control Interface (CCISM) – MIPI Touch over I3CSM – MIPI Debug for I3CSM • MIPI I3CSM feature descriptions • Implementation guidelines – Legacy Device Support – HDR Modes – Varied Topologies • Summarized good design practices 2
- 3. © 2017 MIPI Alliance, Inc. MIPI I3CSM for Ubiquitous Low Speed Interfacing • Anywhere sensors are used, MIPI I3CSM belongs • Aimed toward historical I2C, SPI and UART applications in… 3
- 4. © 2017 MIPI Alliance, Inc. What is MIPI I3CSM? • Innovative new 2-Wire Sensor interface • Key features address historical pain points – In-band Interrupt, Dynamic Addressing, Multi-Master, Standardized Commands, Time Control, Hot-Join, Error Detection and Recovery – Plus… High Data RatesLow PowerI2C Compatibility
- 5. © 2017 MIPI Alliance, Inc. Accelerometer Magnetometer Host ACCEL_INT SNS_SYNC ACCEL_INT2 Accelerometer Gyro GYRO_IRQ_N ALS/Proximity ALS_INT_N Altimeter (barometric pressure) Compass COMPASS_INT I2C_SDA I2C_CLK MISO SPI_ACTIVE SCK MOSI DRDY SLEEP Grip Sensor (ULPP) ULPP_INT DRDY ENABLE TS_I2C_SDA TS_I2C_CLK TS_S_DRDY TS_SLEEP Fingerprint ADC Touchscreen SLEEP Near Field Comm NFC_IRQ_N Accelerometer Magnetometer Host Accelerometer Gyro ALS/Proximity Altimeter (barometric pressure) Compass SENSOR_DATA SENSOR_CLK Grip Sensor (ULPP) Fingerprint ADC Touchscreen Near Field Comm MIPI I3CSM Vision? Too Many I/Os! Fragmented Interfaces!
- 6. © 2017 MIPI Alliance, Inc. Usages Beyond Sensing 6 • MIPI CCISM (Camera Control Interface) over I3CSM offers faster, lower latency and more efficient camera control with future abilities to support grouped data write and AON imaging • Current touch screen controller interfaces are fragmented • For many touch screens, MIPI Touch over I3CSM presents a converged interface option for processed and raw touch data, leveraging IBI and HDR modes • MIPI Debug for I3CSM offers a more complete closed chassis, scalable and power aware platform debug capability with minimum boundary pin count
- 7. © 2017 MIPI Alliance, Inc. MIPI I3CSM Features • I3C SDR – The Base Interface – Up to 12.5 MHz I2C-like clocking with defined Open-Drain / Push-Pull – Supports multiple classes of Devices • I3C Main Master – SDR-only Main Master • I3C Secondary Master – SDR-Only Secondary Master • I3C Slave – SDR-Only Slave • I2C slave I2C SLAVE SDA SCL I3C MAIN MASTER I3C SECONDARY MASTER I3C SLAVE I3C SLAVE I3C SECONDARY MASTER I3C SLAVE I3C SECONDARY MASTER (Slave of Main Master) I3C MAIN MASTER LEGEND I2C SLAVE I2C SLAVE 7
- 8. © 2017 MIPI Alliance, Inc. MIPI I3CSM Features • SDR Dynamic Address Assignment – Standardized procedure for dynamic assignment of 7-bit Addresses to all I3C Devices • I3C Slaves have two standardized characteristics registers and an internal 48- bit Provisional ID to aide the procedure – Legacy I2C Devices still use their static I2C Address • SDR In-band Interrupt – Slave device can issue START Request when in “Bus Available” state – Master provides Interface Clock for Slave to drive it’s Master-assigned address onto the bus – Lowest assigned address wins arbitration in Open-Drain configuration – A data payload (i.e. Mandatory Data Byte) can immediately accompany the In-band Interrupt 8
- 9. © 2017 MIPI Alliance, Inc. MIPI I3CSM Features • Error Detection and Recovery Methodology – For Master and Slave generated errors (9 Error Types identified, Parity, CRC5) • Common Command Codes – Standardized command mode with extensible set of MIPI-defined codes that can be Broadcasted and/or Directed, Read and/or Write – Standardized Command Codes • Event Enable/Disable • Activity States • Payload Mgmt • I3C Feature Mgmt (Dynamic Address Assignment, Mastership, HDR Modes, Timing Control) • Test Modes • Extensible Space (MIPI and Vendor) S or Sr 0x7E / W / ACK Command Code / T Data (Optional) (Broadcast CCC only) / T Sr or P * Example of Broadcast CCC Frame 9
- 10. © 2017 MIPI Alliance, Inc. Guidelines - Legacy I2C Device Support • Fm and Fm+ Speeds Supported • 50ns Spike Filter (tSP) Needed for 12.5MHz I3CSM Clocking • Clock Stretching is Not Allowed – I3C SCL is Push/Pull • 20mA Open Drain Drivers (IOL) are Not Used • I2C Extended Addresses (10 bit) are Not Used Legacy I2 C SDA/SCL Pins After Spike Filter Suppressed by 50ns filter Input to SDA/SCL Pins tDIG_H 0.7 X VDD 0.3 X VDD 0.7 X VDD 0.3 X VDD tSPIKE tSPIKEtDIG_L I3C SDA/SCL Pins Without Spike Filter 0.7 X VDD 0.3 X VDD *UM10204: I2C-bus specification and user manual Rev. 6 tSP: pulse width of spikes that must be suppressed by the input filter 10
- 11. © 2017 MIPI Alliance, Inc. MIPI I3CSM Features • I3C High Data Rate (HDR) Modes – Optionally supported beyond the base SDR mode: 12.5MHz, SDA/SCL • HDR-DDR: Double Data Rate • HDR-TSL/TSP: Ternary Symbol – Offer bit rates over 33Mbps at a fraction of the per bit power of I2C Fast Mode – Simple Slave-side digital implementations – Coexistent with legacy I2C Devices – Leverage rising and falling edges – Individually entered using broadcasted MIPI-defined Common Command Codes – Universally exited and restarted via MIPI-defined toggling patterns • Allows non-HDR I3C Devices to “ignore” HDR transmissions I3C Msg1 Msg2 I3C START Brdcst CCC EnterHDRx HDR Cmd HDR Data HDR Restart Pattern HDR Cmd HDR Data HDR Exit Pattern STOP SDA Restart SCL 2 2 2 2 Setup (SDA/SCL) (If Needed) Possible Restart Next Edge Confirms HDR Restart HDR Exit 11
- 12. © 2017 MIPI Alliance, Inc. MIPI I3CSM Features • HDR-DDR: Double Data Rate – Uses SCL as a clock, however Data and Commands change SDA on both SCL edges. By contrast, SDR Mode changes SDA only when SCL is Low – HDR-DDR moves data by Words, which generally contains 2 preamble bits, 2 payload bytes and 2 parity bits. 4 Word Types defined: Command, Data, CRC, and Reserved – Simple protocol: From Master to Slave From Slave to Master ACK = Acknowledge (SDA Low) NACK = Not Acknowledge (NACK) S = START Condition Sr = RESTART Condition P = STOP Condition T = Transition Bit Alternative to ACK/NACK Transition Bit (Parity Bit for CCC) ... S or Sr I3C Reserved byte (0x7E) (R/W=0) ACK Enter HDR-DDR CCC (ENTHDR0) T HDR-DDR Command HDR DDR Data (1 or more words) HDR DDR CRC HDR RESTART HDR-DDR Command HDR Data (1 or more words) HDR DDR CRC HDR Exit P SDR HDR HDR SDR Command, Data, or CRC Based on Preamble (2-bit MSB) Parity Bits P1: Odd Parity bit P0: Even Parity bit Preamble Bits Define the subsequent Word Types SDA P1 P0 D0.7 D0.6 D0.5 D0.4 D0.3 D0.2 D0.1 D0.0 D1.7 D1.6 D1.5 D1.4 D1.3 D1.2 D1.1 D1.0 P1 P0 SCL 12
- 13. © 2017 MIPI Alliance, Inc. MIPI I3CSM Features • HDR-TSL/TSP: Ternary Symbol Coding – Ternary symbol coding for pure (TSP) and I2C legacy-inclusive (TSL) systems – Given a two-wire interface with ‘simultaneous’ transitions and no traditional clock, there are 3 possible symbols available – 0, 1, 2 – At least one line must transition each period – Ideally, there are 3 possible “next” transition – Transition indices are used to efficiently encode Binary into Ternary – Simple protocol: SDA 10 SCL One symbol 11 01010011 00 HDR-TSL/TSP I2C and I3C SDR vs I3C SDR Msg1 Msg2 I3C START Brdcst CCC EnterHDRx HDR Cmd HDR Data HDR Restart Pattern HDR Cmd HDR Data HDR Exit Pattern STOP 13
- 14. © 2017 MIPI Alliance, Inc. Guidelines - HDR Modes • Enter HDR Commands Supported • HDR Exit Pattern detected by all I3C Devices • Non-HDR Devices shall ignore I3C HDR bus traffic until the HDR Exit Pattern is detected I3C Msg1 Msg2 I3C START Brdcst CCC EnterHDRx HDR Cmd HDR Data HDR Restart Pattern HDR Cmd HDR Data HDR Exit Pattern STOP HDR Exit 14
- 15. © 2017 MIPI Alliance, Inc. Guidelines - Varied Topologies • Impacts on signal transition/transit times (maximum bus frequency) – SDA/SCL drive strength: “weaker” for lower power and interference vs “stronger” for faster over larger topologies/loads – Trace length and material: short vs long and pcb vs cable – SCL/SDA pad capacitance – Clock to Data Turnaround Time (tSCO) • Legacy I2C Devices impact maximum bus frequency (MHz) – Must run I3C at speeds/pulses beyond Spike Filter or slow Bus to that of slowest I2C Device • Impacts on signal integrity/reliability – Device Location: close and far Devices can cause interference from reflections I3C Master I3C Slave I3C Slave I3C Slave Example 15
- 16. © 2017 MIPI Alliance, Inc. Summarized Good Design Practices • Thoroughly understand capability of coexistent Legacy I2C Devices – 50ns Spike Filter – Disabled Clock Stretch • Understand bus topology and performance tradeoffs Mixed (I3C and Legacy I2C Devices) vs Pure Bus (I3C Devices Only) – Trace length and material – SDA/SCL pad capacitance – Clock to Data Turnaround Time (tSCO) – Device location 16