MIPI DevCon 2021: MIPI I3C interface for the ETSI Smart Secure Platform
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The document outlines the MIPI I3C interface for the ETSI Smart Secure Platform (SSP), highlighting new market requirements such as versatility, flexibility, and high security. It details the specifications, architectures, and stakeholder benefits of the SSP, facilitating the integration and use of secure elements in various applications. Additionally, it discusses the current status and next steps for the SSP I3C implementation to enhance communication and security across multiple device platforms.
MIPI DevCon 2021: MIPI I3C interface for the ETSI Smart Secure Platform
- 1. © 2021 MIPI Alliance, Inc. Giulio Follero STMicroelectronics ETSI SCP TEC delegate MIPI I3C® Interface for the ETSI Smart Secure Platform
- 2. Presented by: For: © ETSI 2021 – All rights reserved MIPI I3C® Interface for the ETSI Smart Secure Platform Giulio Follero STMicroelectronics ETSI SCP TEC delegate MIPI DevCon 2021 29 September 2021
- 3. © ETSI 2021 – All rights reserved 3 Agenda ETSI TC Smart Card Platform (SCP) New Market Requirements Stakeholder Benefits The SSP Specifications SSP Architecture ETSI SSP I3C Status and Next Steps
- 4. © ETSI 2021 – All rights reserved 4 TC SCP is responsible for the development and maintenance of specifications for Secure Elements (SEs) in a multi-application capable environment, the integration into such an environment, as well as the secure provisioning of services making use of SEs • Home of the UICC – the most widely deployed Secure Element with billions of pieces going into the market every year just as SIM cards Visit the SCP webpage on the ETSI website https://www.etsi.org/committee/1411-scp For details of recent activities, see SCP Activity Report 2020 ETSI TC Smart Card Platform (SCP)
- 5. © ETSI 2021 – All rights reserved 5 New Market Requirements Versatility Flexibility Cost efficiency High Security SSP Smart Secure Platform (SSP) is the answer for new market needs: to provide independency to business players and update the technology proposal bearing in mind complexity and cost of the product, size of the hardware and allowing flexible implementations Objective: Better integration into the specific use case Design: Modular platform offering a core set of features and a number of options Flexible: Options selected at time of implementation, application dependent High Security: extensive set of security and certification requirements Versatility: Choice of interfaces: SPI, I2C, MIPI I3C, choice of hardware New filesystem and transport/application protocols Support of existing functions: Contactless, APDU, etc.
- 6. © ETSI 2021 – All rights reserved 6 SSP Device Makers Secure Element Providers Service Providers SoC Providers End Users Stakeholder benefits • Offer a secure execution platform • Reduce Bill of Material (BoM) • Ease design and manufacturing • Increase the Secure Element (SE) value • Extend the SE life cycle management with remote update to OS and applications • Exploit a common secure element platform to store credentials and services • Target more devices • Limit liability • Increase personal data protection • Increase privacy • Ease service accessibility • Icrease the System on Chip (SoC) value • Differentiate the SoC offer in constrained device use cases (e.g. Low Power IoT)
- 7. © ETSI 2021 – All rights reserved 7 The SSP Specifications rSSP (removable) ETSI TS 103 666-x in progress ETSI removable form factors eSSP Type 1 (embedded) ETSI TS 103 666-3 ETSI embedded form factors, SPI eSSP Type 2 (embedded) ETSI TS 103 666-4 in progress eSSP Type 1 with a primary/secondary platform architecture I3C Interface ETSI TS 103 818 in progress SPI Interface ETSI TS 103 813 iSSP (integrated) ETSI TS 103 999-2 about to be published General characteristics ETSI TS 103 999-1 SPI Interface ETSI TS 103 713 iSSP (integrated) ETSI TS 103 666-2 SE integrated in the SoC Primary Platform Secondary Platform Bundle General SSP characteristics - ETSI TS 103 666-1 General SSP characteristics Security & certification, SSP File System, Communication protocol (SCL - SSP Common Layer) and communication layers above, Physical layers SSP (Smart Secure Platform) requirements – ETSI TS 103 465 split into generic and class specific requirements REQ TEC TEST Q1- 2022 Q4- 2021
- 8. © ETSI 2021 – All rights reserved 8 SSP possible Architectures Low Level operating system High Level Operating System Framework (opt) SSP Application SSP Application Secondary Platform Bundle Primary Platform Interface Operating System Framework (opt) SSP Application SSP Application Two possible architectures • SSP software running on the SSP hardware platform • SSP software stack with Primary Platform Interface Primary Platform: hardware platform along with a low-level operating system managing the exceptions, the hardware platform resources and their accesses Secondary Platform: software platform using the primary platform interface and containing the high-level operating system on top of which the SSP applications are running Primary Platform Secondary Platform
- 9. © ETSI 2021 – All rights reserved 9 SSP possible Architectures SSP software running on the SSP hardware: Preferably if only one application needs to be addressed and when the operating system does not need to be updated. Less complexity in the implementation. SSP software stack with Primary Platform: Different applications can be hosted, thanks to clear separation between hardware (SoC), and Operating System with applications (SPB). This architecture offers a mechanism to update operating systems and applications (SPB remote download) Telecom Banking Transport ID Single Application Market Multi Application Market
- 10. © ETSI 2021 – All rights reserved 10 SSP possible Architectures Secondary Platform Bundle • Software platform using the primary platform interface and containing the high-level operating system on top of which the SSP applications are running • “Use-cases dependent” (telco, payment, automotive, transportation, etc.) • The SSP may contain multiple Secondary Platform Bundles. At most one secondary platform bundle at time shall be loaded and executed by Primary Platform, to ensure high security, (protection of sensible data), by physical isolation between bundles High Level Operating System Framework (opt) SSP Application SSP Application Secondary Platform Bundle Secondary Platform
- 11. © ETSI 2021 – All rights reserved 11 SSP Architecture – Secondary Platform SSP Application SSP Application Presentation Layer Session Layer Transport Layer Network SCL Data Link Layer (e.g. ISO 7816-3, SHDLC) Physical Layer (SPI,I2C,I3C) The Secondary Platform introduces the SSP common Layer (SCL) to be independent from the physical layer SCL can support many physical layers The following physical layers are currently specified in ETSI: • SPI • SWP • ISO • MIPI I3C (ongoing…)
- 12. © ETSI 2021 – All rights reserved 12 ETSI SSP I3C Services and Benefits of SSP I3C based • Better integration and usage of SSP in connected devices using I3C interfaces • All device components will be easily able to find the SSP and communicate directly with it. • Wider SSP application field that can use data from other devices connected to the bus Consumer market: Using I3C bus, SSP improves quality of services (speed of communication, flexibility, …) IoT market: SSP can increase security levels and decrease power consumption Automotive market: SSP can use the I3C bus of the car, providing Cryptographic and security services
- 13. © ETSI 2021 – All rights reserved 13 ETSI SSP I3C ETSI TS 103 818; SSP I3C specification content • Electrical interfaces • Physical layer • Device STATUS • Data Link Layer • Link Layer Frame • LLC Layer • Power management Logical Link Control and SHDLC MAC SCL I3C Physical Layer MAC others Physical Layer In the scope of SSP I3C spec Out of the scope of TS 103 818 spec
- 14. © ETSI 2021 – All rights reserved 14 ETSI SSP I3C ETSI SSP I3C implementation The main MIPI I3C features used in the ETSI specification • IBI support with payload • Single Data Rate • Power management • Power saving mode • Operating voltages • Dynamic Addressing • Hot-join (in case of removable SSP TBD) The SSP features in I3C • The SSP is Target Only • One SSP per system Baseband I3C Other IC’s Display Touch Fingerprint Audio MEM’s MIPI Alliance: "Specification for I3CSM - Improved Inter Integrated Circuit" Version 1.0” ETSI SSP
- 15. © ETSI 2021 – All rights reserved 15 SSP I3C Status and next Steps • The first version of SSP over I3C has been presented in ETSI • Physical and Electrical Interfaces • Mac and Data link layers under definition • Asking for a specific Device ID for the SSP in the DCR • TEST specification Q1.2021 Q2.2021 Q1.2022 Q3.2021 Start ETSI Working First Draft of ETSI TS 103 818 ETSI presentation at MIPI DevCon ETSI TS 103 818 Approval and Publication Q4.2020 Liaison Statement between ETSI and MIPI
- 16. © ETSI 2021 – All rights reserved Thank you