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SK Choi
Keysight Technologies
Next Generation MIPI Physical
Layer Design and Evaluation
Challenges
©	2017	MIPI	Alliance,	Inc.
Agenda
• New	specification	and	CTS	changes	in	2017
• Eye	diagram	tests	changes	and	challenges
– MIPI	C-PHYSM
– MIPI	D-PHYSM
– MIPI	M-PHYÒ
• SSC	test
– MIPI	D-PHYSM
2
©	2017	MIPI	Alliance,	Inc.
Specification	updates	in	MIPI	C-PHY
3
• TX	Pre-Emphasis(TxEQ option)	– from	Pre-
emphasis	method	to	de-emphasis	method
• RCLK	jitter(reference	clock	jitter)	– Annex	to	
chapter	9
• Receiver	calibration	– removing	PVT(Process,	
Voltage	and	Temperature	variation	after	Long	
LP	signal)
C-PHY	1.1	:	Approved	Feb	11,	2016
C-PHY	1.2	:	Approved	Mar	28,	2017
3
©	2017	MIPI	Alliance,	Inc.
CTS	updates	in	MIPI	C-PHY
4
CTS	1.0	:	Approved	Feb	12,	2016
CTS	1.1	:	expected	approve	Aug,	2017
• Test	1.2.21	– Tx Eye	Pattern	Test
• Test	1.4.1	– HS-TX	Differential	Voltages	
Unterminated
• Test	1.4.2	– HS-TX	Differential	Voltage	
Mismatch	Unterminated
• Test	1.4.3	– HS-TX	Single-Ended	Output	High	
Voltages	Unterminated
• Test	1.4.4	– HS-TX	Static	Common-Point	
Voltages	Unterminated
©	2017	MIPI	Alliance,	Inc.
Specification	updates	in	MIPI	D-PHY
5
• Up	to	6500Mbps	with	Short	reference	
channel	(8K	support)
• Lower	LP	voltage	level	from	1.2V	to	1V
• HS-Idle	(lower	latency)
• Programmable	Preamble(RX	PVT	calibration	
due	to	LP	signal)
D-PHY	2.0	:	Approved	Mar	8,	2016
D-PHY	2.1	:	Approved	Mar	28,	2017
©	2017	MIPI	Alliance,	Inc.
CTS	updates	in	MIPI	D-PHY
6
CTS	1.2	:	April	24, 2017
• Test	1.5.7	– HS-TX	Eye	Diagram
• Test	1.4.19	– TX	Spread	Spectrum	
Clocking(SSC)	Requirement
• ZID	open	case	test
• Direct	connection	supporting	in	HS	
continuous	mode.
CTS	v2.0/v2.1
CTS	2.0/2.1	:	expected	finished	in	October
©	2017	MIPI	Alliance,	Inc.
Specification	updates	in	MIPI	M-PHY
7
M-PHY	4.0	:	Approved	Aug	3,	2015
M-PHY	4.	2.1	:	Approved	Mar	28,	2017
• Minor	spec	clarification
• Target	BER	10-10 to	10-12
©	2017	MIPI	Alliance,	Inc.
CTS	updates	in	MIPI	M-PHY
8
CTS	3.1	:	On-going(revision	21)
CTS	4.0/4.1	:	On-going(revision	1)
• Test	1.1.7	– HS-TX	G3	and	G4 Differential	AC	
Eye	(TEYE-HS-G3/G4-TX,	VDIF-AC-HS-G3/G4-
TX)
©	2017	MIPI	Alliance,	Inc.
Agenda
• New	specification	and	CTS	changes	in	2017
• Eye	diagram	tests	changes	and	challenges
– MIPI	C-PHYSM
– MIPI	D-PHYSM
– MIPI	M-PHYÒ
• SSC	test
– MIPI	D-PHYSM
9
©	2017	MIPI	Alliance,	Inc.
Eye	Diagram	Test	- General
Refence	channelEye	diagram
MIPI	C-PHY MIPI	D-PHY MIPI	M-PHY
10
©	2017	MIPI	Alliance,	Inc.
Eye	Diagram	Test	Challenges	for	MIPI	C-PHY/D-PHY
• RTB(Reference	Termination	Board)	can’t	support	new	specifications
500Msps 1Gsps 1.5Gsps 2.0Gsps 2.5Gsps
Same	data,	+/-250mV	HS	swing,	82ps	R/F	time,	without	reference	channel
However,	eye	diagram	is	distorted	
MIPI	C-PHY	RTB MIPI	D-PHY	RTB
Click	to	add	text
sps : Symbol	Per	Second
11
©	2017	MIPI	Alliance,	Inc.
MIPI	C-PHY/D-PHY	Eye	Diagram	Test
Setup	2
Direct	connection	
to	scope(HS	only)
DUT Oscilloscope
§ Now,	PHY	WG	defines	
direct	connection	to	
oscilloscope
§ However,	RTB	is	still	
required	for	LP	to	HS	
timing	test.
MIPI	D-PHY
MIPI	C-PHY
TX	HS	Test	Setup	2
Direct	connection	to	oscilloscope
(HS,	100ohm	termination	only)
12
©	2017	MIPI	Alliance,	Inc.
Resolving	Issue	with	Direct	Connection
• Direct	connection	provide	more	accurate	result	on	tests
500Msps 1Gsps 1.5Gsps 2.0Gsps 2.5Gsps
Same	data,	+/-250mV	HS	swing,	82ps	R/F	time,	without	reference	channel
sps : Symbol	Per	Second
13
©	2017	MIPI	Alliance,	Inc.
Chip	Design	Tip	for	Testing
• New	MIPI	C-PHY	v1.1	and	D-PHY	v2.0	or	above	require	to	send	both	
Burst	mode	and	Continuous	mode	signal	on	testing,	so	it	is	good	to	
consider	to	implement	both	mode	for	easy	testing.
• If	not,	it	is	not	easy	to	get	right	test	result.
MIPI	C-PHY	CTS	Annex	B MIPI	D-PHY	CTS	Annex	B
14
©	2017	MIPI	Alliance,	Inc.
Test	Setup	Tip	1
§ Prepare	Test	Fixture	(TVB)	
with	short	routing	to	
connector	to	reducing	
fixture	line	loss	(5cm	or	less)	
or	extract	S-parameter	of	
fixture	trace	when	design	
TVB
§ To	emulate	100ohm	
termination	in	MIPI	PHY,	
please	use	external	voltage	
sourced	scope	or	probe	to	
compensate	common	mode	
voltage	drop	and	double	
current	consumption
PHY	
Chip
Typical	5cm	PCB	trace	insertion	loss
VOD_A
VOD_B
22pF
RL
RLRs
Rs
A
B
15
©	2017	MIPI	Alliance,	Inc.
Test	Setup	Tip	2
§ Use	hardware	or	software	
channel	for	eye	diagram	test,	
all	oscilloscope	vendor	
provide	easy	tool	for	
software	channel	
embedding,	using	S-
parameter	file.
§ For	MIPI	C-PHY	and	D-PHY,	it	
requires	more	than	2	lines	of	
channel	so	software	
embedding	provide	more	
price	merit	than	real	
hardware	channel,	also	
convenient	to	test
16
©	2017	MIPI	Alliance,	Inc.
MIPI	M-PHY	Eye	Diagram	Test
• Test	setup	is	same	on	both	HSG3	and	HSG4	but	testing	points	has	changed.
DUT
CH1/CH2
Oscilloscope
CH1/CH2 PKG CTLE
PLL
PLL DFE
Gear3
Gear4
MIPI	M-PHY	HS	G3/G4	test	setup
MIPI	M-PHY	HSG3/G4	Test	point
17
©	2017	MIPI	Alliance,	Inc.
MIPI	M-PHY	Embedding	Channel	+	Package	Model
DUT
CH1/CH2
Oscilloscope
CH1/CH2 PKG CTLE
PLL
PLL DFE
Gear3
Gear4
-3dB	at	5.83GHz
18
©	2017	MIPI	Alliance,	Inc.
Test	Setup	Tip	3	– and	Must	for	HS	Gear4
§ Reference	package	plus	
pad	capacitance	model	is	
not	real	material	for	using,	
so	it	is	hard	to	emulate	
with	real	PCB	or	another	
circuit,	so	MIPI	WG	
recommends	using	
software	embedding	
function	for	embedding	
reference	package	plus	
pad	capacitance	model	
19
©	2017	MIPI	Alliance,	Inc.
MIPI	M-PHY	RX	Equalizer-CTLE
• Not	likely	another	application,	M-PHY	CTLE	has	vary	wide	range	of	zero	pole	value	and	
Adc value
What	if	A	company	think	2.5dB	Adc +	400MHz	Fz is	
optimal	CTLE	value
B	company	think	0dB	Adc +	400MHz	Fz is	optimal	
CTLE	value?
Does	it	correlated	between?
20
©	2017	MIPI	Alliance,	Inc.
MIPI	M-PHY	RX	Equalizer-CTLE
Same	waveform	but	only	change	Adc value	from	2.5dB	to	0dB
2.5dB	Adc case
Fz =	400MHz
0dB	Adc case
Fz =	400MHz
Adc :	CTLE	DC	gain
Fz :	CTLE	zero	frequency
21
©	2017	MIPI	Alliance,	Inc.
MIPI	M-PHY	RX	Equalizer-DFE
Also	Oscilloscope’s	DFE	setting	is	not	favor	to	the	customer.
22
©	2017	MIPI	Alliance,	Inc.
MIPI	M-PHY	RX	Equalizer-DFE
Also	Oscilloscope’s	DFE	setting	is	not	favor	to	the	customer.
Tap	=		VDFE_RX/Amplitude
Amplitude	or	
upper/lower	
target	is	voltage	
value	after	CTLE	
applied.	Not	
direct	VDEF_RX	
value
23
©	2017	MIPI	Alliance,	Inc.
MIPI	M-PHY	RX	Equalizer-DFE
40mV	VDEF_RX 60mV	VDEF_RX
40mV/133mV
=0.30075
60mV/133mV
=0.45112
VDEF_RX	:	DFE	feedback	voltage	signal
24
©	2017	MIPI	Alliance,	Inc.
Test	Setup	Tip	4
Use	SigTest tool	
Commonly	used	for	High	speed	digital	interface
• USB
• PCIe
Provide	similar	result	between	oscilloscopes
A	company B	company
25
©	2017	MIPI	Alliance,	Inc.
Agenda
• New	specification	and	CTS	changes	in	2017
• Eye	diagram	tests	changes	and	challenges
– MIPI	C-PHYSM
– MIPI	D-PHYSM
– MIPI	M-PHYÒ
• SSC	test
– MIPI	D-PHYSM
26
©	2017	MIPI	Alliance,	Inc.
SSC	(Spread	Spectrum	Clocking)	- General
SSC	onSSC	off
Peak	power	:	
-6dBm	=	
112mV
Peak	power	:	
-22dBm	=	
17.8mV
§ SSC	makes	distribution	of	RF	power	on	signal	so	that	it	can	
reduce	interruption	to	another	signals	like	wireless	signal.
§ Now	MIPI	D-PHY	fundamental	frequency	is	over	2GHz	
bandwidth,	where	lots	of	wireless	signals	have	used.	
§ Because	of	Clock	line	in	MIPI	D-PHY,	SSC	feature	is	required.	
Up	to	4.5Gbps
Up	to	6.5Gbps
Mobile	Wireless	bandwidth
27
©	2017	MIPI	Alliance,	Inc.
SSC	(Spread	Spectrum	Clocking)	Test	in	MIPI	D-PHY
SSC	modulation	frequency
SSC	modulation	deviation
SSC	df/dt
28
©	2017	MIPI	Alliance,	Inc.
SSC	in	MIPI	D-PHY	Specification
Requirements
29
©	2017	MIPI	Alliance,	Inc.
Chip	Design	Tip	for	Testing
• For	SSC	(spread	spectrum	clocking),	Designer	must	implement	Chip	
can	enable	and	disable	SSC	transmission.
30
©	2017	MIPI	Alliance,	Inc.
Test	Setup	Tip	5	
Source	:	Wikipedia
2nd order	Butterworth	filter
=	40dB/decade
w0	=	cutoff	frequency
Use	2nd order	Butterworth	filter	to	meet	SSC	df/dt test	condition § Some	of	Digital	
oscilloscope	are	possible	
to	use	Matlab code	in	the	
oscilloscope	itself	so	that	
Matlab can	apply	
complicated	filter	function.	
31
MIPI DevCon Bangalore 2017: Next generation MIPI Physical Layer Design and Evaluation Challenges

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MIPI DevCon Bangalore 2017: Next generation MIPI Physical Layer Design and Evaluation Challenges