23. What is Microcontroller??
• A microcontroller is a compact
integrated circuit(IC) designed to do
a specific operation in an embedded
system.
• An embedded system is a
specialized computer system—a
combination of a computer
processor, computer memory, and
input/output peripheral devices—
that has a dedicated function within
a larger mechanical or electronic
system.
32. • Home
– Appliances, intercom, telephones, security systems, garage door
openers, fax machines, TVs, cable TV tuner, VCR, remote controls,
video games, cellular phones, musical instruments, sewing
machines, lighting control, camera, microwave ovens, Washing
machines etc.
• Office
– Telephones, security systems, fax machines, copier, printers etc.
• Auto
– Engine control, Air bag, ABS, Power window, Button start
– instrumentation, security system, transmission control, music
system, climate control, keyless entry, paint shop robots, welding
robots, CNC machines
33. Why do we need to learn
Microprocessors/controllers?
• The microprocessor is the core of computer
systems.
• Nowadays many communication, digital
entertainment, portable devices, are
controlled by them.
• A designer should know what types of
components he needs, ways to reduce
production costs and product reliable.
34. Different aspects of a microprocessor/
Microcontroller
Hardware : Interface to the real world
Software : order how to deal with inputs
35. The necessary tools for a
microprocessor/Microcontroller
CPU: Central Processing Unit
I/O: Input /Output
Bus: Address bus & Data bus
Memory: RAM & ROM
Timer/Counters
Interrupt
Serial Port
38. Difference Microcontroller Vs Microprocessor
Sl. No. Microcontroller Microprocessor
1 Microcontroller having inbuilt RAM or ROM and
inbuilt timer.
Do not have inbuilt RAM or ROM and timer.
2 Input and output ports are available. Input and output ports are not available, requires extra
device.
3 Inbuilt serial port. Do not have inbuilt serial port, requires 8250 device.
4 Separate memory to store program and data. Program and data are stored in same memory.
5 Many functions pins on the IC. Less multifunction pins on IC.
6 Most of the micro controllers have power saving modes
like idle mode and power saving mode. This helps to
reduce power consumption even further.
Most of the microprocessors do not have power saving
features
7 Used mainly in single purpose device like washing
machine, MP3 players
Mainly used in General personal computers
8
Micro controllers are based on Harvard architecture
where program memory and Data memory are separate
Microprocessors are based on Von Neumann
model/architecture where program and data are stored
in same memory module
9 Since external components are low, total power
consumption is less and can be used with devices
running on stored power like batteries.
Due to external components, the entire power
consumption is high. Hence it is not suitable to used
with devices running on stored power like batteries.
39. 1. Meeting the computing needs of the task
efficiently and cost effectively
speed, the amount of ROM and RAM, the number of
I/O ports and timers, size, packaging, power
consumption
easy to upgrade
cost per unit
2. Availability of software development tools
assemblers, debuggers, C compilers, emulator,
simulator, technical support
3. Wide availability and reliable sources of the
microcontrollers.
Three criteria in Choosing a
Microcontroller
40. Computer Architecture
The two basic architectures in the field of computer
architecture to explain the way of memory and process
units in a computer system.
•Von Neumann architecture
•Harvard architecture
41. Von Neumann Architecture
• Von Neumann Architecture is
a digital computer architecture
whose design is based on the
concept of stored program
computers where program
data and instruction data are
stored in the same memory.
• This architecture was
designed by the famous
mathematician and physicist
John Von Neumann in 1945.
42. Advantages of Von Neumann
Architecture
• Simplicity: The fact that all data and instructions are
stored in a single memory space helps the process of
designing a computer system as there is no need to
create complicated systems of routing since pathways
may co-incide.
• Cost-Effective: A smaller number of components is
needed as compared to the other architectural designs
hence more economical.
• Flexibility: A program can Always be changed or altered
without experiencing a change in some underlying
physical aspects such as the circuitry.
43. Disadvantages of Von
Neumann Architecture
• Bottleneck Issues: The shared bus can be a problem
because the data and control instructions cannot be
obtained simultaneously and therefore it becomes slow.
• Memory Corruption: Since the data and instructions
reside in the same memory, then there is a temptation of
one erasing the other thereby producing system faults.
44. Harvard Architecture
• Harvard Architecture is the
digital computer architecture
whose design is based on the
concept where there are
separate storage and
separate buses (signal path)
for instruction and data.
• It was basically developed to
overcome the bottleneck of
Von Neumann Architecture.
45. Advantages of Harvard
Architecture
• Faster Processing: The availability of two buses for data
and instructions avoids a problem of contention where only
one bus is used and this enhances the velocity of the system.
• Improved Security: In this way the chance of memory
corruption is at least cut in half since data is not stored in the
same locations as instructions.
• Efficient Use of Resources: It enables the use of different
memory for data and for instructions of different sizes as this
help in optimal utilization of the buses and other resources.
46. Disadvantages of Harvard
Architecture
• Complexity: The design and the implementation of this type
are more intricate, thus necessitating other hardware
facilities.
• Higher Cost: Since the concept of Harvard architecture
calls for two sets of memory and two separate buses, their
implementation costs are comparatively high than Von
Neumann architecture.
• Less Flexibility Competitors: Changing or even improving
the system can also be a little tricky because of the different
memory regions.
48. VON NEUMANN ARCHITECTURE HARVARD ARCHITECTURE
It is ancient computer architecture
based on stored program computer
concept.
It is modern computer architecture
based on Harvard Mark I relay based
model.
Same physical memory address is
used for instructions and data.
Separate physical memory address is
used for instructions and data.
There is common bus for data and
instruction transfer.
Separate buses are used for
transferring data and instruction.
Two clock cycles are required to
execute single instruction.
An instruction is executed in a single
cycle.
It is cheaper in cost.
It is costly than Von Neumann
Architecture.
CPU can not access instructions and
read/write at the same time.
CPU can access instructions and
read/write at the same time.
It is used in personal computers and
small computers.
It is used in micro controllers and
signal processing.
49. RISC and CISC in Computer
Organization
• RISC(Reduced Instruction Set Computing) is the way to
make hardware simpler.
• CISC(Complex Instruction Set Computing) is the single
instruction that handles multiple work.
50. Reduced Instruction Set
Architecture (RISC)
• The main idea behind this is to simplify hardware by
using an instruction set composed of a few basic steps
for loading, evaluating, and storing operations just like a
load command will load data, a store command will store
the data.
51. Characteristics of RISC
• Simpler instruction, hence simple instruction decoding.
• Instruction comes undersize of one word.
• Instruction takes a single clock cycle to get executed.
• More general-purpose registers.
• Simple Addressing Modes.
• Fewer Data types.
• A pipeline can be achieved.
52. Advantages of RISC
• Simpler instructions: RISC processors use a smaller
set of simple instructions, which makes them easier to
decode and execute quickly. This results in faster
processing times.
• Faster execution: Because RISC processors have a
simpler instruction set, they can execute instructions
faster than CISC processors.
• Lower power consumption: RISC processors consume
less power than CISC processors, making them ideal for
portable devices.
53. Disadvantages of RISC
• More instructions required: RISC processors require
more instructions to perform complex tasks than CISC
processors.
• Increased memory usage: RISC processors require
more memory to store the additional instructions needed
to perform complex tasks.
• Higher cost: Developing and manufacturing RISC
processors can be more expensive than CISC
processors.
54. Complex Instruction Set
Architecture (CISC)
• The main idea is that a single instruction will do all
loading, evaluating, and storing operations just like a
multiplication or INC command will do stuff like loading
data, evaluating, and storing it, hence it’s complex.
55. Characteristics of CISC
• Complex instruction, hence complex instruction
decoding.
• Instructions are larger than one-word size.
• Instruction may take more than a single clock cycle to
get executed.
• Less number of general-purpose registers as operations
get performed in memory itself.
• Complex Addressing Modes.
• More Data types.
56. Advantages of CISC
• Reduced code size: CISC processors use complex
instructions that can perform multiple operations,
reducing the amount of code needed to perform a task.
• More memory efficient: Because CISC instructions are
more complex, they require fewer instructions to perform
complex tasks, which can result in more memory-
efficient code.
• Widely used: CISC processors have been in use for a
longer time than RISC processors, so they have a larger
user base and more available software.
57. Disadvantages of CISC
• Slower execution: CISC processors take longer to
execute instructions because they have more complex
instructions and need more time to decode them.
• More complex design: CISC processors have more
complex instruction sets, which makes them more
difficult to design and manufacture.
• Higher power consumption: CISC processors
consume more power than RISC processors because of
their more complex instruction sets.
58. • CISC approach: There will be a single command or
instruction for this like INC which will perform the task.
• RISC approach: Here programmer will write the first
load command to load data in registers then it will use a
suitable constant and then it will store the result in the
desired location.
59. RISC CISC
Focus on software Focus on hardware
Transistors are used for more registers
Transistors are used for storing complex
Instructions
Fixed sized instructions Variable sized instructions
Requires more number of registers Requires less number of registers
Code size is large Code size is small
An instruction executed in a single clock
cycle
Instruction takes more than one clock cycle
An instruction fit in one word.
Instructions are larger than the size of one
word
The number of instructions and addressing
modes are less as compared to CISC.
The number of instructions and addressing
modes are more as compared to RISC.
It consumes the low power. It consumes more/high power.
RISC is highly pipelined. CISC is less pipelined.
60. Block Diagram of Microcontroller
CPU
On-chip
RAM
On-chip
ROM for
program
code
4 I/O Ports
Timer 1
Serial
Port
OSC
Interrupt
Control
External interrupts
Timer 0
Timer/Counter
Bus
Control
TxD RxD
P0 P1 P2 P3
Address/Data
Counter
Inputs
63. Architectural Components of 8051
• Arithmetic Logical Unit(ALU): ALU can perform arithmetic
and logic functions on 8-bit variables.
• Internal RAM: 8051 has 128 bytes which is divided into
o Working registers [00 – 1F]
o Bit addressable memory area [20 – 2F]
o General purpose memory area (Scratch pad memory) [30-7F]
• Internal ROM: 8051 has 4 K Bytes. The address space is from
0000 to 0FFFh.
o If the program size is more than 4 K Bytes 8051 will fetch the code
automatically from external memory.
64. • I/O Ports: It has 4 ports (P0-P3).
• Bus: Address bus (16 bit) & Data bus (8 bit).
• Timer/Counters: 2 Timers of 16 bit.
• Interrupt and Serial Port: It has 2 External Interrupts (INT0 and
INT1) and 3 Internal Interrupts (TI1, TI0 and Serial Interrupt).
• Registers: It has general purpose and Special purpose Registers.
Architectural Components of 8051
65. Salient features of 8051
microcontroller
8-bit CPU.
On chip clock oscillator.
4K bytes of internal program memory [ROM].
128 bytes of internal data memory [RAM].
64 Kbytes of external program memory address space .
64 Kbytes of external data memory address space.
32 bit directional I/O lines (can be used as four 8-bit ports or 32
individually addressable I/O lines).
Two 16 Bit Timer/Counter :T0, T1
Full Duplex serial data receiver/transmitter.
Four Register banks (RB0-RB3) with 8 registers in each bank.
66. 16 bit Program counter (PC) and a data pointer (DPTR).
8 bit Program Status Word (PSW).
8 bit Stack Pointer.
Five vector interrupt structure (RESET not considered as an
interrupt).
8051 CPU consists of 8 bit ALU with associated registers like
accumulator ‘A’, B register, PSW, 16 bit program counter,
stack pointer.
Quartz Crystal Oscillator that generates the clock pulses by
which all internal operations are synchronized.
Salient features of 8051
microcontroller (Cont..)
68. Pins of 8051 （ 1/4 ）
• Vcc （ pin 40 ）：
-Vcc provides supply voltage to the chip.
-The voltage source is +5V.
• GND （ pin 20 ）： ground
• XTAL1 and XTAL2 （ pins 19,18 ）
69. XTAL Connection to 8051
C2
30pF
C1
30pF
XTAL2
XTAL1
GND
Using a quartz crystal oscillator
We can observe the frequency on the XTAL2 pin.
70. Pins of 8051
• RST （ pin 9 ）： reset
–It is an input pin and is active
high （ normally low ） .
• The high pulse must be high at least 2
machine cycles.
– It is a power-on reset.
• Upon applying a high pulse to RST, the
microcontroller will reset and all values in
registers will be lost.
71. Pins of 8051
/EA （ pin 31 ）： external access. It can’t be left
unconnected
– There is no on-chip ROM in 8031 and 8032 .
– The /EA pin is connected to GND to indicate the code
is stored externally.
– /PSEN ＆ ALE are used for external ROM.
– For 8051, /EA pin is connected to Vcc.
– “/” means active low.
/PSEN （ pin 29 ）： program store enable
– Reads the external program memory. This is an output
pin and is connected to the OE pin of the ROM.
72. Pins of 8051
ALE （ pin 30 ）： Address Latch Enable
–It is an output pin and is active high.
–8051 port 0 provides both address and
data.
•I/O port pins
–The four ports P0, P1, P2, and P3.
–Each port uses 8 pins.
73. Pins of I/O Port
The 8051 has four I/O ports
– Port 0 （ pins 32-39 ）： P0 （ P0.0 ～ P0.7 ）
– Port 1 （ pins 1-8 ） ： P1 （ P1.0 ～ P1.7 ）
– Port 2 （ pins 21-28 ）： P2 （ P2.0 ～ P2.7 ）
– Port 3 （ pins 10-17 ）： P3 （ P3.0 ～ P3.7 ）
– Each port has 8 pins.
• Named P0.X （ X=0,1,...,7 ） , P1.X, P2.X, P3.X
• Ex ： P0.0 is the bit 0 （ LSB ） of P0
• Ex ： P0.7 is the bit 7 （ MSB ） of P0
• These 8 bits form a byte.
Each port can be used as input or output (bi-direction).
74. Module-01
8051 Architecture
Registers
General Purpose Registers: There are total 34 GPRs.
Special Function/purpose Registers:
– Program Counter (PC)
– Data Pointer (DPTR)
– Program Status Word (PSW)
– Stack Pointer (SP)
– P0, P1, P2, P3 - Input/Output Registers
76. Registers in 8051
1. CPU Registers
2. I/O Port Registers
3. Timer Registers
4. Serial Registers
5. Interrupt Registers
Accumulator (ACC)
B Registers (B)
Program Counter (PC)
DPTR (Data Pointer Register)
Program Status Word Register (PSW)
Stack Pointer
Port-0 to Port-03
TMOD (Timer Mode Register)
TCON (Timer Control Register)
SCON (Serial Control Register)
SBUF (Serial Buffer Register)
PCON (Power Control Register)
IE (Interrupt Enable)
IP (Interrupt Priority)
79. Registers in 8051 Microcontroller
General Purpose Registers
•Accumulator
•B Register
•R Registers (R0-R7)
Special Function Registers
•Program Counter (PC)
•Data Pointer (DPTR)
•Program Status Word (PSW)
•Stack Pointer (SP)
•P0, P1, P2, P3 - Input/Output Registers
•Timer Registers T0 and T1
•Timer Control (TCON) Register
•TMOD Register (Timer Mode)
•SBUF register
•Serial Port Control (SCON) Register
•Power Control (PCON) Register
•IE (Interrupt Enable) Register
•IP (Interrupt Priority) Register
80. General Purpose Registers in 8051
• Totally 34 general purpose registers or working registers.
They are used to store data.
• Two of these ACC and B Registers hold results of many
instructions, particularly arithmetic and logical operations of
8051 CPU.
• The other 32 are in four register banks, RB0 –RB3 of eight
registers each.
81. Accumulator and B Register
Accumulator:
•The Accumulator (A register) is used for many operations like
Addition, Subtraction, Multiplication, Division and Boolean
bit logical operations.
•It is also used for data transfer between 8051 and external
memories, I/O devices.
B Register:
•The B register is used to do arithmetic operations such as
multiplication and division with Accumulator.
•B register may be used to store the data and it has no other
functions.
82. R Registers (R0-R7)
• These registers are from the data
memory location starting from 00h.
There are 4 register banks each
consisting of eight 8-bit registers as
shown in diagram.
• R registers is a common name for
8 general-purpose registers (R0,
R1, R2 …R7). Similar to the
accumulator, they are used for
temporary storing variables and
intermediate results during
operation.
Which one of these banks is to be active
depends on two bits of the PSW Register.
83. Special Function Registers in 8051
• Programmers should not use the addresses in the range 80H to
FFH (other than SFR) as it is used by INTEL / ATMEL
CORPORATION for expansion functions of 8051.
86. Program Counter (PC)
• Program instruction bytes are fetched from locations in the
memory that are addressed by the PC.
• The PC is automatically incremented after every instruction
byte is fetched.
• The PC is the only register that does not have an internal
address.
• Since PC is 16 bit in 8051 can access program address from
0x0000 to 0xFFFF, up to 64KB.
• After Reset. PC always point to 0x0000 of the program
memory.
87. Data Pointer (DPTR)
• The Data Pointer (DPTR) is the 8051 only user-accessible 16-
bit (2-byte) register.
• DPTR, as the name suggests, is used to point to data. It is used
by a number of commands which allow the 8051 to access
external memory.
• When the 8051 accesses external memory it will access
external memory at the address indicated by DPTR.
88. Program Status Word (PSW)
• Flags are single bit register and used to store the result of
certain function after executing instruction.
• PSW register in 8051 microcontroller contains math flags and
they are Carry(CY), Auxiliary Carry (AC), Over flow (OV),
and Parity (P).
• The PSW is accessible fully as an 8-bit register, with the
address D0H.
89. • Parity bit (P)
• This parity flag bit is used to show the number of 1s in the
accumulator only. If the accumulator register contains an
odd number of 1s, then this flag set to 1.
• If accumulator contains even number of 1s, then this flag
cleared to 0.
Program Status Word (PSW)
90. • Overflow flag (OV)
• This flag is set during ALU operations, to indicate overflow in the
result. It is set to 1 if there is a carry out of either the D7 bit or the
D6 bit of the accumulator.
• Overflow flag is set when arithmetic operations such as add and
subtract result in sign conflict.
• The conditions under which the OV flag is set are as follows:
Positive + Positive = Negative
Negative + Negative = Positive
Positive – Negative = Negative
Negative – Positive = Positive
Program Status Word (PSW)
91. • Register bank select bits (RS1 and RS0)
• These two bits are used to select one of four register banks
of RAM. By setting and clearing these bits, registers R0-R7
are stored in one of four banks of RAM as follows.
• These bits are user-programmable. They can be set by the
programmer to point to the correct register banks.
• The register bank selection in the programs can be changed
using these two bits. RS1 RS0
Bank
Selected
Address of
Registers
0 0 Bank 0 00h-07h
0 1 Bank 1 08h-0Fh
1 0 Bank 2 10h-17h
1 1 Bank 3 18h-1Fh
Program Status Word (PSW)
92. • General-purpose flag (F0)
• This is a user-programmable flag; the user can program and
store any bit of his/her choice in this flag, using the bit
address.
• Auxiliary carry flag (AC)
• It is used in association with BCD arithmetic. This flag is
set when there is a carry out of the D3 bit of the
accumulator.
Program Status Word (PSW)
93. • Carry flag (CY)
• This flag is used to indicate the carry generated after
arithmetic operations. It can also be used as an
accumulator, to store one of the data bits for bit-related
Boolean instructions.
Program Status Word (PSW)
94. Stack Pointer (SP)
• The register to access the stack is called Stack Pointer.
• The stack pointer (SP) is an 8-bit register within the SFR area,
with the address 81H and it can point an address location
between 00h to 7Fh.
• After reset it is initialized to the value 07H.
• Stack is used to store return address during ISRs and
Subroutines.
• Stack is also used by programmer using PUSH and POP
instructions.
95. Stack Pointer (SP)
Example: WAP in assembly language for PUSH operation
0000h
MOV 08h, #21h
MOV 09h, #56h
PUSH 00h
PUSH 01h
END
96. Stack Pointer (SP)
000H
MOV 00H, #12H
MOV 01H, #32H
POP 1FH
POP 0EH
END
Example: WAP in assembly language for PUSH operation
98. P0, P1, P2, P3 - I/O Registers
• Microcontroller 8051 has 4 ports. Each port is of 8-bit and can
works as input as well as output.
• Port bits will be configured as inputs or outputs.
• If a bit is cleared (0), the appropriate pin will be configured as
an output, while if it is set (1), the appropriate pin will be
configured as an input.
• Upon reset and power-on, all port bits are set (1), which means
that all appropriate pins will be configured as inputs.
99. A Pin of Port 1
A Pin of Port 1
8051 IC
D Q
Clk Q
Vcc
Load(L1)
Read latch
Read pin
Write to latch
Internal CPU
bus
M1
P1.X
pin
P1.X
TB1
TB2
100. Writing “1” to Output Pin P1.X
Writing “1” to Output Pin P1.X
D Q
Clk Q
Vcc
Load(L1)
Read latch
Read pin
Write to latch
Internal CPU
bus
M1
P1.X
pin
P1.X
2. output pin is
Vcc
1. write a 1 to the pin
1
0 output 1
TB1
TB2
101. Writing “0” to Output Pin P1.X
Writing “0” to Output Pin P1.X
D Q
Clk Q
Vcc
Load(L1)
Read latch
Read pin
Write to latch
Internal CPU
bus
M1
P1.X
pin
P1.X
2. output pin is
ground
1. write a 0 to the pin
0
1 output 0
TB1
TB2
102. Reading “High” at Input Pin
Reading “High” at Input Pin
D Q
Clk Q
Vcc
Load(L1)
Read latch
Read pin
Write to latch
Internal CPU bus
M1
P1.X pin
P1.X
8051 IC
2. MOV A,P1
external pin=High
1. write a 1 to the pin MOV
P1,#0FFH
1
0
3. Read pin=1 Read latch=0
1
TB1
TB2
103. Reading “Low” at Input Pin
Reading “Low” at Input Pin
D Q
Clk Q
Vcc
Load(L1)
Read latch
Read pin
Write to latch
Internal CPU bus
M1
P1.X pin
P1.X
8051 IC
2. MOV A,P1
external pin=Low
1. write a 1 to the pin
MOV P1,#0FFH
1
0
3. Read pin=1 Read latch=0
0
TB1
TB2
104. Other Pins
Other Pins
• P1, P2, and P3 have internal pull-up resisters.
– P1, P2, and P3 are not open drain.
• P0 has no internal pull-up resistors and does not connect to Vcc
inside the 8051.
– P0 is open drain
• However, for a programmer, it is the same to program P0, P1, P2
and P3.
105. A Pin of Port 0
A Pin of Port 0
8051 IC
D Q
Clk Q
Read latch
Read pin
Write to latch
Internal CPU
bus
M1
P0.X
pin
P0.X
TB1
TB2
1. write a 1 to the pin
1
0
Output pin
floating
106. Port 0 with Pull-Up Resistors
Port 0 with Pull-Up Resistors
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
Vcc
10 K
Port
0
107. Timer Registers T0 and T1
• Microcontroller 8051 has two timer/counters namely
timer 0 (T0) and timer 1 (T1).
• Size of each timer is 16 bits wide. Since the architecture
of 8051 is 8 bits, the timers are separated into two 8-bit
registers.
• The timer 0 is divided into low byte of timer 0 (TL0)
and high byte of timer 0 (TH0).
• Same way timer 1 as TL1 and TH1.
109. • The timer registers TL0, TL1, TH0 and TH1 can be addressed
by its location like any other registers. Since the timer is
virtually 16-bit register, the largest value it can store is 65535.
• In case of exceeding this value, the timer will be automatically
cleared and counting starts from 0. This condition is called an
overflow.
• Two registers TMOD and TCON are closely connected to this
timer and control its operation.
Timer Registers T0 and T1
110. Timer Control (TCON) Register
• TCON register is also one of the registers whose bits are
directly in control of timer operation.
• Only 4 bits of this register are used for this purpose, while
rest of them is used for interrupt control to be discussed
later.
112. TF1 bit is automatically set on the Timer 1 overflow.
TR1 bit enables the Timer 1.
•1 – Timer 1 is enabled.
•0 – Timer 1 is disabled.
TF0 bit is automatically set on the Timer 0 overflow.
TR0 bit enables the timer 0.
•1 – Timer 0 is enabled.
•0 – Timer 0 is disabled.
Timer Control (TCON) Register
113. TMOD Register (Timer Mode)
• The TMOD register selects the operational mode of the timers
T0 and T1.
• The low 4 bits (bit0 – bit3) refer to the timer 0, while the high
4 bits (bit4 – bit7) refer to the timer 1.
114. •GATE1 enables and disables Timer 1 by means of a signal
brought to the INT1 pin (P3.3):
•1 – Timer 1 operates only if the INT1 bit is set.
•0 – Timer 1 operates regardless of the logic state of the
INT1 bit.
•C/T1 selects pulses to be counted up by the timer/counter 1:
•1 – Timer counts pulses brought to the T1 pin (P3.5).
•0 – Timer counts pulses from internal oscillator.
•T1M1, T1M0 These two bits select the operational mode of the
Timer 1.
TMOD Register (Timer Mode)
116. GATE0 enables and disables Timer 0 using a signal brought to
the INT0 pin (P3.2):
•1 – Timer 0 operates only if the INT0 bit is set.
•0 – Timer 0 operates regardless of the logic state of the
INT0 bit.
•C/T0 selects pulses to be counted up by the timer/counter 0:
•1 – Timer counts pulses brought to the T0 pin (P3.4).
•0 – Timer counts pulses from internal oscillator.
•T0M1, T0M0 These two bits select the operational mode of the
Timer 0.
TMOD Register (Timer Mode)
118. Serial Port Control (SCON)
Register
• Serial port must be configured prior to being used. In other
words, it is necessary to determine how many bits is contained
in one serial “word”, baud rate and synchronization clock
source.
• The whole process is in control of the bits of the SCON
register (Serial Control).
119. •SM0 – Serial port mode bit 0 is used for serial port mode
selection.
•SM1 – Serial port mode bit 1.
•SM2 – Serial port mode 2 bit, also known as multiprocessor
communication enable bit.
•REN – Reception Enable bit enables serial reception when set.
When cleared, serial reception is disabled (done by software).
Serial Port Control (SCON)
Register
120. •TB8 – Transmitter bit 8. Since all registers are 8-bit wide, this
bit solves the problem of transmitting the 9th
bit in modes 2 and 3.
• RB8 – Receiver bit 8 or the 9th
bit received in modes 2 and 3.
Cleared by hardware if 9th
bit received is a logic 0.
•TI – Transmit Interrupt flag is automatically set at the moment
the last bit of one byte is sent. It’s a signal to the processor that
the line is available for a new byte transmitted. It must be cleared
from within the software.
•RI – Receive Interrupt flag is automatically set upon one byte
receive.
Serial Port Control (SCON)
Register
121. PCON register
The purpose of the Register PCON bits is:
•SMOD Baud rate is twice as much higher by setting this bit.
•GF1 General-purpose bit (available for use).
•GF0 General-purpose bit (available for use).
•PD Set bit, the microcontroller enters the Power Down.
•IDL By setting this bit the microcontroller enters the Idle.
122. IE (Interrupt Enable) Register
EA – global interrupt enable/disable:
•0 – disables all interrupt requests.
•1 – enables all individual interrupt
requests.
ES – enables or disables serial interrupt:
•0 – UART system cannot generate an
interrupt.
•1 – UART system enables an interrupt.
ET1 – bit enables or disables Timer 1
interrupt:
•0 – Timer 1 cannot generate an
interrupt.
•1 – Timer 1 enables an interrupt.
EX1 – bit enables or disables external
1 interrupt:
ET0 – bit enables or disables timer 0
interrupt:
•0 – Timer 0 cannot generate an
interrupt.
•1 – enables timer 0 interrupt.
EX0 – bit enables or disables external
0 interrupt:
123. IP (Interrupt Priority) Register
PS – Serial Port Interrupt priority bit
PT1 – Timer 1 interrupt priority
PX1 – External Interrupt INT1 priority
PT0 – Timer 0 Interrupt Priority
PX0 – External Interrupt INT0 Priority
134. Addressing Modes
Addressing Modes
Addressing modes specifies where the
data (operand) is. They specify the
source or destination of data (operand)
in several different ways, depending
upon the situation.
Addressing modes are used to know
where the operand located is.
135. There are 5 types of addressing modes:
1. Register (direct) addressing.
2. Direct addressing.
3. Register indirect addressing.
4. Immediate addressing.
5. Index addressing.
136. 1.Register (Direct) Addressing Mode
1.Register (Direct) Addressing Mode
In register addressing mode; the
In register addressing mode; the source and/or
source and/or
destination is a register.
destination is a register.
In this case; data is placed in any of the 8
In this case; data is placed in any of the 8
registers(R0-R7); in instructions it is specified with
registers(R0-R7); in instructions it is specified with
letter Rn (where ‘n’ indicates 0 to 7).
letter Rn (where ‘n’ indicates 0 to 7).
For example;
For example;
1.
1. MOV A, Rn
MOV A, Rn (This is general instruction).
(This is general instruction).
2.
2. ADD A, R5
ADD A, R5 (This instruction will add the contents
(This instruction will add the contents
of register R5 with the accumulator contents).
of register R5 with the accumulator contents).
137. 2.Direct Addressing Mode
2.Direct Addressing Mode
In direct addressing mode; the address of memory
In direct addressing mode; the address of memory
location containing data to be read is specified in
location containing data to be read is specified in
instruction.
instruction.
In this case; address of the data is given with the
In this case; address of the data is given with the
instruction itself.
instruction itself.
E.g.:
E.g.: MOV A, 25H (This instruction will read/move
(This instruction will read/move
the data from internal RAM address 25H and store
the data from internal RAM address 25H and store
it in the accumulator.
it in the accumulator.
25H (address) 1F To ACC. (A)
25H (address) 1F To ACC. (A)
138. 3.Register Indirect Addressing Mode
3.Register Indirect Addressing Mode
In register indirect addressing mode; the
In register indirect addressing mode; the
contents of the designated register are used
contents of the designated register are used
as a pointer to memory.
as a pointer to memory.
In this case; data is placed in memory, but
In this case; data is placed in memory, but
address of memory location is not given
address of memory location is not given
directly with instruction
directly with instruction
e.g.:
e.g.: MOV A,@R0 This instruction moves
This instruction moves
the data from the register whose address is
the data from the register whose address is
in the R0 register into the accumulator.
in the R0 register into the accumulator.
R0 20H(address) 2F To ACC.(A)
R0 20H(address) 2F To ACC.(A)
139. 4.Immediate Addressing Mode
4.Immediate Addressing Mode
In immediate addressing mode, the data is
In immediate addressing mode, the data is
given with the instruction itself.
given with the instruction itself.
In this case; the data to be stored in memory
In this case; the data to be stored in memory
immediately follows the opcode.
immediately follows the opcode.
e.g.:
e.g.: MOV A, #25H
MOV A, #25H (This instruction will
(This instruction will
move the data 25H to accumulator.
move the data 25H to accumulator.
‘#’ means immediate
25H To ACC (A)
140. 5.
5.Index Addressing Mode
Index Addressing Mode
Offset (from accumulator) is added to the base
Offset (from accumulator) is added to the base
index register( DPTR OR Program Counter) to
index register( DPTR OR Program Counter) to
form the effective address of the memory location.
form the effective address of the memory location.
In this case; this mode is made for reading tables
In this case; this mode is made for reading tables
in the program memory.
in the program memory.
For example;
For example;
MOVC A, @ A + DPTR
MOVC A, @ A + DPTR ( This instruction moves
( This instruction moves
the data from the memory to accumulator; whose
the data from the memory to accumulator; whose
address is computed by adding the contents of
address is computed by adding the contents of
accumulator and DPTR)
accumulator and DPTR)
141. Data Transfer Instructions
Data Transfer Instructions
Mnemonic Description Byte
• MOV A, Rn Move register to accumulator 1
• MOV A, direct Move direct byte to acc. 2
• MOV A, @Ri Move indirect RAM to acc. 1
• MOV A, #data Move immediate data to acc. 2
• MOV Rn, A Move acc. to register 1
• MOV Rn, direct Move direct byte to register 2
• MOV Rn, #data Move immediate data to acc. 2
• MOV direct, A Move acc. to direct byte 2
• MOV direct, Rn Move register to direct byte 2
142. Mnemonic Description Byte
MOV direct, direct Move direct byte to direct 3
MOV direct, @ Ri Move direct RAM to direct byte 2
MOV direct, # data Move immediate data to direct byte 3
MOV @ Ri, A Move Acc. to indirect RAM 1
MOV @ Ri, direct Move direct byte to indirect RAM2
MOV @ Ri, #data Move immediate data to indirect RAM 2
MOV DPTR, #data Move immediate data to DPTR 3
MOVC A @ A+DPTR Move code byte relative to DPTR to acc. 1
MOVC A@ A+PC Move code byte relative to PC to acc. 1
143. Mnemonic Description Byte
MOVX A,@ Ri Move external RAM to acc. 8 bit 1
MOVX A, @ DPTR Move external RAM to acc 16 bit 1
MOVX @Ri, A Move acc. to external RAM 8 bit 1
MOVX @DPTR, A Move acc. to external RAM 16 bit 1
PUSH direct Push direct byte onto stack 2
POP direct Pop direct byte from stack 2
XCH A, Rn Exchange register with acc. 1
XCH A, direct Exchange direct byte with acc. 2
XCH A, @Ri Exchange indirect RAM with acc. 1
144. Arithmetic Instructions
Arithmetic Instructions
Mnemonic Description Byte
ADD A, Rn Add register to acc. 1
ADD A, direct Add direct byte to acc. 2
ADD A, @ Ri Add indirect RAM to acc. 1
ADD A, # data Add immediate data to acc. 2
ADDC A, Rn Add register to acc with carry 1
ADDC A , direct Add direct byte to acc with carry 2
ADDC A, @ Ri Add indirect RAM to acc with carry 1
ADDC A, # data Add immediate data to acc with carry 2
SUBB A, Rn Subtract register from acc with borrow 1
145. SUBB A, direct Subtract direct byte from acc with borrow 2
SUBB A, @ Ri Subtract Indirect RAM from acc with borrow 1
SUBB A, # data Subtract immediate data from acc with borrow 2
INC A Increment accumulator 1
INC RnIncrement register 1
INC direct Increment direct byte 2
INC @ Ri Increment indirect RAM1
DEC A Decrement acc. 1
DEC Rn Decrement register 1
DEC direct Decrement direct byte 2
DEC @ Ri Decrement indirect RAM 1
INC DPTR Decrement data pointer 1
MUL AB Multiply A and B 1
DIV ABDivide A by B 1
Mnemonic Description Byte
146. Logical Instructions
Logical Instructions
Mnemonic Description Byte
ANL A, Rn AND register to acc 1
ANL A, directAND direct byte to acc 2
ANL A,@ Ri AND indirect RAM to acc 1
ANL A, # data AND immediate data to acc 2
ANL direct, AAND acc to direct byte 2
ANL direct,# data AND immediate data to direct byte 3
ORL A, Rn OR register to acc 1
ORL A, directOR direct byte to acc 2
ORL A, @ Ri OR indirect RAM to acc 1
ORL A, # data OR immediate data to acc 2
ORL direct, AOR acc to direct byte 2
ORL direct, #data OR immediate data to direct byte 3
147. Mnemonic Description Byte
XRL A, Rn EX-OR register to acc 1
XORL A, direct EX-OR direct byte to acc 2
XORL A,@ Ri EX-OR indirect RAM to acc 1
XORL A, # data EX-OR immediate data to acc 2
XORL direct, A EX-OR acc to direct byte 2
XORL direct, # data EX-OR immediate data to direct byte 3
CLR AClear accumulator 1
CPL AComplement accumulator 1
SWAP A Swap nibble within acc 1
RL A Rotate acc left 1
RLC ARotate acc left through carry 1
RR A Rotate acc right 1
RRC A Rotate acc right through carry 1
148. Logical Instructions On Bits
Logical Instructions On Bits
Mnemonic Description Byte
CLR C Clear carry 1
CLR bit Clear direct bit 2
SETB C Set carry 1
SETB bit Set direct bit 2
CPL CComplement carry 1
CPL bit Complement direct bit 2
ANL C, bit AND direct bit to carry 2
ANL C,/bit AND complement of direct bit to carry 2
ORL C, bit OR direct bit to carry 2
ORL C,/bit OR complement direct to bit to carry 2
MOV C, bit Move direct bit to carry 2
MOV bit, C Move carry to direct bit 2
151. MOV instruction
MOV instruction
MOV destination, source ; copy source to destination
MOV instruction copies data from one location to another.
This instruction tells the CPU to copy the source operand
to the destination operand.
“MOV A, R0” copies the contents of register R0 to acc.
After this instruction is executed, register A will have the
same value as register R0.
MOV A, #55H ; Load value 55H into register A
(A=55H)
MOV R0, A ; copy contents of A into R0
(A=R0=55H)
152. ADD instruction
ADD instruction
• ADD A, source ; ADD the source operand to
acc
MOV A, #20H ; load 20H into A
MOV R0, #30H ; load 30H into R0
ADD A, R0 ; add R0 to acc
; (A=A+R0)
OR
MOV A, #20H ; Load one operand into A
ADD A, #30H ; add the second operand 30H to
A
153. Some important terms
Some important terms
Machine language: “A program consists of
0s and 1s is called as machine language”
Assembly language programs must be
translated into machine code by a program
called an “assembler”
Assembly language is referred to as a “Low-
level language”, it deals directly with the
internal structure of CPU.
To program in Assembly language, the
programmer must know all the registers of
the CPU and size of each, also other details.
154. • C, C++, Java and numerous other languages
are called “High-level languages” because
the programmer does not have to be
concerned with internal details of CPU.
• “Assembler” is used to translate an
Assembly language program into machine
code(sometimes also called object code or
opcode or operation code)
• “High level languages are translated into
machine code by a program called a
compiler”.
155. Steps to create a program
Steps to create a program
Myfile.lst
Myfile.lst
EDITOR
PROGRAM
ASSEMBLER
PROGRAM
LINKER
PROGRAM
OH
PROGRAM
Myfile.asm
Other .obj
Other .obj
file
file
Myfile.obj
Myfile.obj
Myfile.abs
Myfile.abs
Myfile.hex
Myfile.hex
156. Unconditional Jump Instructions
Unconditional Jump Instructions
All conditional jumps are short jumps
– Target address within -128 to +127 of PC
LJMP (long jump): 3-byte instruction
– 2-byte target address: 0000 to FFFFH
– Original 8051 has only 4KB on-chip ROM
SJMP (short jump): 2-byte instruction
– 1-byte relative address: -128 to +127
157. Call Instructions
Call Instructions
LCALL (long call): 3-byte instruction
– 2-byte address
– Target address within 64K-byte range
ACALL (absolute call): 2-byte instruction
– 11-bit address
– Target address within 2K-byte range
158. Basics of Serial Communication
Basics of Serial Communication
• Computers transfer data in two ways:
– Parallel: Often 8 or more lines (wire conductors) are
used to transfer data to a device that is only a few feet
away.
– Serial: To transfer to a device located many meters
away, the serial method is used. The data is sent one bit
at a time.
160. Serial data communication
Serial data communication
Serial data communication uses two methods
– Asynchronous method
– Synchronous method
There are special IC’s made by many
manufacturers for serial communications.
– UART (universal asynchronous Receiver
transmitter)
– USART (universal synchronous-asynchronous
Receiver-transmitter)
161. Asynchronous – Start & Stop Bit
Asynchronous – Start & Stop Bit
Asynchronous serial data communication is
widely used for character-oriented transmissions
– Each character is placed in between start and
stop bits, this is called framing.
– Block-oriented data transfers use the
synchronous method.
The start bit is always one bit, but the stop bit can
be one or two bits
The start bit is always a 0 (low) and the stop bit(s)
is 1 (high)
163. Data Transfer Rate
Data Transfer Rate
The rate of data transfer in serial data
communication is stated in bps (bits per second).
Another widely used terminology for bps is baud
rate.
– It is modem terminology and is defined as the number of
signal changes per second
– In modems, there are occasions when a single change
of signal transfers several bits of data
As far as the conductor wire is concerned, the baud
rate and bps are the same.
168. Baud Rate
Baud Rate
• No. of signal changes per second is
called as Baud Rate
• The rate of data transfer in serial data
communication is stated in BPS(Bits Per
Second)
• As far as conductor wire is concerned,
the baud rate and bps are the same
• The 8051’s serial communication UART
circuitry divides the machine cycle
frequency of 921.6 KHz by 32 gives
28800Hz.
171. SBUF Register
SBUF Register
Serial Buffer is an 8 bit register.
For a byte (8 bit) of data to be transferred
via the TXD line, it must be placed in the
serial buffer register.
Similarly SBUF register holds the byte of
data when it is received by the 8051’s RXD
line.
172. Operating Modes
Operating Modes
SM0 SM1 Trans. format Baud Rate
SM0 SM1 Trans. format Baud Rate
0 0
0 0 Serial Mode 0, , 8 bits
Serial Mode 0, , 8 bits 1/12
1/12
* 0 1
* 0 1 Serial Mode 1,8 bit data,
Serial Mode 1,8 bit data, variable
variable
1 stop bit, 1 start bit(10bits)
1 stop bit, 1 start bit(10bits)
1 0
1 0 Serial Mode 2
Serial Mode 2 1/32 or 1/64
1/32 or 1/64
11 bits(1 start, 1 stop, 8 bit data, 9
11 bits(1 start, 1 stop, 8 bit data, 9th
th
bit programmble)
bit programmble)
1 1
1 1 Serial Mode 3
Serial Mode 3 variable
variable
11 bits(1 start, 1 stop, 8 bit data, 9
11 bits(1 start, 1 stop, 8 bit data, 9th
th
bit programmble)
bit programmble)
173. Steps to write a program
Steps to write a program
1) Load TMOD register with the value 20H, indicating the use of
1) Load TMOD register with the value 20H, indicating the use of
timer 1,mode 2
timer 1,mode 2
(8 bit auto - reload) to set the baud rate.
(8 bit auto - reload) to set the baud rate.
2) Then TH1 is loaded with one of the values shown in Table 10-4
2) Then TH1 is loaded with one of the values shown in Table 10-4
3) SCON is loaded with value 50 H, indicating serial mode 1.
3) SCON is loaded with value 50 H, indicating serial mode 1.
4) TR1 is set to 1 to start timer 1
4) TR1 is set to 1 to start timer 1
5) Charact. To be transferred is written into SBUF
5) Charact. To be transferred is written into SBUF
6) TI is flag is monitored with the use of the information
6) TI is flag is monitored with the use of the information
“
“JNB TI ,xx”
JNB TI ,xx”
7) TI is cleared by “CLR TI” instruction
7) TI is cleared by “CLR TI” instruction
8)
8) Keep sending “A”
Keep sending “A”
174. Programming the 8051 to transfer data
Programming the 8051 to transfer data
serially
serially
175. Baud rates for SMOD=0
Baud rates for SMOD=0
Machine cycle freq. = 11.0592 MHz / 12 = 921.6 kHz
and
921.6 kHz / 32 = 28,800 Hz since SMOD = 0
176. Doubling the baud rate in the 8051
Doubling the baud rate in the 8051
By Doubling the crystal frequency
By Doubling the crystal frequency
By making SMOD= 1 of PCON register
By making SMOD= 1 of PCON register
178. Timer/Counter
Timer/Counter
8051 has two timers/Counters. They can be
used either as Timer to generate time delay. Or
as Counter to Count Events outside
microcontroller.
Timer 0 (T0) : 16 bit wide TH0(8) TL0(8)
Timer 1 (T1): 16 bit wide TH1(8) TL1(8)
182. Mode 1 programming
Mode 1 programming
1.Loaded value into TL and TH
2.”SETB TR0” for timer 0 ;”SETB TR1” for timer 1
3.If TF (timer flag) = high “CLR TR0” or “CLR TR1”
4.Reloaded TH and TL value, TF reset to 0
185. References
Sr.
No.
Title of Book Authors Publication House
1 “8051Microcontroller” Scott Mackenzie Pearson Education.
2 “8051 microcontroller” Subrata Ghoshal, Pearsons Publishers.
3
“Microprocessor and
Microcontroller”
Theagrajan BS Publication
Text books :
Sr. No. Title of Book Authors Publication House
1
“The 8051 Microcontroller and
Embedded Systems”
Muhammad Ali Mazidi, J.G.
Mazidi
Pearsons Publishers
2
“8051 Microcontroller, Hardware,
software and applications”
V Udayashankara and M S
MallikarjunaSwamy
TATA McGraw Hill
3 “Microcontroller 8051” Ajay Deshmukh TATA McGraw Hill.
4
“The 8051 Microcontrollers-
Architecture, Programming and
Applications”
K. J. Ayala
Peram International
Publications
Reference books:
186. RAM memory space allocation in the 8051
7FH
30H
2FH
20H
1FH
17H
10H
0FH
07H
08H
18H
00H
Register Bank 0
(
Stack
)
Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
(16 bytes)
Scratch pad RAM
(
80
bytes
)
187. Stack in the 8051
• The register used to access
the stack is called SP (stack
pointer) register.
• The stack pointer in the 8051
is only 8 bits wide, which
means that it can take value
00 to FFH. When 8051
powered up, the SP register
contains value 07.
7FH
30H
2FH
20H
1FH
17H
10H
0FH
07H
08H
18H
00H
Register Bank 0
(
Stack
)
Register
Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
190. RESET Value of Some 8051 Registers
0000
DPTR
0007
SP
0000
PSW
0000
B
0000
ACC
0000
PC
Reset Value
Register
RAM are all zero.
.
191. Special Function Registers (SFR'S)
There are 21 Special function registers (SFR)
in 8051 microcontroller and this includes
Register A, Register B, Program Status Word
(PSW), PCON etc. There are 21 unique
locations for these 21 special function
registers and each of these register is of 1
byte size. Some of these special function
registers are bit addressable (which means
you can access 8 individual bits inside a
single byte), while some others are only byte
addressable.
194. Special Function Registers (SFR'S)
Stack Pointer
Stack pointer is an 8 bit register, the direct
address of SP is 81H and it is only byte
addressable, which means you cant
access individual bits of stack pointer.
Usually after a system reset SP is
initialized as 07H and data can be stored
to stack from 08H onwards. This is usually
a default case and programmer can
alter values of SP to suit his needs.
198. Hardware Structure of I/O Pin
• Each pin of I/O ports
– Internal CPU bus ： communicate with CPU
– D latch store the value of this pin
• D latch is controlled by “Write to latch”
– Write to latch ＝ 1 ： write data into the D latch
– 2 Tri-state buffer ：
• TB1: controlled by “Read pin”
– Read pin ＝ 1 ： really read the data present at the pin
• TB2: controlled by “Read latch”
– Read latch ＝ 1 ： read value from internal latch
– A transistor M1 gate
• Gate=0: open
• Gate=1: close
199. A Pin of Port 1
A Pin of Port 1
8051 IC
D Q
Clk Q
Vcc
Load(L1)
Read latch
Read pin
Write to latch
Internal CPU
bus
M1
P1.X
pin
P1.X
TB1
TB2
200. Writing “1” to Output Pin P1.X
Writing “1” to Output Pin P1.X
D Q
Clk Q
Vcc
Load(L1)
Read latch
Read pin
Write to latch
Internal CPU
bus
M1
P1.X
pin
P1.X
2. output pin is
Vcc
1. write a 1 to the pin
1
0 output 1
TB1
TB2
201. Writing “0” to Output Pin P1.X
Writing “0” to Output Pin P1.X
D Q
Clk Q
Vcc
Load(L1)
Read latch
Read pin
Write to latch
Internal CPU
bus
M1
P1.X
pin
P1.X
2. output pin is
ground
1. write a 0 to the pin
0
1 output 0
TB1
TB2
202. Reading “High” at Input Pin
Reading “High” at Input Pin
D Q
Clk Q
Vcc
Load(L1)
Read latch
Read pin
Write to latch
Internal CPU bus
M1
P1.X pin
P1.X
8051 IC
2. MOV A,P1
external pin=High
1. write a 1 to the pin MOV
P1,#0FFH
1
0
3. Read pin=1 Read latch=0
1
TB1
TB2
203. Reading “Low” at Input Pin
Reading “Low” at Input Pin
D Q
Clk Q
Vcc
Load(L1)
Read latch
Read pin
Write to latch
Internal CPU bus
M1
P1.X pin
P1.X
8051 IC
2. MOV A,P1
external pin=Low
1. write a 1 to the pin
MOV P1,#0FFH
1
0
3. Read pin=1 Read latch=0
0
TB1
TB2
204. Other Pins
Other Pins
• P1, P2, and P3 have internal pull-up resisters.
– P1, P2, and P3 are not open drain.
• P0 has no internal pull-up resistors and does not
connect to Vcc inside the 8051.
– P0 is open drain(used in MOS)
• However, for a programmer, it is the same to
program P0, P1, P2 and P3.
• All the ports upon RESET are configured as
output.
205. A Pin of Port 0
A Pin of Port 0
8051 IC
D Q
Clk Q
Read latch
Read pin
Write to latch
Internal CPU
bus
M1
P0.X
pin
P0.X
TB1
TB2
1. write a 1 to the pin
1
0
Output pin
floating
206. Port 0 with Pull-Up Resistors
Port 0 with Pull-Up Resistors
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
Vcc
10 K
Port
0
![Architectural Components of 8051
• Arithmetic Logical Unit(ALU): ALU can perform arithmetic
and logic functions on 8-bit variables.
• Internal RAM: 8051 has 128 bytes which is divided into
o Working registers [00 – 1F]
o Bit addressable memory area [20 – 2F]
o General purpose memory area (Scratch pad memory) [30-7F]
• Internal ROM: 8051 has 4 K Bytes. The address space is from
0000 to 0FFFh.
o If the program size is more than 4 K Bytes 8051 will fetch the code
automatically from external memory.](https://image.slidesharecdn.com/module-018051microcontroller-250424052122-2c9f8e30/85/Module-01-8051-Microcontroller-for-engineering-63-320.jpg)
![Salient features of 8051
microcontroller
8-bit CPU.
On chip clock oscillator.
4K bytes of internal program memory [ROM].
128 bytes of internal data memory [RAM].
64 Kbytes of external program memory address space .
64 Kbytes of external data memory address space.
32 bit directional I/O lines (can be used as four 8-bit ports or 32
individually addressable I/O lines).
Two 16 Bit Timer/Counter :T0, T1
Full Duplex serial data receiver/transmitter.
Four Register banks (RB0-RB3) with 8 registers in each bank.](https://image.slidesharecdn.com/module-018051microcontroller-250424052122-2c9f8e30/85/Module-01-8051-Microcontroller-for-engineering-65-320.jpg)
