MOSFET_MODELING.PDF

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Comparison of Level 1, 2 and 3 MOSFET's
Technical Report · December 2014
DOI: 10.13140/RG.2.1.1616.3442
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Comparison of Level 1, 2 and 3 MOSFET’s
Twesha Patel
Course: Advanced Electronics, Instructor: Prof. Alan Davis, Semester: Fall 2014,
Department of Electrical Engineering, The University of Texas, Arlington
(Dated: December 3, 2014)
Abstract- The scaling of MOS technology to nanometer sizes leads to the
development of physical and predictive models for circuit simulation that cover AC,
RF, DC, temperature, geometry, bias and noise characteristics (1). This paper
addresses the comparison between level 1,2 and 3 MOSFETs. The results are
examined using SPICE (Simulation Program with Integrated Circuit Emphasis).
Drain current versus drain-source voltage characteristics are plotted to display the
differences between them.
I. INTRODUCTION
The downscaling of transistor dimensions over the past years is an evolutionary process
to provide superior performance, reduced size and cost. To assist this miniaturization of
devices, new simulators and device models have been invented.
Everywhere from designing of an IC, manufacturing to fabrication technology
development, modeling of device plays a major role in the advancement of Metal oxide
semiconductor technology. Considering the real time effects is essential while simulating
these device models. The SPICE model uses variety of parasitic circuit elements and
some process related parameters. The circuit designer can control these parameters and
syntax for MOSFET is given by
. MODEL <model name> NMOS [model parameters]
. MODEL <model name> PMOS [model parameters]
II. DEVICE MODELLING
To describe the performance of a device in mathematical terms, device modeling can be
used. Theoretical or empirical considerations, or both can be used to derive a model. A
few parameters along with the characterization can be used to build a desired model.
Quality of approximation and its complexity are often traded while establishing a model
making procedure. When making these tradeoffs, an engineer considers factors such as
intended use of the model and the required accuracy.

To create an understanding of the behavior of FET, rather than elemental models for a
circuit simulation analytical models were built. With the new innovations and
development of SPICE, these models were used as elemental models of the FETs.
III. SPICE MODELS
SPICE is a program used for simulation of electrical circuits. PSPICE (Orcad, Cadence
Design Systems), HSPICE (Synopsis), SPECTRE (Cadence Design Systems), Eldo are
some of the major commercial circuit simulators available in the market.
SmartSPICE (SiIvaco), Smash (Dolphin Integration), Saber (Analogy), APLAC (APLAC
Solutions), TSPICE (Tanner Research) etc. are few more softwares available for
simulation of complex circuits.
SPICE simulator and SPICE device models are the two distinct parts of SPICE. The
simulator uses mathematical models to replicate the behavior of an actual electronic
device or circuit. Simulation software allows for modeling of circuit operation and is an
invaluable analysis tool.
Device models used by SPICE (Simulation Program for Integrated Circuit Engineering)
simulators can be divided into three classes:
1. First Generation Models (Level 1, Level 2, Level 3 models)
2. Second Generation Models (BISM, BSIM2, HSPICE Level 28)
3. Third Generation Models (Level 7, Level 48, BSIM3, etc.)
Local stress, transistors operating in the sub-threshold region, short channel effects, noise
calculations, gate leakage (tunneling), temperature variations and the equations used are
better for circuit simulation in the newer generation models.
A. First Generation
Rather than focusing on the mathematical representation, these models express the
original purpose of a physically based analytical MOSFET model, with all geometry
dependent included in the model equations.
The First model generation is comprised of
1. LEVEL 1 model- When detailed analog models are not needed, these are often used to
simulate large digital circuits. They provide a high level of accuracy for timing
calculations and low simulation time. For more precision LEVEL 6 IDS model or one of
the BSIM models (LEVEL 13, 28, 39, 47, 49, 53, 54, 57, 59, and 60) can be used for a

detailed description.
2. LEVEL 2 model-The bulk charge effects on current are considered in this model.
3. LEVEL 3 model-The accuracy of this model is similar to that of LEVEL 2 but it offers
lesser simulation time and has a greater tendency to converge.
Fig. 1. Schematic of Level 1,2 and 3 MOSFET’s (4)
1. LEVEL 1 (Schichman-Hodges Model)
The model is applicable to devices with gate length greater than 10𝜇𝑚. This model is a
first order approximation of practical output of long channel MOS device. This model
takes into consideration channel length modulation by using a parameter L and body bias
effect is taken care by the transconductance. Whenever the channel length reduces below
4 mm, these parameters become dependent on externally applied voltages and other
parameters. The drain current (Ids) values will be lesser than the practically obtained
values if the channel length falls below this value and the model fails to include the
parameters related to short and narrow channel effects (3).
Gradual channel approximation and the square law for the saturated drain current are the
simplifications employed in this model (1).
MODEL EQUATIONS:
(a.) Drain current, Ids Equations:
174
Examples M1 14 2 13 0 PNOM L=25u W=12u
M13 15 3 0 0 PSTRONG
M16 17 3 0 0 PSTRONG M=2
M28 0 2 100 100 NWEAK L=33u W=12u
+ AD=288p AS=288p PD=60u PS=60u NRD=14 NRS=24 NRG=10
Model form .MODEL <model name> NMOS [model parameters]
.MODEL <model name> PMOS [model parameters]
Description The MOSFET is modeled as an intrinsic MOSFET using ohmic resistances in se
drain, source, gate, and bulk (substrate). There is also a shunt resistance (RDS) i
with the drain-source channel.
Arguments and options
L and W
are the channel length and width, which are decreased to get the effective ch
length and width. They can be specified in the device, .MODEL (model de
.OPTIONS (analysis options) statements. The value in the device statemen
the value in the model statement, which supersedes the value in the .OPTION
Defaults for L and W can be set in the .OPTIONS statement. If L or W defa
set, their default value is 100 u.
[L=<value>] [W=<value>] cannot be used in conjunction with Mon
analysis.
Drain
RD
Cgb
Cgd Cbd
RB
Bulk
Idrain
Cbs
Cgs
RG
Gate
Source
RS

The LEVEL 1 model does not include the carrier saturation effect, carrier mobility
degradation or the weak inversion model. The drain current equations for different
regions of operation are given below:
Cutoff Region (Vgs ≤Vth )
Ids = 0.0
Linear Region (𝑉!" > 𝑉
!" − 𝑉!!)
𝐼!"= KP.
!"##
!"##
. 1 + 𝜆. 𝑉!" . 𝑉
!" − 𝑉!! −
!"#
!
. 𝑉!"
(1)
Saturation Region (𝑉!" ≥ 𝑉
!" − 𝑉!!)
𝐼!" =
!"
!
.
!!""
!!""
. 1 + 𝜆. 𝑉!" . (𝑉
!" − 𝑉!!)!
(2)
(b.) Effective Channel Length and Width:
The Level 1 model calculates the effective channel length and width from the drawn
length and width:
Leff = Lscaled Ŋ LMLT + XLscaled – 2 . (LDscaled + DELscaled) (3)
Weff = M Ŋ (Wscaled WMLT + XWscaled – 2 . WDscaled) (4)
(LMLT-Length shrink factor
WMLT-Diffusion layer and width shrink factor
𝐿𝐷!"#$%&- Lateral diffusion into channel from source and drain diffusion
𝑊𝐷!"#$%& − Lateral diffusion into channel from bulk along width
XL, XW- Accounts for masking and etching effects
DEL- Channel length reduction factor.)
(c.) Saturation Voltage, 𝑉!"#:

The channel pinch-off at the drain side develops the saturation voltage for LEVEL 1
MOSFET model which is given by:
Vsat = Vgs – Vth
The carrier velocity saturation effects are not included in the LEVEL 1 model.
(d.) Threshold Voltage, Vth :
𝑉!" < 0 Vth = Vbi + ΥŊ ( 𝜙 +
!
!
!!"
!
) (5)
𝑉!" ≥ 0 Vth = Vbi+ Υ Ŋ ( 𝜙 + Vsb)1/2 (6)
The built-in voltage (Vbi) in the preceding equations are given by:
Vbi = Vfb + 𝜙 (7)
𝑉!" = 𝑉𝑇𝑂 − Υ. 𝜙
(VTO- Zero bias threshold voltage for a large device)
TABLE I
BASIC MODEL PARAMETERS (1)
Name Units Default Description
LEVEL 1.0 LEVEL 1 is the
Schichman-Hodges
model.
COX F/m2
3.453e-4 Oxide capacitance
per unit gate area.
LAMBDA, 𝜆 V-1
0.0 Channel-length
modulation.

KP (BETA-𝛽) A/V2
Intrinsic
transconductance
parameter.
TABLE II
THRESHOLD VOLTAGE PARAMETERS (1)
GAMMA, 𝛾 𝑉 0.5276 Body effect factor.
NSUB cm-3
1e15 Bulk surface doping.
PHI, 𝜙 V 0.576 Surface inversion
potential.
VTO, Vt V Zero-bias threshold
voltage.
TABLE III
EFFECTIVE WIDTH AND LENGTH PARAMETERS (1)
DEL m 0.0 Channel length
reduction on each
side.
LD m Default-0.0 Lateral diffusion into
channel from source
and drain diffusion.
LMLT 1.0 Length shrink factor.
WD M 0.0 Lateral diffusion into
channel from bulk
along width.
WMLT 1.0 Diffusion layer and
width shrink factor.
XL m 0.0 Accounts for
masking and etching
effect.

XW m 0.0 Accounts for
masking and etching
effect.
2. LEVEL 2 (Grove-Frohman Model)
LEVEL 2 is an advanced version of LEVEL 1 and implements Meyer’s model. LEVEL 1
doesn’t account for the short channel effects and is based on the assumption that
threshold voltage is constant and varies only with the substrate voltage.
This simplified semi-empirical model gives a detailed description of the mobility
degradation by the vertical field, the threshold region and the depletion region. It is used
for very long- channel devices with gate length of approximately 10𝜇𝑚. (1)
MODEL EQUATIONS:
Drain current for LEVEL 2 models is lower than that of LEVEL 1 models and is given
by:
Cutoff Region (𝑉
!" ≤ 𝑉!!)
Ids=0.0
On Region (𝑉
!" > 𝑉!!)
𝐼!" = 𝛽. 𝑉
!" − 𝑉!" −
!.!!"
!
. 𝑉!" −
!
!
. 𝛾. 𝜙 + 𝑉!" + 𝑉!"
!.!
− 𝜙 + 𝑉!"
!.!
(8)
𝜂 = 1 + 𝐷𝐸𝐿𝑇𝐴.
!.!!"
!.!"#.!!""
; (9)
DELTA- Controls the curvature of piecewise linear corners.

𝛽 = 𝐾𝑃.
!!""
!!""
(10)
(b.) Effective Channel Length and Width:
The drawn length and width are used to calculate the effective channel length and width
for LEVEL 2 and can be written as:
Leff = Lscaled Ŋ LMLT + XLscaled – 2. (LDscaled + DELscaled) (11)
Weff = M Ŋ (Wscaled Ŋ WMLT + XWscaled – 2 . WDscaled) (12)
LREFeff = LREFscaled Ŋ LMLT + XLscaled – 2. (LDscaled + DELscaled) (13)
WREFeff = M Ŋ (WREFscaled Ŋ WMLT + XWscaled – 2. WDscaled) (14)
(LREF, WREF- Channel length and width reference respectively)U
(c.) Saturation Voltage, Vdsat:
Due to channel pinch off at the drain side, the program calculates the saturation voltage.
If the corrections for small-size effects are included, then:
𝑉!"# =
!!"!!!"
!
+ 0.5.
!!
!!
. 1 − 1 + 4.
!!
!!
.
!!"!!!"
!
+ 𝜙 + 𝑉!"
!/!
(15)
Vdsat = Vsat
Considering the velocity saturation effect,
𝑉!"#$ = 𝑉!"# + 𝑉
! − (𝑉!"# − 𝑉
!)!/!
(16)
The following equation calculates the Vc value used in the preceding equation:
Vc = 𝐸!"#$ Ŋ Leff

𝐸!"#$ = Drain-source critical field.
(d.) Threshold Voltage, Vth:
The effective threshold voltage including the device size effects and the terminal
voltages is given by:
𝑉!! = 𝑉!" + 𝛾. (𝜙 + 𝑉!")!/!
(17)
The following equation calculates the Vbi value used in the preceding equation:
𝑉!" = 𝑉𝑇𝑂 − 𝛾 𝜙+(𝜂 − 1)(𝜙 + 𝑉!")!/!
(18)
LEVEL 2 uses VTO, 𝛾 and 𝜙 to calculate the threshold voltage.
(e.) Channel Length Modulation:
The LEVEL 2 MOS model modifies the Ids current to include the channel length
modulation effect:
𝐼!" =
!!"
!!!!!"
(19)
For λ=LAMBDA<0; VMAX >0
λ =
!!
!"##.!!"".!!"
.
!"#$.!!
!. !"##.!!""
!
+ 𝑉!" − 𝑉!"#$ −
!"#$.!!
!. !"##.!!""
(20)
NEFF-Total channel charge (fixed and mobile) coefficient
VMAX-Maximum drift velocity of carriers
For λ=LAMBDA<0; VMAX =0

λ =
!!
!!"".!!"
.
!!"!!!"#$
!
+ 1 +
!!"!!!"#$
!
!
(21)
𝑋! =
2. 𝐸!"
𝑞. 𝑁𝑆𝑈𝐵
NSUB-Bulk surface doping
(f.) Mobility Reduction, 𝜇!"":
The mobility of carriers in the channel decreases as the carriers' speeds approach their
scattering limited velocity.
If MOB=0, 𝜇!"" < 𝑈0 (default):
𝜇!"" = 𝑈0.
!"#$%.!!"
!"#.(!!"!!!!!!"#$.!!")
!"#$
(22)
𝑉
!" < 𝑉!!, 𝜇!"" = 𝑈0:
𝜇!"" = 𝑈0.
!"#$%.!!"
!"#.(!!"!!!!)
!"#$
(23)
TABLE IV
LEVEL 2.0 LEVEL 2 is the
Grove-Frohman
model.
COX F/m2
per unit gate area.

ECRIT V/cm 0.0 Critical electric field
for carrier velocity
saturation.
LAMDA, 𝜆 V-1
0.0 Channel length
modulation.
NEFF 1.0 Total channel charge
(fixed and mobile)
coefficient.
VMAX m/s 0.0 Maximum drift
velocity of carriers
KP (BETA-𝛽) A/V2
2.0e-5 Intrinsic
transconductance
parameter.
TABLE V
NSUB cm-3
potential.
voltage.
DELTA 0.0 Narrow width factor
for adjusting
threshold
TABLE VI
reduction on each
side.
channel from source

LREF m 0.0 Channel length
reference.
WD m 0.0 Lateral diffusion into
channel from bulk
along width.
WREF m 0.0 Channel width
reference
XL, XW m 0.0 Accounts for
masking and etching
effect.
TABLE VII
MOBILITY PARAMETERS (1)
MOB 0.0 MOB=0 or MOB=7.
NOTE: MOB=7
invokes the channel
length modulation
and mobility
equations of
MOSFET LEVEL 3.
THETA V-1
0.0
Mobility modulation
when MOB=7
UCRIT V/cm 1.0e4 Critical field for
mobility degradation
UEXP 0.0 Critical field
exponent which
characterizes surface
mobility degradation

UO cm2
/V-s 600 (N)
250 (P)
Low-field bulk
mobility.
3. LEVEL 3 (Empirical Model)
LEVEL 3 is developed to overcome the observed shortcomings of Level 2. It is more
efficient mathematically and more accurate as compared to LEVEL 2. LEVEL 3 model is
an improvement over LEVEL 2 model with simple equations and many empirical
constants. As the name suggests this model is derived from empirical relations between
practical data obtained from experiments and the theoretical models already existent.
With a structure similar to LEVEL 2, this is a semi-empirical model that places more
emphasis on parameter extraction. Drain-induced barrier lowering (DIBL) and mobility
degradation by the lateral field like physical effects are also included. These models are
applicable to long-channel devices with gate length of approximately 2 𝜇𝑚 (1).
MODEL EQUATIONS:
Drain current equations for LEVEL 3 are given by:
Cutoff Region (Vgs <Vth)
Ids = 0
On Region (Vgs >Vth)
𝐼!" = 𝛽. 𝑉
!" − 𝑉!! −
!!!"
!
. 𝑉!" . 𝑉!" (24)
𝛽 = 𝐾𝑃.
!!""
!!""
; 𝐾. 𝑃 = 𝑢!"". 𝐶𝑂𝑋 (25)
𝑓𝑏 = 𝑓! +
!.!!
!. !! !!"
(26)
𝑓! specifies the narrow width effect and is given by:
𝑓! =
!"#$%
!!""
. 0.25.
!!.!!"
!"#
(27)

𝑓! specifies the short channel effects and is given by:
𝑓! = 1 −
!"!"#$%&
!!""
⇒
!"!"#$%&!!!
!"!"#$%&
. 1 −
!!
!!!"#$%&!!!
!
−
!"!"#$%&
!"!"#$%&
(28)
𝑊
! = 𝑋!. 𝜙 + 𝑉!"
(b.) Saturation Voltage, Vdsat:
Due to the channel pinch-off at the drain side, LEVEL 3 calculates the saturation voltage
considering the VMAX parameter which specifies the reduction of the saturation voltage
due to the carrier velocity saturation effect.
𝑉!"# =
!!"!!!!
!!!"
(29)
𝑉!"#$ = 𝑉!"# + 𝑉
! − 𝑉!"#
!
+ 𝑉
!
! !.!
(30)
(c.) Threshold Voltage, Vth:
The following equation calculates the effective threshold voltage, including the device
size and terminal voltage effects:
𝑉!! = 𝑉!" −
!.!"!!!!
!!".!"##!
⇒ 𝐸𝑇𝐴 ⇒ 𝑉!" + Υ. ϕ + 𝑉!" . 𝑓!. +𝑓!. (𝜙 + 𝑉!") (31)
The following equation calculates the vbi value used in the preceding equation:
𝑉!" = 𝑉!" + ϕ = 𝑉𝑇𝑂 − 𝐺𝐴𝑀𝑀𝐴. ϕ (32)
(e.) Effective Channel Length and Width:

The following equations are used to determine the effective channel length and width for
the LEVEL 3 model:
Leff = Lscaled Ŋ LMLT + XLscaled – 2. (LDscaled + DELscaled) (34)
W
eff
= M Ŋ (W
scaled
Ŋ WMLT + XW
scaled
– 2 .WD
scaled
) (35)
LREFF = LREFscaled Ŋ LMLT + XLscaled – 2.(LDscaled + DELscaled) (36)
WREFeff = M Ŋ (WREFscaled Ŋ WMLT + XWscaled – 2 . WDscaled) (37)
(f.)Effective Mobility, 𝜇!"":
The model defines the carrier mobility reduction due to the normal field as the effective
surface mobility (𝜇!).
For Vgs >Vth,
𝜇! =
!!
!!!"#!$(!!"!!!!)
(38)
VMAX>0
𝜇!"" =
!!
!!
!!"
!!
(39)
else ,
𝜇!"" = 𝜇!
(g.) Channel Length Modulation:
For 𝑉!" > 𝑉!"#$
VMAX=0
Δ𝐿 = 𝑋! 𝐾𝐴𝑃𝑃𝐴(𝑉!" − 𝑉!"#$) (40)

VMAX>0
Δ𝐿 = −
!!.!!
!
!
+
!!.!!
!
!
!
+ 𝐾𝐴𝑃𝑃𝐴. 𝑋!
!
(𝑉!" − 𝑉!"#$) (41)
𝐸! =
!!(!!!!!"#$)
!!"".!!"#$
= Lateral electric field at the pinch off point
TABLE VIII
LEVEL 3 LEVEL 3 is the
empirical model.
COX F/m2
per unit gate area.
ECRIT V/cm 0.0 Critical electric field
for carrier velocity
saturation.
LAMDA, 𝜆 V-1
0.0 Channel length
modulation.
NEFF 1.0 Total channel charge
(fixed and mobile)
coefficient.
VMAX m/s 0.0 Maximum drift
velocity of carriers
KP (BETA-𝛽) A/V2
2.0e-5 Intrinsic
transconductance
parameter.
TABLE IX

NSUB cm-3
potential.
voltage.
DELTA 0.0 Narrow width factor
for adjusting
threshold.
ETA 0.0 Static feedback factor
for adjusting
threshold
TABLE X
reduction on each
side.
channel from source
LREF m 0.0 Channel length
reference.
WD m 0.0 Lateral diffusion into
channel from bulk
along width.
WREF m 0.0 Channel width
reference
XL, XW m 0.0 Accounts for
masking and etching
effect.

TABLE XI
MOBILITY PARAMETERS (1)
THETA V-1
0.0
Mobility degradation
factor
UO cm2
/V-s 600 (N)
250 (P)
Low-field bulk
mobility.
V. PSPICE NETLIST AND OUTPUT WAVEFORMS
A. LEVEL 1
Vgs 1 0 2V
Vds 2 0 2V
Vbs 3 0 0V
*NFET
M1 2 1 0 3 L1 L=3u W=3u
*NFET Model
.MODEL L1 NMOS LEVEL=1 RSH=0 TOX=300E-10 LD=0.21E-6
+ XJ=0.3E-6 VMAX=15E4 ETA=0.18 GAMMA=0.4 KAPPA=0.5
+ NSUB=35E14 UO=700 THETA=0.095 VTO=0.781 CGSO=2.8E-10
+ CGDO=2.8E-10 CJ=5.75E-5 CJSW=2.48E-10 PB=0.7 MJ=0.5
+ MJSW=0.3 NFS=1E10
.options post probe
*For I-V Curve Id vs Vgs
.dc Vgs 0 5 0.1
.probe I1(M1)
*For I-V Curve Id vs Vds with Vgs = 2V
.dc vds 0 5 0.1
.probe I1(M1)
*For family of I-V Curves
.dc Vds 0 5 0.1 Vgs 0 5 1
.probe I1(M1)
.end

Fig. 2. Variation of Id as a function of gate voltage in LEVEL 1 model
B. LEVEL 2
Vgs 1 0 2V
Vds 2 0 2V
Vbs 3 0 0V
*NFET
M1 2 1 0 3 L2 L=3u W=3u
*NFET Model
.MODEL L2 NMOS LEVEL=2 PHI=0.7 TOX=4.08E-8 XJ=0.2 TPG=1
+VTO=0.8096 DELTA=4.586 LD=2.972E-7 KP=5.3532E-5
+UO=632.5 UEXP=0.1328 UCRIT=3.897E4 RSH=6.202
+GAMMA=0.5263 NSUB=5.977E15 NFS=5.925e11 VMAX=5.83E4
+LAMBDA=3.903E-2 CGDO=3.7731E-10 CGSO=3.7731E-10
+CGBO=3.4581E-10 CJ=1.3679E-4 MJ=0.63238 CJSW=5.1553E-10
+MJSW=0.26805 PB=0.4
.options post probe
.dc Vgs 0 5 0.1
.probe I1(M1)
.dc vds 0 5 0.1

.probe I1(M1)
.dc Vds 0 5 0.1 Vgs 0 5 1
.probe I1(M1)
.end
C. LEVEL 3
Vgs 1 0 2V
Vds 2 0 2V
Vbs 3 0 0V
*NFET
M1 2 1 0 3 L3 L=3u W=3u
*NFET Model
.MODEL L3 NMOS LEVEL=3 TPG=1 TOX=1.5E-8 LD=2.95E-7 WD=3.00E-7
+UO= 263 VTO=0.5 THETA=0.046 RS=27 RD=27 DELTA=2.27 NSUB=1.45E17
+XJ=1.84E-7 VMAX=1.10E7 ETA=0.927 KAPPA=0.655 NFS=3E11
+CGSO=3.4E-10 CGDO=3.48E-10 CGBO=5.75E-10 XQC=0.4
.options post probe
.dc Vgs 0 5 0.1
.probe I1(M1)
.dc vds 0 5 0.1

.probe I1(M1)
.dc Vds 0 5 0.1 Vgs 0 5 1
.probe I1(M1)
.end
D. TEMPERATURE COMPENSATION
vds 1 0 5
vgs 2 0 2
.option ingold=2 numdgt=6 post=2
.temp 25 100
m1 1 2 0 0 nch w=10u L=1u
.print id=lx4(m1) vdsat=lv10(m1)
.model M1 nmos LEVEL=3 tlev=1 tlevc=0 acm=3
+ uo=600 tox=172.6572
+ vto=0.8 gamma=0.8 phi=0.64
+ kappa=0 xj=0
+ nsub=1e16 rsh=0
+ tcv=1.5e-3 bex=-1.5
.op

.end
1. CALCULATIONS:
1. At T= 25
beta = 1.2e – 3
Vtm= 0.8
phi(t) = 0.64
𝐼!" = 1.2𝑒 − 3 . 0.5.
!!!.! !
!!
!.!
!.!"
= 6.9123 − 4
2. At T= 100
beta = (1.2e - 3).(1.251)-1.5
= 0.570545e-4
Vtm= 0.8- (1.5e - 3).75= 0.6875
phi(t) = 0.64. 1.251 – 0.323 = 0.4770
𝐼!" = 0.570545e − 4 . 0.5.
2 − 0.6875 !
1 +
0.2
0.4770
= 5.724𝑒 − 4
2. SIMULATION RESULTS:
At T= 25, id=6.91200e - 04
At T= 100, id=5.72451e - 04
V. COMPARISON
A. LEVEL 1
NSUB (substrate impurity concentration); NSS (Surface state density used to define

surface component of VT0); NA (NMOS); ND (PMOS); U0 (Surface mobility µ0); RD
(Drain resistance); TOX (Oxide thickness tox); RS (Source resistance); RSH (Drain and
Source sheet resistance (Ω/□)) are the parameters used.
Fig. 5. Variation of Id with model parameter VTO for LEVEL 1 model (Copyright 1988 by
McGraw- Hill, Inc).
B. LEVEL 2
Level 2 is an analytical model that takes into account small geometry effects. New
parameters added are NFS (Fast surface state density which models sub threshold); NEFF
(Total channel charge coefficient); VMAX (Maximum drift velocity for carriers used for
modeling velocity saturation); DELTA (Channel width effect on VT); XJ (Junction depth
of source and drain). UCRIT (Critical electric field for mobility degradation), UTRA
(Transverse field coefficient for mobility degradation) and UEXP (Exponent coefficient
for mobility degradation) and produce a multiplicative surface mobility degradation
factor to multiply times KP and appears in Level 2 only.
Fig. 6. Variation of Id with gate voltage in LEVEL 2 model (Copyright 1988 by McGraw- Hill,
Inc).
4
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11
4
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12
4
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19
DC SPICE Models: Level 2 (2/2)
–Equations
VT – Equation as derived previously
ID – Equations as derived previously with linear mode equation
times (1+λVDS) for continuity across linear-saturation boundary.
Both use Leff in place of L where:
Leff = L – 2 LD
–Key Parameters: What do they represent? See Kang and
Leblebici – Table 4.1
NMOS, PMOS (obvious) – MOSFET channel type
KP – process transconductance k‘
VTO (note O, not 0!) – zero substrate-bias threshold voltage VT0
GAMMA – substrate-bias or body-effect coefficient γ
PHI – twice the Fermi potential 2φF
LAMBDA – channel length modulation λ
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20

C. LEVEL 3
Level 3 as the name describes is more empirical and less analytical than Level 2, which
permits simpler computation and improved convergence while sacrificing little accuracy.
Level 2 parameters such as NEFF, UTRA, UCRI and UEXP have been deleted. New
parameters important to this model are KAPPA (Saturation field factor); ETA (static
feedback on VT which models effect of VDS on VT); THETA (Mobility modulation
which models the effect of VGS on surface mobility).
Fig. 7. Id-Vds characteristics of NMOS for LEVEL 2 (A) and LEVEL 3 (B) model.
VI. CONCLUSION
From the above results we can conclude that Level 1 model is too approximated with the
number of fitting parameters too small. Also Level 1 can be used for preliminary circuit
simulations and appropriate for long channel and uniform-doping devices. The benefit
from Level 2 is small. Level 3 has higher accuracy and requires less time for calculations.
Level 3 is good for MOSFET down to about 2 microns.
The most challenging task to device models is the high accuracy fitting of device data
from different technologies. Along with quality, the ease of parameter extraction, number
of parameters, redundancy of parameters, correlation of parameters, etc. should also be
considered (2).
Device models are constantly developed, elaborated and refined to achieve best
description and prediction of the downscaling devices and to met the new challenges of
power dissipation, leakage management, short channel effects, etc. Deep understanding
of the underlying physical phenomena is required as well as competent use of
mathematical techniques to settle efficient and accurate modeling methodologies that
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• BSIM2 (HSPICE Level 39): Good for small geometry MOSFETs
with L down to 0.2 micron and tox down to 36 Angstroms.
• HSPICE Level 28: BSIM with its problems solved; good choice
for HSPICE users.
• BSIM3 Version 3 (HSPICE Level 49): Most accurate, but
complex.
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4.8 Comparison of the SPICE MOSFET Models

encompass constantly downscaling technologies. Now a huge emphasis is placed on
obtaining physics-based, simple and highly accurate analytical device models.
REFERENCES
[1] HSPICE® Reference Manual: MOSFET Models Version D-2010.12, December 2010
[2] SPICE Modeling of MOSFETs in Deep Submicron, GEORGE ANGELOV, MARLN
HRISTOV, Technical University of Sofia, Faculty f Electronic Engineering and Technology, ECAD
Laboratory.
[3] H. Shichman and D. A. Hodges, “Modeling and simulation of insulated-gate field-
effect transistor switching circuits,” IEEE Journal of Solid-State Circuits, SC-3, 285,
September 1968.
[4] ORCAD SPICE A/D Reference Manual, Version 9.0, October 1998.
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