VLSI_Design_flow_Introduction_details.ppt
- 1. Lecture #7 Page 1 EE 414 – Introduction to VLSI Design Fall 2007 EE 414 – Introduction to VLSI Design Lecture #7 • Agenda 1. SPICE Modeling 2. CMOS Fabrication 3. Catch-up & Problem Session • Announcements (Tuesday, 9/18) 1. HW#4 posted, (due 9/27) 2. Read Ch4, 2.1-2.3
- 2. Lecture #7 Page 2 EE 414 – Introduction to VLSI Design Fall 2007 SPICE Modeling • SPICE Modeling - Simulation Program with Integrated Circuit Emphasis or Simulation Program for the Integrated Circuit Environment - Developed by UC Berkeley in the late 1970’s - SPICE is an electric circuit simulator (R,L,C,V,I,…) - Its main contribution at the time was the ability to support transistor Models - Today… - Berkeley SPICE is free for Unix/Linux. It is a text based program. - CAD vendors take the free SPICE engine and add features like graphical entry and additional components - The CAD vendors then sell it for big money (Mentor, Synopsis, Cadence,…)
- 3. Lecture #7 Page 3 EE 414 – Introduction to VLSI Design Fall 2007 SPICE Modeling • SPICE Modeling - How does SPICE work? - for a given circuit, KCL and KVL equations can be written - Just like in EE206, these equations can be solved using Matrix math - SPICE does the same thing, except on the front-end it is able to take the entered circuit and create the KCL/KVL equations for us
- 4. Lecture #7 Page 4 EE 414 – Introduction to VLSI Design Fall 2007 SPICE Modeling • SPICE Modeling - This can also be extended to AC analysis since the matrix math can handle Complex numbers - We can create Bode Plots by sweeping the frequency (i.e., running a simulation at each frequency) - SPICE can also perform transient simulations by performing numerical integration
- 5. Lecture #7 Page 5 EE 414 – Introduction to VLSI Design Fall 2007 SPICE Modeling • SPICE Modeling - The source file for a SPICE simulation is called a DECK (from the days of punch cards… what is a punch card?... I’m not that old…) - The DECK can be thought of as a text netlist of the circuit. - Even when using a graphical entry tool for the schematic, the first thing the tool does when you click “simulate”, is create a text-based DECK that is plugged into the SPICE engine. - the first letter of a component instantiation in the DECK tells SPICE what the component is. - devices are then followed by the net names they connect to followed by their parameters R1 n1 n2 VALUE=75 * resistor L1 n2 n3 VALUE=1n * inductor C1 n3 n4 VALUE=1p * capacitor V1 n4 n5 DC=1v * DC voltage source I1 n5 n6 ACmag=1 * AC current source
- 6. Lecture #7 Page 6 EE 414 – Introduction to VLSI Design Fall 2007 SPICE Modeling • SPICE Modeling - SPICE allows the use of MODELS to represent components with complex, non-linear responses such as Diodes and Transistors - Models are present in their own file (starting with the .MODEL keyword) - A component is instantiated in the DECK, but then references the MODEL to describe its behavior - MOSFETS are denoted with an “M” as their first letter M1 D G S B NMOD (L=1U W=10U) .MODEL NMOD NMOS + KP=40 + VT0=0.55 + GAMMA=0.34 + PHI=0.3 + LAMBDA=0.2 : : MOSFET Terminal Connections Model Name Parameters DECK MODEL Model Name Device Parameters Model Type (NMOS or PMOS)
- 7. Lecture #7 Page 7 EE 414 – Introduction to VLSI Design Fall 2007 SPICE Modeling • SPICE Modeling (Level 1) - There different levels of accuracy and complexity that a model can have. - We give these different types of models the description of Level (i.e., Level 1 model, Level 2 model..) - Increasing model accuracy increases simulation time - Let’s start by looking at the simplest model for a MOSFET, Level 1 - Level 1 uses the basic IV equations - it also includes: 1) Resistance of Source & Drain 2) Capacitance (bias dependant) 3) Reverse-Bias behavior of Junction Diodes
- 8. Lecture #7 Page 8 EE 414 – Introduction to VLSI Design Fall 2007 SPICE Modeling • SPICE Modeling (Level 1) - parameters can exist in the Model file. However, we can pass in parameters (i.e., override) the parameters by putting them in the Deck instantiation - there are different types of parameters for the model “Design Parameters” - these parameters are under the designer’s control - these sometimes have default values, but if we are doing design, this is what we change Parameter Description L length of channel (drawn) W width of channel AS / AD area of Source/Drain PS / PD perimeter of Source/Drain
- 9. Lecture #7 Page 9 EE 414 – Introduction to VLSI Design Fall 2007 SPICE Modeling • SPICE Modeling (Level 1) “Electrical Parameters” - there are 5 parameters that fully characterize the base model - these will have default values in the model based on the fab process - we can overwrite these from the DECK if we want to perform sensitivity analysis Parameter Description KP k’, transconductance VTO VT0, zero substrate bias threshold GAMMA γ, substrate-bias coefficient PHI |2F|, surface potential LAMBDA λ, channel length modulation coefficient
- 10. Lecture #7 Page 10 EE 414 – Introduction to VLSI Design Fall 2007 SPICE Modeling • SPICE Modeling (Level 1) “Physical Parameters” - there are parameters that describe the shape and material properties of the device Parameter Description U0 un, electron mobility TOX tox, oxide thickness NSUB NA, doping concentration LD LD, lateral diffusion - notice that these parameters are redundant with the Electrical parameters since these quantities are used to calculate k’, VT0, γ, |2F|, and λ - these allow you to get further into the details of the fabrication to see its effect on performance - however, the “Electrical Parameters” OVERRIDE the “Physical Parameters” - this means you wouldn’t supply both if you really want to see the effect of a physical parameters on the performance of the device. You would need to remove the electrical parameter.
- 11. Lecture #7 Page 11 EE 414 – Introduction to VLSI Design Fall 2007 SPICE Modeling • SPICE Modeling (Level 1) “Parasitic Parameters” - these are the capacitances and resistances of the material Parameter Description CJ CJ0, zero-bias bulk capacitance per area CJSW CJ0sw, zero-bias sidewall capacitance per area - there parameters scale with the size of the device provided by W,L,AS,AD,PS, and PD. - there are many more parameters in table 4.1 in the textbook, take a look and you’ll see why we need SPICE to properly predict the behavior of a transistor.
- 12. Lecture #7 Page 12 EE 414 – Introduction to VLSI Design Fall 2007 SPICE Modeling • SPICE Modeling (Level 2) - Level 2 adds the following behavior to the Level 1 model 1) Variation of the bulk depletion charge dependence on the channel voltage (we assumed it was constant in Level 1). 2) Variation of electron mobility (un) with the applied E-field 3) Variation of effective Channel Length in Saturation model 4) Carrier Velocity Saturation 5) Subthreshold Conduction - we also have the ability to indicate which level we want to use. For example, you can have a Level 2 model, but in the instantiation you say: M1 D G S B NMOD (Level=1 L=1U W=10U) this will tell the simulator to ignore all the parameters associated with Level 2 or higher accuracy. - we can also put the “Level=1” as the first parameters in the model
- 13. Lecture #7 Page 13 EE 414 – Introduction to VLSI Design Fall 2007 SPICE Modeling • SPICE Modeling (Level 3) - Level 3 was developed to specifically address small geometry effects. - instead of trying to come up with an expression for each and every bump and wiggle on the IV curve, Level 3 instead moves toward a more empirical approach. - curve-fitting parameters are added to the IV equations from Level 1 and Level 2. - these parameters are dialed-in based on measurement data from a test run of transistors.
- 14. Lecture #7 Page 14 EE 414 – Introduction to VLSI Design Fall 2007 SPICE Modeling • SPICE Modeling (BSIM) - Berkeley Short-Channel IGFET Model - what is an IGFET? - the term MOSFET implies a “metal” contact for the gate. Some say that is in not accurate for transistors that use polysilicon for the gate contact since polysilicon is not considered a true metal. Of course polysilicon is a conductor, just not a pure metal. - so the term “Insulated Gate FET” is used which describes any type of conducting gate used. - this is a totally empirical model which reduces the # of curve fitting parameters - this actually reduces simulation time over the Level 3 models, and sometimes over Level 2 due to moving away from IV equations with many coefficients. - there have been many versions of the BSIM models, but the most current is BSIM3 - this is the most commonly used model for accurate simulations.
- 15. Lecture #7 Page 15 EE 414 – Introduction to VLSI Design Fall 2007 SPICE Modeling • SPICE Modeling - Which Model should I use? - simulation is always a tradeoff of accuracy vs. simulation time - simulation time is a big problem. You’ll never ship if each simulation takes a month, (and they easily can!!!) - typically, we can use Level 1 models for quick, functional simulations ex) if I hook it up like this, does it do what I think it is supposed to? - then we move to BSIM3 models for accurate simulations which tell us speed, power, etc…
- 16. Lecture #7 Page 16 EE 414 – Introduction to VLSI Design Fall 2007 CMOS Fabrication • CMOS Fabrication - We have talked about 1) Device Physics of how materials act in a MOS/MOSFET structure 2) IV characteristics of the MOSFET device 3) Small geometry effects on transistor performance 4) Capacitances present in the MOSFET device 5) How we can use SPICE to simulate the behavior - we have seen that the properties of the materials play a major role in how the MOSFET performs - the properties of the material (which material, doping, sizes,..) come from the Fabrication of the MOSFET. - we want to understand how the devices are created so when we are designing, we can make educated decisions on what can and can’t be done to alter performance.
- 17. Lecture #7 Page 17 EE 414 – Introduction to VLSI Design Fall 2007 CMOS Fabrication • The Basics - We create the majority of our IC’s on Silicon - we take a Silicon Wafer, which is a thin disk of intrinsic Silicon - on this disk, we create multiple IC’s, which are square or rectangular in shape
- 18. Lecture #7 Page 18 EE 414 – Introduction to VLSI Design Fall 2007 CMOS Fabrication • The Basics - Once the wafer is processed, each individual IC is tested and marked whether it passed or failed - The individual IC’s are then cut out using a precision diamond saw. - the individual IC is called a “die” - the plural of this is “dies” or “dice”
- 19. Lecture #7 Page 19 EE 414 – Introduction to VLSI Design Fall 2007 CMOS Fabrication • The Basics - we define the : Yield = (# of Good die) (# of die on the wafer) - Yield heavily drives the cost of the chip so we obviously want a high yield. However, yields can be very low initially (i.e., <10%). - a mature process tries to hit ~90% yield
- 20. Lecture #7 Page 20 EE 414 – Introduction to VLSI Design Fall 2007 CMOS Fabrication • The Basics - since all of the IC’s on a wafer are processed together, the time it takes and the process steps required for the wafer are the same regardless of the # of IC’s on it. - this means the cost to process a wafer is the same whether it has 1 IC, or 1000 IC’s on it. - we can drive the cost down by: 1) Increasing the number of die on a wafer - smaller features (i.e., new processes, 1um, 0.8um, 0.25um, 90nm, 45nm) - larger wafers (2”, 4”, 8”, 12”, 16”) 2) Increasing yield - design changes - fab changes