3. SYLLABUS
8085 Interrupts – Software and Hardware
Interrupts – 8259 Programmable Interrupt
Controller - Data Transfer Techniques –
Synchronous, Asynchronous and Direct Memory
Access (DMA) and 8237 DMA Controller- 8253
Programmable Interval Timer
4. INTERRUPT STRUCTURE
Interrupt is a mechanism by which the processor (CPU) is made to transfer control
from its current program execution to another program of more importance or higher
priority.
The interrupt signal may be given to the processor by any external peripheral device.
In general, interrupts are generated by a variety of sources, either internal or
external, to the CPU.
Interrupts are the primary means by which input and output devices obtain the
services of the CPU.
The program or the routine that is executed upon interrupt is called interrupt service
routine (ISR).
The processor must temporarily stop its current task and execute the ISR, which
relates specifically to the event or device that issues the interrupt signal.
5. After execution of the ISR, the processor must return to the interrupted
program.
Processors have many interrupt signals and proper identification of
interrupt signals is done internally by the processor.
6. The key features in the interrupt structure of any microprocessor are as follows:
(i) The number and types of interrupt signals available.
(ii) The address of the memory where the ISR is located for a particular interrupt signal.
This addresses called interrupt vector address.
(iii) The masking and unmasking feature for the interrupt signals. This feature allows the
programmer to execute the ISR only when required.
(iv) The priority of interrupts when more than one interrupt signals are available
(v) The timing of the interrupt signals
(vi) The handling and storing of information about the interrupted program (status
information). This information must be loaded into the CPU when the ISR is executed.
When the return instruction is executed, control is transferred back to the
interrupted program.
7. INTERRUPT SOURCES AND VECTOR ADDRESSES IN 8085
Intel 8085 supports both software and hardware interrupts.
Software interrupts are in the form of instructions; hardware interrupts are applied as signals
from external devices.
Software Interrupts
The Intel 8085 instruction set includes eight software interrupt instructions called Restart
(RST) instructions.
These are one-byte instructions that make the processor execute a subroutine at predefined
locations.
The eight software interrupt instructions and their interrupt vector addresses are given in Table
9. Hardware Interrupts and Priorities
Intel 8085 has five hardware interrupts—INTR, RST 5.5, RST 6.6, RST 7.5, and
Trap.
The details of the five interrupts are given in Table
10. INTERRUPT SOURCES AND VECTOR ADDRESSES IN
8085
SIM Instruction
The SIM instruction is used to mask or unmask the restart (RST) hardware
interrupts.
The SIM instruction when executed reads the contents of the accumulator
and accordingly masks or unmasks the interrupts.
So the SIM instruction must be executed after storing the appropriate
control word in the accumulator
RIM Instruction
The RIM instruction is used to read the status of the interrupt mask bits.
When the RIM instruction is executed, the accumulator is loaded with the
current status of the interrupt masks and the pending interrupts.
11. 8259 PROGRAMMABLE INTERRUPT CONTROLLER
In a system, interrupts are used to handle routines such as reading ASCII characters
from a keyboard on interrupt basis, and detecting and performing emergency
operations such as sounding a fire alarm.
For this purpose, the processor has maskable and non-maskable interrupts.
However, the processor has a limited number of hardware interrupts.
For applications that use interrupts from multiple sources, the hardware can use an
external device called Programmable Interrupt Controller or Priority Interrupt
Controller.
13. 8259 PROGRAMMABLE INTERRUPT CONTROLLER
In 8085-based systems, the interrupt vector address is provided by a three-byte CALL
instruction.
In 8086-based systems, it is provided by an 8-bit vector number. It can be operated in
polled and vectored mode.
The starting address of the ISR or vector number is programmable. No clock is
required for the IC.
Using the read/write logic, the 8259 is interfaced with the processor.
The data bus lines D0-D7 are connected to the data lines of the processor. The 8259
chip is selected using the CS line.
The address line A0 is used to select the control word or the data word.
If A0 is low, the controller selects the writing a command word/reading a status option.
If A0 is high, the controller selects another register for writing the initialization words.
15. The control logic has the signals INT and INTA. The INT output pin is used to interrupt
the CPU.
The 8259 receives the interrupt acknowledge pulse from the CPU through its INTA
input.
The 8259 can receive interrupt signals from eight different sources on the lines IR0-IR7.
When these lines go high, the requests are stored in the interrupt request register (IRR).
The interrupt service register (ISR) stores all the levels that are currently being serviced.
The interrupt mask register (IMR) stores the masking bits of the interrupt lines to be
masked.
The priority resolver examines the interrupt registers and determines whether the INT
signal should be sent to the microprocessor or not. The internal block diagram of the
interrupt controller is shown in Fig
16. The following three registers are used to program and control the operation of IC
8259:
Interrupt mask register (IMR)
Interrupt request register (IRR)
In-service register (ISR)
The interrupt mask register is used to program the masking of external interrupt
sources.
This register is written into by the programmer.
The interrupt request register is used to store the interrupts that have been sensed by
the 8259 at its inputs.
The in-service register maintains the list of interrupts that are currently being
serviced and the corresponding service routine that is being executed.
18. Pin Diagram and Details of 8259
The main signals in the 8259 are as follows:
Eight external interrupt request input lines—IR0-IR7
An interrupt request output line INT to be connected to the processor
Interrupt acknowledgment input INTA from the processor
Bidirectional data bus lines D0-D7 for data or commands from the processor
Control signals CAS0-CAS2 for cascading 8259s
Active low read control signal RD
Active low write control signal WR
Select line AO to select the control registers
Active low chip select line CS(x) Select line SP/EN to make the 8259 a slave or a
master
22. Format of lCW2 (Initialization Command Word 2)
In the 8085, ICW2 is used to set the higher-order eight bits of
the interrupt vector addresses.
In the 8086, it defines the 8-bit vector address. This
initialization word is written into the 8259 with AO = 1.
23. Format of ICW3 (Initialization Command Word 3)
• ICW3 is required only when the 8259 is connected in
cascaded mode, i.e., more than one 8259 is connected in the
system.
• This initialization word is written into the 8259 with AO = 1.
The format of ICW3 is given in Fig
24. Format of ICW4 (Initialization Command Word 4)
ICW4 is necessary only when its requirement is mentioned in ICW1.
It is used to indicate whether the 8085 or the 8086 is being used in the system.
It also indicates the usage of end of interrupt mode, buffered/non-buffered mode,
and special fully nested mode.
The format of ICW4 is given in Table. This initialization word is written into the
8259 with A0 = 1.
27. OCW1 (Operational Command Word 1)
OCW1 is written into the 8259 with A0 = 1.
This word is used to mask the interrupt requests IR0-IR7.
The eight bits of the OCW1 are used to mask the eight interrupts, with the LSB D0
masking IR0 and the MSB D7 masking IR7.
A particular interrupt IRn is masked by setting the corresponding bit Mn to 1; the mask
is cleared by setting the corresponding bit Mn to 0 (where n is the number of the bit and
ranges from 0 to 7).
The format of OCW1 is given in Fig
29. OCW2 (Operational Command Word 2)
OCW2 is written into the 8259 with AO = 1.
This word is used to specify priorities of interrupts and issue of end of interrupt
commands.
OCW2 is usually written to reset the bit in the in-service register.
Normally, a bit is set in the in-service register when the corresponding interrupt
is being serviced.
OCW2 is generally written at the end of the interrupt service routine.
The OCW2 can be programmed for non-specific end of interrupt mode with the
data 0010 0000 to automatically reset the in-service register (ISR) bit.
The programmer can also use OCW2 to reset a specific ISR bit and rotate the
priorities of the interrupts.
33. METHODS OF DATA TRANSFER AND INTERRUPT
STRUCTURE IN 8085
DATA TRANSFER MECHANISMS
Data transfer is essential in any microprocessor-based system.
It can take place between the processor and the memory, the
processor and an input/output device, or the memory and an
input/output device.
Data can be transferred in several ways.
The mechanism differs based on characteristics such as the
addressing of the devices, amount of data transferred, method of
data transfer, and interaction among the devices.
34. The data transfer mechanism is divided into the following types:
Based on the addressing of the device
I/O-mapped I/O access (ii) Memory-mapped I/O access
Based on the program and hardware involved
Programmed data transfer
Polled mode of data transfer (b) Interrupt-driven data transfer
Direct memory access
Burst mode (b) Cycle stealing mode
35. METHODS OF DATA TRANSFER AND INTERRUPT
STRUCTURE IN 8085
Based on the method of data transfer and access
Parallel data transfer
Simple data transfer (b) Handshake mode data transfer
Serial data transfer
(a) Synchronous data transfer (b) Asynchronous data transfer
36. MEMORY-MAPPED AND l/O-MAPPED DATA TRANSFER
In I/O-mapped device data transfer method, I/O devices and memory are handled separately.
A separate address range is assigned for input/output devices. Separate control signals are used
for memory access and for I/O device read/write operation.
The microprocessor has separate instructions for input and output device access, such as the IN
and OUT instructions of the 8085.
As memory and I/O device accesses are governed by separate control signals, a single address
can be assigned to both an I/O device and a memory location.
In memory-mapped I/O, each input/output device is treated like a memory location.
The same control signals are used for I/O device read/write operation and for memory access.
Each input or output device is identified by a unique address in the memory address range.
All memory-related instructions that are used to read data from memory are used to access
input and output devices.
Since the I/O devices use some of the memory address space, the maximum memory
addressing capacity is reduced in this system.
37. MEMORY-MAPPED AND l/O-MAPPED DATA TRANSFER
Features Memory Mapped IO IO Mapped IO
Addressing IO devices are accessed like any other
memory location
They cannot be accessed like any
other memory location.
Address Size They are assigned with 16-bit address values. They are assigned with 8-bit address
values.
Instructions Used The instruction used are LDA and STA, etc. The instruction used are IN and OUT.
Registers
Communicating
Any register can communicate with the IO
device in case of Memory Mapped IO.
Only Accumulator can communicate
with IO devices in case of IO Mapped
IO.
IO/M` signal During writing or read cycles (IO/M` = 0 ) in
case of Memory Mapped IO.
During writing or read cycles (IO/M`
= 1) in case of IO Mapped IO.
Design complexity Simple to implement and design More complex to implement and
design
38. PROGRAMMED DATA TRANSFER
The instructions for programmed data transfer are written and controlled by the
programmer and executed by the processor.
The data transfer between the processor and I/O devices (and vice versa) takes
place by executing the corresponding instructions.
Programmed I/O data transfers are identical to read and write operations for
memories and device registers.
An example of programmed I/O is a device driver writing one data byte at a time
directly into the device’s memory.
Programmed data transfer can take place at a time determined by the programmer.
Based on the time of execution of the data transfer instruction, programmed data
transfer is divided into two types—polled mode of data transfer and interrupt-
driven data transfer.
39. DIRECT MEMORY ACCESS
In programmed I/O data transfer, the processor is actively involved in the entire data
transfer process.
So, the data transfer rate is limited.
The processor is tied up and processor time is wasted. To overcome these disadvantages,
the direct memory access (DMA) method of data transfer is used.
Under normal circumstances, the CPU has full control of the address and data buses in the
system.
When direct memory access occurs, an external device or DMA controller takes over the
temporary control of the system bus from the CPU.
The CPU writes necessary control words into the DMA controller, to indicate the following
details about the data transfer: read or write operation, device address involved, starting
address of the data memory block and the amount of data to be transferred.
After this initialization, the DMA controller takes care of the data transfer.
In the 8085, the hold request is received and acknowledged using the HOLD and HLDA
pins, respectively.
40. METHODS OF DATA TRANSFER AND INTERRUPT
STRUCTURE IN 8085
The sequence of events in a typical DMA process is as follows:
The peripheral or the DMA controller asserts one of the request pins (such as HOLD) for
holding the processor.
The processor completes its current instruction and enters into the Hold state. In the Hold
state, the processor temporarily stops the execution of the instruction and releases the address
and data buses by making them enter into a high impedance state.
The processor issues a Hold Acknowledge (HLDA) signal to indicate the release of bus
control to the peripheral or the DMA controller.
The DMA operation starts.
Upon completion of the DMA operation, the peripheral or the DMA controller removes the
Hold signal applied to the processor and relinquishes bus control.
41. METHODS OF DATA TRANSFER AND INTERRUPT
STRUCTURE IN 8085
PARALLEL DATA TRANSFER
• In parallel mode of data transfer, all the bits in a word are simultaneously transmitted.
• Since the 8085 word consists of eight bits, all the eight bits are transmitted and
received in parallel form.
• In some special cases, the number of data bits transferred will be lesser than eight.
• In general, parallel data transfer is used for transfer of data over short distances such
as within a system, within a printed circuit board (PCB), etc.
• It can be done either in polled mode or in interrupt-driven mode.
• In polled method, data is read from the input device by the processor at a time
determined by the processor. This polled mode of data transfer can be done in two
ways—synchronous or simple I/O and handshake I/O.
42. SERIAL DATA TRANSFER
Parallel data transfer has the drawback of needing several wires to transfer all the
bits of data.
So, it can not be used effectively for long distance transfers.
As one wire is used for each bit, byte-wise data transfers are eight times more
expensive than a single bit transfer.
Serial data transfer is the solution for data transfers over long distances. It is a low-
cost way to send data over long distances.
In serial data transfer, only one bit is transferred over a data transfer line.
All the bits in a data word can be transmitted by using a shift register and
transferring the data bit by bit. Parallel-to-serial data conversion is done by a
device called Universal Asynchronous Receiver-Transmitter (UART).
43. In serial data transfer, the following three aspects are important: First, the speed
or frequency at which the bits are transmitted into the serial data line.
The frequency at which the data is transmitted serially is technically called baud
rate.
Baud rate is the measure of the number of bits transmitted over a second.
Second, the mode of data transfer.
Serial data transfer can be done in two modes— synchronous and asynchronous.
Third, the voltage levels for logic 1 and logic 0 for the data being transmitted.
Various serial communication protocols define these aspects as standards for
proper communication.
44. Introduction to RS-232 Standard
RS-232 is a serial communication standard given by the Electronic Industries
Association (EIA), an organization represented by a group of electronic industries.
It is used for one-to-one communication between two computers or processor
systems.
RS-232 standard can also be used with modems. RS-232 can be used to interface a
processor system or DTE with a modem/DCE.
It is the standard used on personal computers’ COM port. The maximum possible
speed with RS-232 is 20 kbps and the maximum possible cable length is 50 feet.
46. 8237 DMA CONTROLLER
Programmed data transfers involve moving data from the memory into the accumulator,
and then from the accumulator to the output ports.
A program has to be written to transfer data from a device to the memory.
Thus, programmed data transfer is a slow process. This causes a problem while
transferring large amounts of data.
DMA stands for direct memory access.
It is one of the ways to accomplish high-speed data transfer directly between the memory and
peripheral devices, without the intervention of the microprocessor.
This method is often used when a large block of data is to be transferred.
Thus, the DMA controller temporarily borrows the address bus, data bus, and control bus from
the microprocessor and transfers the data bytes directly from the external peripheral devices to a
series of memory locations.
Since the data transfer is done by hardware means, it is much faster than it would be if done by
program instructions.
47. FEATURES OF 8237
Four independent DMA channels
Enable and disable control of individual requests
Possibility of memory-to-memory transfer
Address increment or decrement
Cascading to expand to any number of DMA channels
50. DB0-DB7 (I/O data bus): The data bus lines are bidirectional three-state signals
connected to the system data bus, which carries data.
CLK (clock input): The clock input is used to generate the timing signals that
control 82C37A operations. This input may be driven from DC to 12.5 MHz for the
82C37A-12, from DC to 8 MHz for the 82C37A, and from DC to 5 MHz for the
82C37A-5. The clock may be stopped either in 1 state or in 0 state for standby
operation.
CS (Chip Select): Chip Select is an active low input used to enable the controller.
Reset: This is an active high input which clears the command, status, request, and
temporary registers, the first/last flip-flop, and the mode register counter. The mask
register is set to ignore requests. Following a reset, the controller is in an idle cycle.
Ready: This signal can be used to extend the memory read and write pulses
from the 8237 to accommodate slow memories or I/O devices.
HLDA (Hold Acknowledge): The active high Hold Acknowledge from the
CPU indicates that it has handed over control of the system buses.
51. DREQ0-DREQ3 (DMA request): The DMA request (DREQ) lines are individual asynchronous
channel request inputs used by peripheral circuits to obtain DMA service. In fixed priority mode,
DREQO has the highest priority and DREQ3 has the lowest priority. A request can be generated
by activating the DREQ line of a channel. The polarity of the DREQ is programmable. Reset
signal initializes these lines to active high. The DREQ must be maintained until the
corresponding DACK goes active. It will not be recognized while the clock is stopped.
IOR (I/O read): I/O read is a bidirectional active low three-state line. In the idle or slave mode, it
is an input control signal used by the CPU to read the control registers. In the active or master
mode, it is an output control signal used by the 8237 to access data from the peripheral during a
DMA write transfer.
IOW (I/O write): I/O write is a bidirectional active low three-state line. In the idle cycle, it is an
input control signal used by the CPU to load information into the 8237. In the active cycle, it is
an output control signal used by the 8237 to load data in the peripheral during a DMA read
transfer.
52. EOP (end of process): EOP is an active low bidirectional signal. Information
concerning the completion of DMA services is available at the bidirectional EOP
pin. A pulse is generated by the 8237 when terminal count (TC) for any channel is
reached, except for channel 0 in memory-to-memory mode.
A0-A3 (I/O address): The four least significant address lines are bidirectional three-
state signals. In the idle cycle, they are inputs and are used by the 8237 to address
the control register to be loaded or read. In the active cycle, they are outputs and
provide the lower four bits of the output address.
A4-A7 (address): The four most significant address lines are three-state outputs and
provide four bits of address. These lines are enabled only during the DMA service.
HRQ (Hold Request): The Hold Request (HRQ) output is used to request control of
the system bus. When a DREQ occurs and the corresponding mask bit is clear, or a
software DMA request is made, the 82C37A issues HRQ. The HLDA signal then
informs the controller when access to the system buses is permitted.
53. DACK0-DACK3 (DMA Acknowledge): DMA Acknowledge is used to notify the
individual peripherals when one has been granted a DMA cycle. DACK
acknowledges the recognition of a DREQ signal.
AEN (Address Enable): The address enable signal is an active high signal used to
indicate the availability of the higher-order 8-bit address. It can be used by the latch
to store the address. AEN can also be used to disable other system bus drivers
during DMA transfers. AEN is an active high signal.
ADSTB (Address Strobe): This is an active high signal used to control latching of
the upper address byte.
MEMR (Memory Read): The Memory Read signal is an active low three- state
output used to access data from the selected memory location during a DMA read
or a memory-to-memory transfer.
MEMW (Memory Write): The Memory Write signal is an active low three- state
output used to write data to the selected memory location during a DMA write or a
memory-to-memory transfer.
54. INTEL TIMER IC 8253
In programming the 8085, we have seen that a delay subroutine can be used to introduce a
predefined time delay.
The delay is achieved by decrementing a count value in a register using appropriate
instructions.
The disadvantage of this software approach is that the processor is locked in the delay loop
and processor time is lost in counting.
This can be overcome by using hardware timer and interrupts. IC 555 can be used to generate
timing signals, but only at fixed time intervals. However, it cannot be easily interfaced with the
microprocessor. So Intel has produced programmable timer devices, IC 8253 and IC 8254.
These devices can be programmed to generate different types of delay signals and also count
external signals. Other counter/timer functions that are commonly implemented with the 8253
are programmable frequency square wave generator, event counter, real time clock, digital
one-shot, and complex motor controller.
55. Features of IC 8253 & 8254
The following is the list of major features of IC 8253:
(i) Generation of accurate time delay
(ii) Three independent 16-bit down counters called channels
(iii) Six different programmable operating modes
(iv) Timer or counter operation
(v) Counting in binary or BCD
(vi) Capability to interrupt the processor
(vii) Single+5 V supply
(viii) Operation in both DC and AC (up to 2.6 MHz)
8254
Operating frequency is 10 MHz
Read write command available-which allows the user to check the count value, current mode
and current status of the counter.
Read and write of the same counter can be interleaved.
58. INTEL TIMER IC 8253
The internal block diagram of IC 8253 shows the three independent 16-bit timers—
counters 0, 1, and 2.
These counters are programmer-controlled; the programmer can initialize the count value
and start the counting process.
The initialization is done through the data bus of the system.
Counting can be started and stopped using software instructions written into the control
register.
The count value in the counter can be read by the programmer at any time, using the
appropriate command word, through the data bus of the system.
Each counter has two pins, CLK (clock input) and GATE, for input and one pin, OUT, for
output.
The control input line GATE is used to start or stop the counting operation.
The Out signal from each counter can be used to indicate the completion of required
counting or timing operation and also to interrupt the processor.
59. An 8-bit data bus is available in the 8253 to interface the IC with the
microprocessor.
The control signal CS is used to select the chip.
This active low signal can be activated using the address lines and the decoder.
In addition, the 8253 requires two address lines A0 and A1 to be issued from the
8085 hardware.
These address lines are used to select one of four registers (three counters and one
control register) in the 8253.
64. In mode 0, the counter is used to issue an output after counting up to the pre
initialized value.
The initial count value is loaded into the counter and gets decremented every clock
pulse.
The Gate signal input also controls the counting operation.
The output line OUT is made high from low, when the count value becomes 0.
The Out signal becomes low when the counter is loaded with the next count value.
65. Mode 1: Hardware-triggered One-shot
Mode 1 is similar to mode 0, but has a minor difference.
The similarity between the modes is that the output becomes low while counting down and
becomes high once the count value reaches zero.
The first difference between the modes 0 and 1 is that in mode 1, the counting is
started/triggered whenever the Gate input becomes high.
The second difference is that in mode 1, the count value is reloaded if in the middle of the
count the Gate goes low and becomes high again.
This operation of the counter is similar to that of a monostable multivibrator, with the Gate
input signal acting as the trigger input to the multivibrator.
The duration of low output is the quasi-stable state of the multivibrator and is decided by the
count value loaded initially.
67. Mode 2: Rate Generator
In mode 2, the counter generates continuous signals in the output line.
The down counting starts once the counter is loaded with the count value.
In this mode, the output signal becomes high once the counting starts.
The output becomes low, only during the last clock cycle of the count. After this,
the count becomes zero.
68. Mode 3: Square Wave Generator
The operation of modes 3 and 2 are similar, except that the output is a square wave
with equal low and high periods in mode 3.
If the count value is loaded with n, the output will be low for n/2 clock periods and
high for n/2 clock periods.
If n is odd, the output will be high for a (n + l)/2 clock periods and low for a (n -
l)/2 clock periods.
The counting will be reinitialized once the count value reaches zero. Thus, the
square wave will be generated continuously. The frequency of the output square
waveform will be given by the input clock frequency divided by the count value.
70. Mode 4: Software-triggered Strobe
In mode 4, the down-counting in the counter is initiated by writing the count value in
the counter.
The output will be low during the last clock period of every count cycle.
The Gate input controls the counting and will reinitialize the count value, as shown
in.
An input of 0 on the Gate input pin inhibits the counting.
71. Mode 5: Hardware-triggered Strobe
Mode 5 of the timer IC 8253 is similar to mode 4, with the difference that the
counting is triggered by the Gate input signal and not by the writing of the count
value by the software.
The output is high once the count value is loaded.
Counting starts on the rising edge of the gate pulse.
The output is low during the last count of the counter.
