8259 programmable PPI interfacing with 8085 .ppt
- 2. 8259 Spacial Features • 8086, 8088 Compatible • MCS-80, MCS-85 Compatible • Eight-Level Priority Controller • Expandable to 64 Levels • Programmable Interrupt Modes • Individual Request Mask Capability
- 3. Interrupts in Microcomputer System Microcomputer system design requires that I.O devices such as keyboards, displays, sensors and other components receive servicing in an efficient manner so that large amounts of the total system tasks can be assumed by the microcomputer with little or no effect on throughput
- 4. General Method :Polled Method The most common method of servicing such devices is the Polled approach. This is where the processor must test each device in sequence and in effect ``ask'' each one if it needs servicing. It is easy to see that a large portion of the main program is looping through this continuous polling cycle and that such a method would have a serious detrimental effect on system throughput, thus limiting the tasks that could be assumed by the microcomputer and reducing the cost effectiveness of using such devices
- 5. A More Reliable Method : Interrupt A more desirable method would be one that would allow the microprocessor to be executing its main program and only stop to service peripheral devices when it is told to do so by the device itself. In effect, the method would provide an external asynchronous input that would inform the processor that it should complete whatever instruction that is currently being executed and fetch a new routine that will service the requesting device. Once this servicing is complete, however, the processor would resume exactly where it left off
- 6. What is PIC & Why should we opt for it ? The Programmable Interrupt Controller (PIC) functions as an overall manager in an Interrupt-Driven system environment. It accepts requests from the peripheral equipment, determines which of the incoming requests is of the highest importance (priority), ascertains whether the incoming request has a higher priority value than the level currently being serviced, and issues an interrupt to the CPU based on this determination. Each peripheral device or structure usually has a special program or ``routine'' that is associated with its specific functional or operational requirements ; this is referred to as a ``service routine''. The PIC, after issuing an Interrupt to the CPU, must somehow input information into the CPU that can ``point'' the Program Counter to the service routine associated with the requesting device. This ``pointer'' is an address in a vectoring table and will often be referred to as vectoring data.
- 9. IRR and ISR INTERRUPT REQUEST REGISTER (IRR) AND IN-SERVICE REGISTER (ISR) The interrupts at the IR input lines are handled by two registers in cascade, the Interrupt Request Register (IRR) and the In-Service (ISR). The IRR is used to store all the interrupt levels which are requesting service; and the ISR is used to store all the interrupt levels which are being serviced.
- 10. Priority Resolver This logic block determines the priorities of the bits set in the IRR. The highest priority is selected and strobed into the corresponding bit of the ISR during INTA pulse.
- 11. Interrupt Mask Register The IMR stores the bits which mask the interrupt lines to be masked. The IMR operates on the IRR. Masking of a higher priority input will not affect the interrupt request lines of lower quality.
- 12. INT(Interrupt) This output goes directly to the CPU interrupt input. The VOH level on this line is designed to be fully compatible with the 8080A, 8085A and 8086 input levels.
- 13. INTA(Interrupt Acknowledgement) INTA pulses will cause the 8259A to release vectoring information onto the data bus. The format of this data depends on the system mode of the 8259A.
- 14. Data Bus Buffer This 3-state, bidirectional 8-bit buffer is used to interface the 8259A to the system Data Bus. Control words and status information are transferred through the Data Bus Buffer
- 15. Read-Write Control Logic The function of this block is to accept OUTput commands from the CPU. It contains the Initialization Command Word (ICW) registers and Operation Command Word (OCW) registers which store the various control formats for device operation. This function block also allows the status of the 8259A to be transferred onto the Data Bus
- 16. Chip Select ( CS ) A LOW on this input enables the 8259A. No reading or writing of the chip will occur unless the device is selected A0 This input signal is used in conjunction with WR and RD signals to write commands into the various command registers, as well as reading the various status registers of the chip. This line can be tied directly to one of the address lines
- 17. RD & WR A LOW on WR input enables the CPU to write control words (ICWs and OCWs) to the 8259A. A LOW on RD input enables the 8259A to send the status of the Interrupt Request Register (IRR), In Service Register (ISR), the Interrupt Mask Register (IMR), or the Interrupt level onto the Data Bus.
- 18. 8259A Block Diagram (Repeat)
- 19. The Cascade Buffer/Comparator This function block stores and compares the IDs of all 8259A's used in the system. The associated three I/O pins (CAS0-2) are outputs when the 8259A is used as a master and are inputs when the 8259A is used as a slave. As a master, the 8259A sends the ID of the interrupting slave device onto the CAS 0-2 lines. The slave thus selected will send its preprogrammed subroutine address onto the Data Bus during the next one or two consecutive INTA pulses.
- 20. INTERRUPT SEQUNCE The events occur as follows in an MCS-80/85 system: 1. One or more of the INTERRUPT REQUEST lines (IR7-0) are raised high, setting the corresponding IRR bit (s). 2. The 8259A evaluates these requests, and sends an INT to the CPU, if appropriate. 3. The CPU acknowledges the INT and responds with an INTA pulse. 4. Upon receiving an INTA from the CPU group, the highest priority ISR bit is set, and the corresponding IRR bit is reset. The 8259A will also release a CALL instruction code (11001101) onto the 8-bit Data Bus through its D0-7 pins. 5. This CALL instruction will initiate two more INTA pulses to be sent to the 8259A from the CPU group. 6. These two INTA pulses allow the 8259A to release its preprogrammed subroutine address onto the Data Bus. The lower 8-bit address is released at the first INTA pulse and the higher 8-bit address is released at the second INTA pulse. 7. This completes the 3-byte CALL instruction released by the 8259A. In the AEOI mode the ISR bit is reset at the end of the third INTA pulse. Otherwise, the ISR bit remains set until an appropriate EOI command is issued at the end of the interrupt sequence.
- 21. INTERRUPT SEQUENE(CONT.) If no interrupt request is present at step 4 of either sequence (i.e., the request was too short in duration) the 8259A will issue an interrupt level 7. Both the vectoring bytes and the CAS lines will look like an interrupt level 7 was requested. When the 8259A PIC receives an interrupt, INT becomes active and an interrupt acknowledge cycle is started. If a higher priority interrupt occurs between the two INTA pulses, the INT line goes inactive immediately after the second INTA pulse. After an unspecified amount of time the INT line is activated again to signify the higher priority interrupt waiting for service. This inactive time is not specified and can vary between parts. The designer should be aware of this consideration when designing a system which uses the 8259A. It is recommended that proper asynchronous design techniques be followed.
- 22. 8259 Interface to Standard System Bus
- 23. Interrupt Sequence Outputs This sequence is timed by three INTA pulses. During the first INTA pulse the CALL opcode is enabled onto the data bus. Content of First Interrupt Vector Byte - D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 0 1 1 0 1 During the second INTA pulse the lower address of the appropriate service routine is enabled onto the data bus. When Interval = 4 bits A5-A7 are programmed, while A0-A4 are automatically inserted by the 8259A. When Interval = 8 only A6 and A7 are programmed, while A0-A5 are automatically inserted.
- 24. Interrupt Sequence Outputs (Contd.) IR Interval = 4 D7 D6 D5 D4 D3 D2 D1 D0 7 A7 A6 A5 1 1 1 0 0 6 A7 A6 A5 1 1 0 0 0 5 A7 A6 A5 1 0 1 0 0 4 A7 A6 A5 1 0 0 0 0 3 A7 A6 A5 0 1 1 0 0 2 A7 A6 A5 0 1 0 0 0 1 A7 A6 A5 0 0 1 0 0 0 A7 A6 A5 0 0 0 0 0 IR Interval = 8 D7 D6 D5 D4 D3 D2 D1 D0 7 A7 A6 1 1 1 0 0 0 6 A7 A6 1 1 0 0 0 0 5 A7 A6 1 0 1 0 0 0 4 A7 A6 1 0 0 0 0 0 3 A7 A6 0 1 1 0 0 0 2 A7 A6 0 1 0 0 0 0 1 A7 A6 0 0 1 0 0 0 0 A7 A6 0 0 0 0 0 0
- 25. Interrupt Sequence Outputs (Contd.) During the third INTA pulse the higher address of the appropriate service routine, which was programmed as byte 2 of the initialization sequence (A8-A15), is enabled onto the bus. Content of Third Interrupt Vector Byte D7 D6 D5 D4 D3 D2 D1 D0 A15 A14 A13 A12 A11 A10 A9 A8
- 26. PROGRAMMING THE 8259A The 8259A accepts two types of command words generated by the CPU: 1. Initialization Command Words (ICWs): Before normal operation can begin, each 8259A in the system must be brought to a starting point by a Sequence of 2 to 4 bytes timed by WR pulses. 2. Operation Command Words (OCWs): These are the command words which command the 8259Ato operate in various interrupt modes. These modes are: a. Fully nested mode b. Rotating priority mode c. Special mask mode d. Polled mode The OCWs can be written into the 8259A anytime after initialization.
- 28. ICW Format ICW 1: A0 D0 D1 D2 D3 D4 D5 D6 D7 0 A7 A6 A5 1 LTIM ADI SNGL IC 4 IC4=1 ICW4 needed IC4=0 ICW4 not needed SNGL=1 Single SNGL=0 Cascade Mode LTIM=1 Level Triggered Mode LTIM=0 Edge Triggered Mode A5-A7 Vector Addresses
- 29. ICW Format ( contd.) ICW 2: A0 D0 D1 D2 D3 D4 D5 D6 D7 1 A15/T7 A14/T6 A13/T5 A12/T4 A11/T3 A10 A9 A8 A8 – A15 (VECTOR ADDRESSES in case of MCS 80/85 system) T3-T7 (VECTOR ADDRESSES in case of MCS 8086/8088 system)
- 30. ICW Format (contd.) ICW 3: (MASTER MODE) A0 D0 D1 D2 D3 D4 D5 D6 D7 1 S7 S6 S5 S4 S3 S2 S1 S0 S0 – S7 = 1, IR input has a slave = 0, IR input does not have a slave ICW 3: (SLAVE MODE) A0 D0 D1 D2 D3 D4 D5 D6 D7 1 0 0 0 0 0 ID2 ID1 ID0 ID0-2 = Slave IDs
- 31. Operation Command Words (OCW) OCW1:- A0 D7 D6 D5 D4 D3 D2 D2 D1 D0 1 M7 M6 M5 M4 M4 M3 M2 M1 M0 Interrupt Mask = 1 Mask Set = 0 Mask Reset
- 32. Operation Command Words (OCW) (contd.) OCW 2:- A0 D7 D6 D5 D4 D3 D2 D1 D0 0 R SL EOI 0 0 L2 L1 L0 0 0 1 - Non-Specific EOI Command 0 1 1 - Specific EOI Command 1 0 1 - Rotate on Non-Specific EOI Command 1 0 0 - Rotate in automatic EOI mode (Set) 0 0 0 - Rotate in automatic EOI mode (Clear) 1 1 1 - Rotate on Specific EOI command 1 1 0 - Set Priority Command 0 1 0 - No Opearation L0 – L2 = IR Level to be acted upon
- 33. Operation Command Words (OCW) (contd.) OCW 3 :- A0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 ESMM SMM 0 1 P RR RIS No Action 0 0 No Action 0 1 Read IR reg. on next RD pulse 1 0 Read IR reg. on next RD pulse 1 1 P =1 Poll Command =0 No Poll Command ESMM SMM 0 0 No Action 0 1 No Action 1 0 Reset Special Mask 1 1 Set Special Mask
- 34. OCW Description :- OCW 3 :- ESMM (Enable Special Mask Mode) - When this bit is set to 1 it enables the SMM bit to set or reset the Special Mask Mode. When ESMM e 0 the SMM bit becomes a ``don't care''. SMM (Special Mask Mode) - If ESMM = 1 and SMM = 1 the 8259A will enter Special Mask Mode. If ESMM = 1 and SMM = 0 the 8259A will revert to normal mask mode. When ESMM = 0, SMM has no effect.
- 35. Fully Nested Mode This mode is entered after initialization unless another mode is programmed. The interrupt requests are ordered in priority from 0 through 7 (0 highest). When an interrupt is acknowledged the highest priority request is determined and its vector placed on the bus. Additionally, a bit of the Interrupt Service register (ISO-7) is set. This bit remains set until the microprocessor issues an End of Interrupt (EOI) command immediately before returning from the service routine, or if AEOI (Automatic End of Interrupt) bit is set, until the trailing edge of the last INTA. While the IS bit is set, all further interrupts of the same or lower priority are inhibited, while higher levels will generate an interrupt (which will be acknowledged only if the microprocessor internal Interrupt enable flip-flop has been re- enabled through software). After the initialization sequence, IR0 has the highest prioirity and IR7 the lowest. Priorities can be changed, as will be explained, in the rotating priority mode.
- 36. EOI (End Of Interrupt) The In Service (IS) bit can be reset either automatically following the trailing edge of the last in sequence INTA pulse (when AEOI bit in ICW1 is set) or by a command word that must be issued to the 8259A before returning from a service routine (EOI command). An EOI command must be issued twice if in the Cascade mode, once for the master and once for the corresponding slave. There are two forms of EOI command: Specific and Non-Specific. When the 8259A is operated in modes which preserve the fully nested structure, it can determine which IS bit to reset on EOI. When a Non-Specific EOI command is issued the 8259A will automatically reset the highest IS bit of those that are set, since in the fully nested mode the highest IS level was necessarily the last level acknowledged and serviced. A non-specific EOI can be issued with OCW2 (EOI = 1, SL = 0, R = 0). When a mode is used which may disturb the fully nested structure, the 8259A may no longer be able to determine the last level acknowledged. In this case a Specific End of Interrupt must be issued which includes as part of the command the IS level to be reset. A specific EOI can be issued with OCW2 (EOI =1, SL=1, R= 0, and L0-L2 is the binary level of the IS bit to be reset). It should be noted that an IS bit that is masked by an IMR bit will not be cleared by a non-specific EOI if the 8259A is in the Special Mask Mode.
- 37. Automatic End of Interrupt (AEOI) Mode If AEOI =1 in ICW4, then the 8259A will operate in AEOI mode continuously until reprogrammed by ICW4 , in this mode the 8259A will automatically perform a non-specific EOI operation at the trailing edge of the last interrupt acknowledge pulse (third pulse in MCS-80/85, second in 8086). Note that from a system standpoint, this mode should be used only when a nested multilevel interrupt structure is not required within a single 8259A. The AEOI mode can only be used in a master 8259A and not a slave. 8259As with a copyright date of 1985 or later will operate in the AEOI mode as a master or a slave.
- 38. AUTOMATIC ROTATION In some applications there are a number of interrupting devices of equal priority. In this mode a device, after being serviced, receives the lowest priority, so a device requesting an interrupt will have to wait, in the worst case until each of 7 other devices are serviced at most once . For example, if the priority and ``in service'' status is: Before Rotate (IR4 the highest priority requiring service) :- IS7 IS6 IS5 IS4 IS3 IS2 IS1 IS0 0 1 0 1 0 0 0 0 IS STATUS 7 6 5 4 3 2 1 0 Priority Status After Rotate (IR4 the highest priority requiring service) :- IS7 IS6 IS5 IS4 IS3 IS2 IS1 IS0 0 1 0 0 0 0 0 0 IS STATUS 2 1 0 7 6 5 4 3 Priority Status
- 39. Specific Rotation (Specific Priority) The programmer can change priorities by programming the bottom priority and thus fixing all other priorities ;i.e., if IR5 is programmed as the bottom priority device, then IR6 will have the highest one. The Set Priority command is issued in OCW2 where: R=1, SL=1, L0-L2 is the binary priority level code of the bottom priority device. Observe that in this mode internal status is updated by software control during OCW2. However, it is independent of the End of Interrupt (EOI) command (also executed by OCW2). Priority changes can be executed during an EOI command by using the Rotate on Specific EOI command in OCW2 (R=1, SL=1, EOI=1 and LO-L2 IR level to receive bottom priority).
- 40. INTERRUPT MASK Each Interrupt Request input can bem masked individually by the Interrupt Mask Register (IMR) programmed through OCW1. Each bit in the IMR masks one interrupt channel if it is set (1). Bit 0 masks IR0,Bit 1 masks IR1 and so forth. Masking an IR channel does not affect the other channels operation. SPECIAL MASK MODE Some applications may require an interrupt service routine to dynamically alter the system priority structure during its execution under software control. For example, the routine may wish to inhibit lower priority requests for a portion of its execution but enable some of them for another portion. The difficulty here is that if an Interrupt Request is acknowledged and an End of Interrupt command did not reset its IS bit (i.e., while executing a service routine), the 8259A would have inhibited all lower priority requests with no easy way for the routine to enable them. That is where the Special Mask Mode comes in. In the special Mask Mode, when a mask bit is set in OCW1, it inhibits further interrupts at that level and Enables interrupts from all other levels (lower as well as higher) that are not masked. Thus, any interrupts may be selectively enabled by loading the mask register. The special Mask Mode is set by OWC3 where: SSMM =1, SMM =1, and cleared where SSMM =1, SMM = 0.
- 41. POLL COMMAND In Poll mode the INT output functions as it normally does. The microprocessor should ignore this output. This can be accomplished either by not connecting the INT output or by masking interrupts within the microprocessor, thereby disabling its interrupt input. Service to devices is achieved by software using a Poll command. The Poll command is issued by setting P = `1'' in OCW3. The 8259A treats the next RD pulse to the 8259A (i.e., RD e 0, CS e 0) as an interrupt acknowledge, sets the appropriate IS bit if there is a request, and reads the priority level. Interrupt is frozen from WR to RD. The word enabled onto the data bus during RD is: D7 D6 D5 D4 D3 D2 D1 D0 I - - - - w2 w1 w0 W0 - W2: Binary code of the highest priority level requesting service. I : Equal to ``1'' if there is an interrupt. This mode is useful if there is a routine command common to several levels so that the INTA sequence is not needed (saves ROM space). Another application is to use the poll mode to expand the number of priority levels to more than 64.
- 42. CASCADE MODE
- 43. CASCADE MODE (contd.) The 8259A can be easily interconnected in a system of one master with up to eight slaves to handle up to 64 priority levels. The master controls the slaves through the 3 line cascade bus. The cascade bus acts like chip selects to the slaves during the INTA sequence. In a cascade configuration, the slave interrupt outputs are connected to the master interrupt request inputs. When a slave request line is activated and afterwards acknowledged, the master will enable the corresponding slave to release the device routine address during bytes 2 and 3 of INTA. (Byte 2 only for 8086/8088). The cascade bus lines are normally low and will contain the slave address code from the trailing edge of the first INTA pulse to the trailing edge of the third pulse. Each 8259A in the system must follow a separate initialization sequence and can be programmed to work in a different mode. An EOI command must be issued twice: once for the master and once for the corresponding slave. An address decoder is required to activate the Chip Select (CS) input of each 8259A. The cascade lines of the Master 8259A are activated only for slave inputs, non- slave inputs leave the cascade line inactive (low).
- 44. The Special Fully Nested Mode This mode will be used in the case of a big system where cascading is used, and the priority has to be conserved within each slave. In this case the fully nested mode will be programmed to the master (using ICW4). This mode is similar to the normal nested mode with the following exceptions: A) When an interrupt request from a certain slave is in service this slave is not locked out from the master's priority logic and further interrupt requests from higher priority IR's within the slave will be recognized by the master and will initiate interrupts to the processor. (In the normal nested mode a slave is masked out when its request is in service and no higher requests from the same slave can be serviced.) B) When exiting the Interrupt Service routine the software has to check whether the interrupt serviced was the only one from that slave. This is done by sending a non-specific End of Interrupt (EOI) command to the slave and then reading its In-Service register and checking for zero. If it is empty, a non-specific EOI can be sent to the master too. If not, no EOI should be sent.
- 45. Buffered Mode When the 8259A is used in a large system where bus driving buffers are required on the data bus and the cascading mode is used, there exists the problem of enabling buffers. The buffered mode will structure the 8259A to send an enable signal on SP/EN to enable the buffers. In this mode, whenever the 8259A's data bus outputs are enabled, the SP/EN output becomes active. This modification forces the use of software programming to determine whether the 8259A is a master or a slave. Bit 3 in ICW4 programs the buffered mode, and bit 2 in ICW4 determines whether it is a master or a slave.