Minimum Modes and Maximum Modes of 8086 Microprocessor
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The document discusses the minimum and maximum modes of the Intel 8086 microprocessor. In minimum mode, the 8086 generates its own control signals to interface with memory and I/O, while in maximum mode it requires an 8288 bus controller to generate the control signals. Minimum mode has limitations and does not support the 8087 coprocessor, while maximum mode allows use of the coprocessor and provides additional functions. Key signals in minimum mode include the address/data bus lines, status lines, control signals like ALE and M/IO, and interrupt lines.
Minimum Modes and Maximum Modes of 8086 Microprocessor
- 1. NRI GROUP OF INSTITUTION • Prepared by: • Nikhil Kumar • Enroll no : 0511ec111056 • NIRT
- 2. INTEL (8086) HAS TWO OPERATION MODES: Minimum Mode Maximum Mode 8088 generates control signals for memory and I/O operations It needs 8288 bus controller to generate control signals for memory and I/O operations Some functions are not available in minimum mode It allows the use of 8087 coprocessor; it also provides other functions Compatible with 8085-based systems
- 3. MINIMUM MODE OF 8086 Microprocessor & Microcontroller Read Signal Write Signal Memory or I/0 Data Bus Enable Data Transmit/Receive
- 4. MINIMUM MODE OF 8086 • When the Minimum mode operation is selected, the 8086 provides all control signals needed to implement the memory and I/O interface. The minimum mode signal can be divided into the following basic groups : address/data bus, status, control, interrupt and DMA. • Address/Data Bus : these lines serve two functions. As an address bus is 20 bits long and consists of signal lines A0 through A19. A19 represents the MSB and A0 LSB. A 20bit address gives the 8086 a 1Mbyte memory address space. • More over it has an independent I/O address space which is 64K bytes in length. • The 16 data bus lines D0 through D15 are actually multiplexed with address lines A0 through A15 respectively. By multiplexed we mean that the bus work as an address bus during first machine cycle and as a data bus during next machine cycles. D15 is the MSB and D0 LSB. • When acting as a data bus, they carry read/write data for memory, input/output data for I/O devices, and interrupt type codes from an interrupt controller. • Status signal : The four most significant address lines A19 through A16 are also multiplexed but in this case with status signals S6 through S3. These status bits are output on the bus at the same time that data are transferred over the other bus lines.
- 5. MINIMUM MODE OF 8086 • Bit S4 and S3 together from a 2 bit binary code that identifies which of the 8086 internal segment registers are used to generate the physical address that was output on the address bus during the current bus cycle. • Code S4 S3 = 00 identifies a register known as extra segment register as the source of the segment address. • Status line S5 reflects the status of another internal characteristic of the 8086. It is the logic level of the internal enable flag. The last status bit S6 is always at the logic 0 level. • Control Signals : The control signals are provided to support the 8086 memory I/O interfaces. They control functions such as when the bus is to carry a valid address in which direction data are to be transferred over the bus, when valid write data are on the bus and when to put read data on the system bus. • ALE is a pulse to logic 1 that signals external circuitry when a valid address word is on the bus. This address must be latched in external circuitry on the 1-to-0 edge of the pulse at ALE. • Another control signal that is produced during the bus cycle is BHE bank high enable. Logic 0 on this used as a memory enable signal for the most significant byte half of the data bus D8 through D1. These lines also serves a second function, which is as the S7 status line. • Using the M/IO and DT/R lines, the 8086 signals which type of bus cycle is in progress and in which direction data are to be transferred over the bus.
- 6. MINIMUM MODE OF 8086 • The logic level of M/IO tells external circuitry whether a memory or I/O transfer is taking place over the bus. Logic 1 at this output signals a memory operation and logic 0 an I/O operation. • The direction of data transfer over the bus is signalled by the logic level output at DT/R. When this line is logic 1 during the data transfer part of a bus cycle, the bus is in the transmit mode. Therefore, data are either written into memory or output to an I/O device. • On the other hand, logic 0 at DT/R signals that the bus is in the receive mode. This corresponds to reading data from memory or input of data from an input port. • The signal read RD and write WR indicates that a read bus cycle or a write bus cycle is in progress. The 8086 switches WR to logic 0 to signal external device that valid write or output data are on the bus. • On the other hand, RD indicates that the 8086 is performing a read of data of the bus. During read operations, one other control signal is also supplied. This is DEN ( data enable) and it signals external devices when they should put data on the bus. • There is one other control signal that is involved with the memory and I/O interface. This is the READY signal.
- 7. MAXIMUM MODE OF 8086 DMA Request/Grant Lock Output Queue Status Used by numeric coprocessor (8087)
- 8. MAXIMUM MODE OF 8086