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Microprocessor And Microcontroller Interfacing (2150907)
Active Learning Assignment
on
Demultiplexing of Busses And Its Control Signal
Prepared By:
Patel RajalKumar H.
(160123109013)
Guided By :
Prof. Hitesh T. Manani
Electrical Department
Batch-B3
Gandhinagar Institute of Technology 1
Contents
 Introduction
 Demultiplexing
 Generation of control signal
 Truth table of control signal
 Conclusion
Gandhinagar Institute of Technology 2
Introduction
 The address bus has 8 signal lines A8 – A15 which are
unidirectional.
 The other 8 address bits are multiplexed(time shared) with the
8 data bits. So, the bits AD0 –AD7are bi-directional and serve
as A0 –A7and D0 –D7at the same time. During the execution
of the instruction, these lines carry the address bits during the
early part, then during the late parts of the execution, they
carry the 8 data bits.
 In order to separate the address from the data, we can use a
latch to save the value before the function of the bits changes.
Gandhinagar Institute of Technology 3
Demultiplexing of AD7-AD0
 From the above description, it becomes obvious that the AD7–
AD0 lines are serving a dual purpose and that they need to be
demultiplexed to get all the information.
 The high order bits of the address remain on the bus for three
clock periods. However, the low order bits remain for only one
clock period and they would be lost if they are not saved
externally. Also, notice that the low order bits of the address
disappear when they are needed most.
Gandhinagar Institute of Technology 4
 To make sure we have the entire address for the full three
clock cycles, we will use an external latch to save the value of
AD7–AD0 when it is carrying the address bits. We use the
ALE signal to enable this latch.
 Given that ALE operates as a pulse during T1, we will be able
to latch the address. Then when ALE goes low, the address is
saved and the AD7–AD0 lines can be used for their purpose as
the bi-directional data lines.
Gandhinagar Institute of Technology 5
Gandhinagar Institute of Technology 6
Generation of Control signal
Gandhinagar Institute of Technology 7
Truth Table of Control Signal
Gandhinagar Institute of Technology 8
Conclusion
 After study this topic I understand the de multiplexing of
busses.
 I understand how to bifurcate the address and data bus.
 I understand the generation of the control signal.
Gandhinagar Institute of Technology 9
Gandhinagar Institute of Technology 10

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Demultiplexing of buses of 8085 microprocessor

  • 1. Microprocessor And Microcontroller Interfacing (2150907) Active Learning Assignment on Demultiplexing of Busses And Its Control Signal Prepared By: Patel RajalKumar H. (160123109013) Guided By : Prof. Hitesh T. Manani Electrical Department Batch-B3 Gandhinagar Institute of Technology 1
  • 2. Contents  Introduction  Demultiplexing  Generation of control signal  Truth table of control signal  Conclusion Gandhinagar Institute of Technology 2
  • 3. Introduction  The address bus has 8 signal lines A8 – A15 which are unidirectional.  The other 8 address bits are multiplexed(time shared) with the 8 data bits. So, the bits AD0 –AD7are bi-directional and serve as A0 –A7and D0 –D7at the same time. During the execution of the instruction, these lines carry the address bits during the early part, then during the late parts of the execution, they carry the 8 data bits.  In order to separate the address from the data, we can use a latch to save the value before the function of the bits changes. Gandhinagar Institute of Technology 3
  • 4. Demultiplexing of AD7-AD0  From the above description, it becomes obvious that the AD7– AD0 lines are serving a dual purpose and that they need to be demultiplexed to get all the information.  The high order bits of the address remain on the bus for three clock periods. However, the low order bits remain for only one clock period and they would be lost if they are not saved externally. Also, notice that the low order bits of the address disappear when they are needed most. Gandhinagar Institute of Technology 4
  • 5.  To make sure we have the entire address for the full three clock cycles, we will use an external latch to save the value of AD7–AD0 when it is carrying the address bits. We use the ALE signal to enable this latch.  Given that ALE operates as a pulse during T1, we will be able to latch the address. Then when ALE goes low, the address is saved and the AD7–AD0 lines can be used for their purpose as the bi-directional data lines. Gandhinagar Institute of Technology 5
  • 7. Generation of Control signal Gandhinagar Institute of Technology 7
  • 8. Truth Table of Control Signal Gandhinagar Institute of Technology 8
  • 9. Conclusion  After study this topic I understand the de multiplexing of busses.  I understand how to bifurcate the address and data bus.  I understand the generation of the control signal. Gandhinagar Institute of Technology 9
  • 10. Gandhinagar Institute of Technology 10