Master synchronous serial port (mssp)
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The Master Synchronous Serial Port (MSSP) module allows communication with peripheral devices using either Serial Peripheral Interface (SPI) or Inter-Integrated Circuit (I2C) protocols. In SPI mode, data is synchronously transmitted and received on three pins - Serial Data Out, Serial Data In, and Serial Clock. The MSSP has registers for status, control, and buffering data during read and write operations according to the SPI protocol.
Master synchronous serial port (mssp)
- 1. MASTER SYNCHRONOUS SERIAL PORT (MSSP)MODULE • The Master Synchronous Serial Port (MSSP) module is a serial interface useful for communicating with other peripheral or micro controller devices. • These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters,SD Cards,USB devices etc. • The MSSP module can operate in one of two modes: – Serial Peripheral Interface (SPI) – Inter-Integrated Circuit (I2 C)
- 3. Control Registers • The MSSP module has three associated registers. • status register (SSPSTAT) and two control registers (SSPCON1 and SSPCON2). SPI Mode • SPI bus was started by Motorola Corp • The SPI mode allows 8-bits of data to be synchronously transmitted and received, simultaneously. • To accomplish communication, typically three pins are used: • Serial Data Out (SDO) - RC5/SDO • Serial Data In (SDI) - RC4/SDI/SDA • Serial Clock (SCK) - RC3/SCK/SCL/LVDIN • Additionally, a fourth pin may be used when in a Slave mode of operation: • Slave Select (SS) - RA5/SS/AN4
- 4. SPI Read and Write Protocol • In connecting a device with an SPI bus to µC, we use µC as the master while the SPI device acts as slave. • µC generates the SCLK, which is fed to SCLK pin of the SPI device, to synchronize the transfer of data one bit at a time, MSB goes in first. • During transfer, the SS(Slave Select) pin must be HIGH. • To distinguish b/w read and write, D7 bit of address byte(A7) is always 1 for write, and for read this bit is Low.
- 5. Steps for writing data to SPI device Single byte write • Make SS=0 to select the device for writing. • 8bit address is shifted in one bit at a time, with each edge of SCLK. A7 =1 for the write operation and the A7 bit goes in first. • After all 8bits of the address are sent in, the SPI device expects to receive the data belonging to address location immediately. • The 8bit data is shifted in one bit at a time,with each edge of SCLK. • Make SS =0 to indicate the end of write cycle.
- 6. Multi byte burst write • SS=0 • 8bit address of first location is provided and shifted one bit at a time, each edge of SCLK A7=1 for the write operation and A7 bit goes in first. • The 8bit data for the first location is provided and shifted one bit at a time, with each edge of the SCLK. • From then on, we simply provide consecutive bytes of data to be placed in consecutive locations. • During this process SS must Low. • SS=1 to end write cycle.
- 7. Steps for Reading data from SPI device Single byte Read • Make SS=0 to select the device for writing. • 8bit address is shifted in one bit at a time, with each edge of SCLK. A7 =0 for the write operation and the A7 bit goes in first. • After all 8bits of the address are sent in, the SPI device sends out the data belonging to address location immediately. • The 8bit data is shifted out one bit at a time,with each edge of SCLK. • Make SS =0 to indicate the end of read cycle.
- 8. Multi byte burst Read • SS=0 • 8bit address of first location is provided and shifted one bit at a time, each edge of SCLK A7=0 for the write operation and A7 bit goes in first. • The 8bit data for the first location shifted out one bit at a time, with each edge of the SCLK. • From then on, we simply keep getting consecutive bytes of data to be placed in consecutive locations. • During this process SS must Low. • SS=1 to end read cycle.
- 9. REGISTERS The MSSP module has four registers for SPI mode operation. These are: • MSSP Control Register1 (SSPCON1) • MSSP Status Register (SSPSTAT) • Serial Receive/Transmit Buffer (SSPBUF) • MSSP Shift Register (SSPSR) - Not directly accessible
- 12. OPERATION • When initializing the SPI, several options need to be specified. • This is done by programming the appropriate control bits (SSPCON1<5:0>) and SSPSTAT<7:6>. • These control bits allow the following to be specified: – Master mode (SCK is the clock output) – Slave mode (SCK is the clock input) – Clock Polarity (IDLE state of SCK) – Data input sample phase (middle or end of data output time) – Clock edge (output data on rising/falling edge of SCK) – Clock Rate (Master mode only) – Slave Select mode (Slave mode only) • The MSSP consists of a transmit/receive Shift Register (SSPSR) and a buffer register (SSPBUF). • The SSPSR shifts the data in and out of the device, MSb first. • The SSPBUF holds the data that was written to the SSPSR, until the received data is ready. • Once the 8 bits of data have been received, that byte is moved to the SSPBUF register.