SlideShare a Scribd company logo
3
Most read
14
Most read
18
Most read
SPI in ARM7(LPC2148)
By-
Aarav Soni
What is SPI ?
• Serial Peripheral Interface (SPI) is a synchronous serial data protocol used
by microcontrollers for communicating with one or more peripheral
devices quickly over short distances. It can also be used for
communication between two microcontrollers.
• Low power than I2C (no need of Pull ups)
• Supports Single master and multiple slaves
• No hardware slave acknowledgement
• Instrumentation & Communication Unit
• designed by Motorola
• four wire protocol
• Single complete and independent SPI controller.
• Compliant with Serial Peripheral Interface (SPI) specification.
• Synchronous, Serial, Full Duplex Communication.
• Combined SPI master and slave.
• Maximum data bit rate of one eighth of the input clock rate.
• 8 to 16 bits per transfer
• Master In Slave Out (MISO) - The Slave line for sending data to the master,
• Master Out Slave In (MOSI) - The Master line for sending data to the
peripherals,
• Serial Clock (SCK) - The clock pulses which synchronize data transmission
generated by the master, and
• Slave Select pin - the pin on each device that the master can use to enable
and disable specific devices. When a device's Slave Select pin is low, it
communicates with the master. When it's high, it ignores the master .
Spi in arm7(lpc2148)
Spi in arm7(lpc2148)
Spi in arm7(lpc2148)
Spi in arm7(lpc2148)
• The data and clock phase relationships are summarized in Table 197. This
table
• summarizes the following for each setting of CPOL and CPHA.
• When the first data bit is driven
• When all other data bits are driven
• When data is sampled
SPI Register
Read Overrun:
A read overrun occurs when the SPI block internal read buffer contains data that has
not been read by the processor, and a new transfer has completed. The read buffer
containing valid data is indicated by the SPIF bit in the status register being active.
When a transfer completes, the SPI block needs to move the received data to the
read buffer. If the SPIF bit is active (the read buffer is full), the new receive data
will be lost, and the read overrun (ROVR) bit in the status register will be activated.
Write Collision:
As stated previously, there is no write buffer between the SPI block bus interface,
and the internal shift register. As a result, data must not be written to the SPI data
register when a SPI data transfer is currently in progress. The time frame where
data cannot be written to the SPI data register is from when the transfer starts, until
after the status register has been read when the SPIF status is active. If the SPI data
register is written in this time frame, the write data will be lost, and the write
collision (WCOL) bit in the status register will be activated.
Mode Fault:
The SSEL signal must always be inactive when the SPI block is a master.
If the SSEL signal goes active, when the SPI block is a master, this
indicates another master ha selected the device to be a slave. This condition
is known as a mode fault. When a mode fault is detected, the mode fault
(MODF) bit in the status register will be activated, the SPI signal drivers
will be de-activated, and the SPI mode will be changed to be a slave.
Slave Abort
A slave transfer is considered to be aborted, if the SSEL signal goes
inactive before the transfer is complete. In the event of a slave abort, the
transmit and receive data for the transfer that was in progress are lost, and
the slave abort (ABRT) bit in the status register will be activated.
Spi in arm7(lpc2148)
SPI Control Register (S0SPCR)
Spi in arm7(lpc2148)
SPI Status Register (S0SPSR)
Spi in arm7(lpc2148)
SPI Interrupt register (S0SPINT)
/********************************/
Function for initializing SPI
/********************************/
void spi_init()
{
PINSEL0=0X00001505;// Select MOSI, MISO, SCK
S0SPCCR=0X08; // clock is divided by 8
S0SPCR=0X0020; // select as master
}
/********************************/
Function for sending a char
/********************************/
void spi_master(char a)
{
S0SPDR=a;
while(!(S0SPSR & 0X80));
}
/********************************/
Function for receiving a char
/********************************/
char spi_slave(void)
{
while(!(S0SPSR & 0X80));
return S0SPDR;
}
Thanks
For any suggestion,
Please contact me on-
Mail id- a.soniarav@gmail.com
Facebook- https:www.facebook.com/arav.soni.98
Twitter- https://twitter.com/AaravSoni1

More Related Content

PPTX
Serial Peripheral Interface
PDF
SPI Protocol in LPC2148
PPT
Serial Peripheral Interface(SPI)
PPTX
Pic microcontroller architecture
PPTX
Timer counter in arm7(lpc2148)
PPTX
DOCX
ARM7-ARCHITECTURE
PDF
I2C Bus (Inter-Integrated Circuit)
Serial Peripheral Interface
SPI Protocol in LPC2148
Serial Peripheral Interface(SPI)
Pic microcontroller architecture
Timer counter in arm7(lpc2148)
ARM7-ARCHITECTURE
I2C Bus (Inter-Integrated Circuit)

What's hot (20)

PPTX
PPTX
I2C Protocol
ODP
APB protocol v1.0
DOC
8086 class notes-Y.N.M
PPTX
Features of 89c51,pic,avr & arm processors
PDF
Introduction to ARM LPC2148
PPTX
ARM Exception and interrupts
PDF
Lpc2148 i2c
PDF
SPI Protocol
PPSX
Lect 2 ARM processor architecture
PPSX
VLSI Testing Techniques
PPT
SPI Bus Protocol
PPTX
PDF
ARM CORTEX M3 PPT
PDF
Unit II Arm 7 Introduction
PPTX
Introduction about APB Protocol
PPTX
Advance Peripheral Bus
PPTX
SPI introduction(Serial Peripheral Interface)
PPTX
I2c protocol - Inter–Integrated Circuit Communication Protocol
PPT
Axi protocol
I2C Protocol
APB protocol v1.0
8086 class notes-Y.N.M
Features of 89c51,pic,avr & arm processors
Introduction to ARM LPC2148
ARM Exception and interrupts
Lpc2148 i2c
SPI Protocol
Lect 2 ARM processor architecture
VLSI Testing Techniques
SPI Bus Protocol
ARM CORTEX M3 PPT
Unit II Arm 7 Introduction
Introduction about APB Protocol
Advance Peripheral Bus
SPI introduction(Serial Peripheral Interface)
I2c protocol - Inter–Integrated Circuit Communication Protocol
Axi protocol
Ad

Viewers also liked (20)

PPTX
Analog to Digital converter in ARM
PPTX
Pll in lpc2148
PPTX
Serial peripheral interface
PPT
PDF
4 bit lcd_interfacing_with_arm7_primer
PPTX
Serial peripheral Interface - Embedded System Protocol
PPT
ARM7TDM
PDF
ARM 7 LPC 2148 lecture
PPTX
LPC 2148 ARM MICROCONTROLLER
PPTX
Serial communication in LPC2148
PPTX
PPT
PPT
I2C And SPI Part-23
PDF
Serial Peripheral Interface
PPTX
Coin Based Water Flow System Using ARM7(LPC2148) By Nehad
PPTX
MOBILE MONITORNG SYSTEM FOR SMART HOMES
PDF
Entity Relationship diagrams - ER diagrams
PPTX
Cyber crime
PPT
Stellaris® 9000 Family of ARM® Cortex™-M3
PDF
7508 dcf ed01
Analog to Digital converter in ARM
Pll in lpc2148
Serial peripheral interface
4 bit lcd_interfacing_with_arm7_primer
Serial peripheral Interface - Embedded System Protocol
ARM7TDM
ARM 7 LPC 2148 lecture
LPC 2148 ARM MICROCONTROLLER
Serial communication in LPC2148
I2C And SPI Part-23
Serial Peripheral Interface
Coin Based Water Flow System Using ARM7(LPC2148) By Nehad
MOBILE MONITORNG SYSTEM FOR SMART HOMES
Entity Relationship diagrams - ER diagrams
Cyber crime
Stellaris® 9000 Family of ARM® Cortex™-M3
7508 dcf ed01
Ad

Similar to Spi in arm7(lpc2148) (20)

PPTX
LPC2148 SPI (Serial Peripheral Interface).pptx
PPT
Spi (1)
PPTX
Designing of fifo and serial peripheral interface protocol using Verilog HDL
DOCX
D-7-17 Interface an 8-bit serial device using SPI- Thecontrol pin is i.docx
PPTX
Serial Communication - Serial Peripheral Interface
PDF
What's going on with SPI
PDF
AREA OPTIMIZATION OF SPI MODULE USING VERILOG HDL
PPTX
UNI T 6- SPI_I2C_Lecture8.pptx
PPTX
Serial Peripheral Interface (SPI).pptx
PDF
Serial Peripheral Interface Design for Advanced Microcontroller Bus Architect...
PPT
Master synchronous serial port (mssp)
PDF
Welcome to International Journal of Engineering Research and Development (IJERD)
PPTX
APB2SPI.pptx
PPTX
spi-180501092933-converted.pptx
PPT
PPTX
Deepu Kumar Shah.pptx
PDF
International Journal of Computational Engineering Research(IJCER)
PDF
Cd36479483
PPT
10_2Starting with serial_II.ppt
LPC2148 SPI (Serial Peripheral Interface).pptx
Spi (1)
Designing of fifo and serial peripheral interface protocol using Verilog HDL
D-7-17 Interface an 8-bit serial device using SPI- Thecontrol pin is i.docx
Serial Communication - Serial Peripheral Interface
What's going on with SPI
AREA OPTIMIZATION OF SPI MODULE USING VERILOG HDL
UNI T 6- SPI_I2C_Lecture8.pptx
Serial Peripheral Interface (SPI).pptx
Serial Peripheral Interface Design for Advanced Microcontroller Bus Architect...
Master synchronous serial port (mssp)
Welcome to International Journal of Engineering Research and Development (IJERD)
APB2SPI.pptx
spi-180501092933-converted.pptx
Deepu Kumar Shah.pptx
International Journal of Computational Engineering Research(IJCER)
Cd36479483
10_2Starting with serial_II.ppt

Recently uploaded (20)

PPTX
Tartificialntelligence_presentation.pptx
PDF
project resource management chapter-09.pdf
PPTX
cloud_computing_Infrastucture_as_cloud_p
PDF
Hybrid model detection and classification of lung cancer
PDF
Web App vs Mobile App What Should You Build First.pdf
PPTX
TLE Review Electricity (Electricity).pptx
PPTX
MicrosoftCybserSecurityReferenceArchitecture-April-2025.pptx
PDF
2021 HotChips TSMC Packaging Technologies for Chiplets and 3D_0819 publish_pu...
PDF
TrustArc Webinar - Click, Consent, Trust: Winning the Privacy Game
PDF
NewMind AI Weekly Chronicles – August ’25 Week III
PDF
DP Operators-handbook-extract for the Mautical Institute
PDF
STKI Israel Market Study 2025 version august
PDF
WOOl fibre morphology and structure.pdf for textiles
PDF
August Patch Tuesday
PDF
Getting started with AI Agents and Multi-Agent Systems
PPTX
TechTalks-8-2019-Service-Management-ITIL-Refresh-ITIL-4-Framework-Supports-Ou...
PDF
Video forgery: An extensive analysis of inter-and intra-frame manipulation al...
PPTX
Programs and apps: productivity, graphics, security and other tools
PDF
Zenith AI: Advanced Artificial Intelligence
PPTX
Chapter 5: Probability Theory and Statistics
Tartificialntelligence_presentation.pptx
project resource management chapter-09.pdf
cloud_computing_Infrastucture_as_cloud_p
Hybrid model detection and classification of lung cancer
Web App vs Mobile App What Should You Build First.pdf
TLE Review Electricity (Electricity).pptx
MicrosoftCybserSecurityReferenceArchitecture-April-2025.pptx
2021 HotChips TSMC Packaging Technologies for Chiplets and 3D_0819 publish_pu...
TrustArc Webinar - Click, Consent, Trust: Winning the Privacy Game
NewMind AI Weekly Chronicles – August ’25 Week III
DP Operators-handbook-extract for the Mautical Institute
STKI Israel Market Study 2025 version august
WOOl fibre morphology and structure.pdf for textiles
August Patch Tuesday
Getting started with AI Agents and Multi-Agent Systems
TechTalks-8-2019-Service-Management-ITIL-Refresh-ITIL-4-Framework-Supports-Ou...
Video forgery: An extensive analysis of inter-and intra-frame manipulation al...
Programs and apps: productivity, graphics, security and other tools
Zenith AI: Advanced Artificial Intelligence
Chapter 5: Probability Theory and Statistics

Spi in arm7(lpc2148)

  • 2. What is SPI ? • Serial Peripheral Interface (SPI) is a synchronous serial data protocol used by microcontrollers for communicating with one or more peripheral devices quickly over short distances. It can also be used for communication between two microcontrollers. • Low power than I2C (no need of Pull ups) • Supports Single master and multiple slaves • No hardware slave acknowledgement • Instrumentation & Communication Unit • designed by Motorola • four wire protocol
  • 3. • Single complete and independent SPI controller. • Compliant with Serial Peripheral Interface (SPI) specification. • Synchronous, Serial, Full Duplex Communication. • Combined SPI master and slave. • Maximum data bit rate of one eighth of the input clock rate. • 8 to 16 bits per transfer • Master In Slave Out (MISO) - The Slave line for sending data to the master, • Master Out Slave In (MOSI) - The Master line for sending data to the peripherals, • Serial Clock (SCK) - The clock pulses which synchronize data transmission generated by the master, and • Slave Select pin - the pin on each device that the master can use to enable and disable specific devices. When a device's Slave Select pin is low, it communicates with the master. When it's high, it ignores the master .
  • 8. • The data and clock phase relationships are summarized in Table 197. This table • summarizes the following for each setting of CPOL and CPHA. • When the first data bit is driven • When all other data bits are driven • When data is sampled
  • 10. Read Overrun: A read overrun occurs when the SPI block internal read buffer contains data that has not been read by the processor, and a new transfer has completed. The read buffer containing valid data is indicated by the SPIF bit in the status register being active. When a transfer completes, the SPI block needs to move the received data to the read buffer. If the SPIF bit is active (the read buffer is full), the new receive data will be lost, and the read overrun (ROVR) bit in the status register will be activated. Write Collision: As stated previously, there is no write buffer between the SPI block bus interface, and the internal shift register. As a result, data must not be written to the SPI data register when a SPI data transfer is currently in progress. The time frame where data cannot be written to the SPI data register is from when the transfer starts, until after the status register has been read when the SPIF status is active. If the SPI data register is written in this time frame, the write data will be lost, and the write collision (WCOL) bit in the status register will be activated.
  • 11. Mode Fault: The SSEL signal must always be inactive when the SPI block is a master. If the SSEL signal goes active, when the SPI block is a master, this indicates another master ha selected the device to be a slave. This condition is known as a mode fault. When a mode fault is detected, the mode fault (MODF) bit in the status register will be activated, the SPI signal drivers will be de-activated, and the SPI mode will be changed to be a slave. Slave Abort A slave transfer is considered to be aborted, if the SSEL signal goes inactive before the transfer is complete. In the event of a slave abort, the transmit and receive data for the transfer that was in progress are lost, and the slave abort (ABRT) bit in the status register will be activated.
  • 18. /********************************/ Function for initializing SPI /********************************/ void spi_init() { PINSEL0=0X00001505;// Select MOSI, MISO, SCK S0SPCCR=0X08; // clock is divided by 8 S0SPCR=0X0020; // select as master } /********************************/ Function for sending a char /********************************/ void spi_master(char a) { S0SPDR=a; while(!(S0SPSR & 0X80)); }
  • 19. /********************************/ Function for receiving a char /********************************/ char spi_slave(void) { while(!(S0SPSR & 0X80)); return S0SPDR; }
  • 20. Thanks For any suggestion, Please contact me on- Mail id- a.soniarav@gmail.com Facebook- https:www.facebook.com/arav.soni.98 Twitter- https://twitter.com/AaravSoni1