Axi protocol
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The document discusses Advanced eXtensible Interface (AXI), which is a third generation interface specification that is targeted at high performance systems. AXI uses separate address/control and data phases to improve performance. It supports burst transactions where only the start address is issued and multiple outstanding addresses can be in flight simultaneously. AXI consists of five channels to separate read and write operations. Simulation results showed that AXI provides higher throughput than older AMBA interfaces, though older interfaces may have lower latency in some cases. AXI's standardization and flexibility make it useful for integrating IP cores.
Axi protocol
- 2. Advanced extensible Interface (AXI) AXI, the third generation of AMBA interface AMBA 3 specification, is targeted at high performance, high clock frequency system designs and suitable for high speed sub-micrometer interconnect: separate address/control and data phases support for unaligned data transfers using byte strobes burst based transactions with only start address issued & issuing of multiple outstanding addresses easy addition of register stages to provide timing closure.
- 3. How AXI work? AXI consist of five different channels: • Read Address Channel • Write Address Channel • Read Data Channel • Write Data Channel • Write Response Channel
- 4. AXI bus - model
- 7. Channel signaling requirements Channel handshake signals Write address channel Write response channel Read address channel Read data channel
- 8. Transaction channel handshake pairs Transaction channel Handshake pair Write address channel AWVALID, AWREADY Write data channel WVALID, WREADY Write response channel BVALID, BREADY Read address channel ARVALID, ARREADY Read data channel RVALID, RREADY
- 9. Comparing AMBA AHB to AXI Bus- System Modeling AMBA AHB single-channel, shared bus. A 128 bit bus running at 400 MHz. The AHB bus speed was assumed to be double the AXI Bus, and two times the width. AMBA AXI Multi-channel, read/write optimized bus. A 64 bit bus running at 200 Mhz The primary throughput channels- R/W data channels, while the address, response channels are to improve pipelining of multiple requests.
- 10. The simulation study between AMBA AHB and AMBA AXI
- 11. The simulation study between AMBA AHB and AMBA AXI-Results The AHB Bus performed best for the given traffic rates and sizes. The AXI Bus was rated higher for throughput. Bus Type Latency Throughput Power AHB Bus Excellent Good Excellent AXI Bus Good Excellent Good
- 12. Throughput Throughput or network throughput is the average rate of successful message delivery over a communication channel. It is closely related to the channel capacity of the system, and is the maximum possible quantity of data that can be transmitted under ideal circumstances. The throughput is usually measured in bits per second (bit/s or bps), data packets per second or data packets per time slot.
- 13. AXI benefits Faster testbench development and more complete verification of AMBA AXI 3.0/4.0 designs. Easy to use command interface simplifies testbench control and configuration of master and slave. Simplifies results analysis. Runs in every major simulation environment.
- 14. Drawback of AXI The AMBA AXI4 has limitations with respect to the burst data and beats of information to be transferred. The burst must not cross the 4k boundary. Bursts longer than 16 beats are only supported for the INCR burst type. Both WRAP and FIXED burst types remain constrained to a maximum burst length of 16 beats. These are the drawbacks of AMBA AXI system which need to be overcome. T
- 15. AXI features AMBA AXI 3.0/4.0 Verification IP provides an smart way to verify the AMBA AXI 3.0/4.0 component of a SOC or a ASIC. AMBA AXI 3.0/4.0 VIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification environment.
- 16. Summary of AXI Productivity—By standardizing on the AXI interface, developers need to learn only single protocol for IP. Flexibility AXI4 memory mapped interfaces and allows burst of up to 256 data transfer cycles with just a single address phase. AXI4-Stream removes the requirement for an address phase altogether and allows unlimited data burst size.
- 17. Summary of AXI cont... Availability—By moving to an industry-standard, access to a worldwide community of ARM Partners. Many IP providers support the AXI protocol. A robust collection of third-party AXI tool vendors is available that provide a variety of verification, system development, and performance characterization tools.