microcontroller AXI Protocol presentation

AXI Protocol
(Advanced eXtensible
Interface)

Introduction
• It is suitable for high-bandwidth and low-latency designs.
• Provides high-frequency operation without using complex bridges.
• It meets the interface requirements of a wide range of components.
• It provides flexibility in the implementation of interconnect architectures.
• backward-compatible with existing AHB and APB interfaces.
The key features of the AXI protocol are:
• separate address/control and data phases.
• support for unaligned data transfers, using byte strobes.
• uses burst-based transactions with only the start address issued.
• separate read and write data channels, that can provide low-cost Direct Memory Access (DMA)
• support for issuing multiple outstanding addresses.
• support for out-of-order transaction completion.

Cont..
• The AXI protocol is burst-based and defines the following independent transaction channels:
read address channel
read data channel
write address channel
write data channel
write response channel
• An address channel carries control information that describes the nature of the data to be
transferred. The data is transferred between master and slave.
• In a write transaction, the slave uses the write response channel to signal the completion of
the transfer to the master.

AXI Interface and Interconnect
• AXI interface is a point to point interface.
• One master and one slave, these two communicate with an AXI
Interface.

AXI Interconnect
Master2
Master3
Slave1
Slave2
Slave3
Slave4
Slave5
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C
T
Master1

AXI Interface Signals
• Global Signals
Signal Source Description
ACLK Clock source Global clock signal.
ARESETn Reset source Global reset signal, active LOW.

Write address channel signals
AWID[3:0] Master Write address ID. This signal is the identification tag for the write address group of signals.
AWADDR[31:0] Master Write address. The write address gives the address of the first transfer in a write burst transaction
AWLEN[3:0] Master Burst length. The burst length gives the exact number of transfers in a burst.
AWSIZE[2:0] Master Burst size. This signal indicates the size of each transfer in the burst.
AWBURST[1:0] Master Burst type. The burst type and the size information, determine how the address for each transfer within the burst is
calculated.
AWLOCK[1:0] Master Lock type. Provides additional information about the atomic characteristics of the transfer.
AWCACHE[3:0] Master Memory type. This signal indicates how transactions are required to progress through a system.
AWPROT[2:0] Master Protection type. This signal indicates the privilege and security level of the transaction, and whether the transaction
is a data access or an instruction access.
AWQOS Master Quality of Service, QoS. The QoS identifier sent for each write transaction. Implemented only in AXI4.
AWREGION Master Region identifier. Permits a single physical interface on a slave to be used for multiple logical interfaces.
AWUSER Master User signal. Optional User-defined signal in the write address channel. Supported only in AXI4.
AWVALID Master Write address valid. This signal indicates that the channel is signaling valid write address and control information.
AWREADY Slave Write address ready. This signal indicates that the slave is ready to accept an address and associated control signals.

Write data channel signals
WID[3:0] Master Write ID tag. This signal is the ID tag of the write data transfer. Supported only in AXI3.
WDATA[31:0] Master Write data. The write data bus can be 8, 16, 32, 64, 128, 256, 512, or 1024 bits wide.
WSTRB[3:0] Master Write strobes. This signal indicates which byte lanes hold valid data. There is one write
strobe bit for each eight bits of the write data bus.
WLAST Master Write last. This signal indicates the last transfer in a write burst.
WUSER Master User signal. Optional User-defined signal in the write data channel.
WVALID Master Write valid. This signal indicates that valid write data and strobes are available.
WREADY Slave Write ready. This signal indicates that the slave can accept the write data.

Write response channel signals
BID[3:0] Slave Response ID tag. This signal is the ID tag of the write response
BRESP[1:0] Slave Write response. This signal indicates the status of the write transaction.
The allowable responses are OKAY, EXOKAY, SLVERR, and DECERR.
BUSER Slave
User signal. Optional User-defined signal in the write response channel.
Supported only in AXI4
BVALID Slave
Write response valid. This signal indicates that the channel is signaling a valid
write response.
BREADY Master
Response ready. This signal indicates that the master can accept a write
response.

Read address channel signals
ARID[3:0] Master Read address ID. This signal is the identification tag for the read address group of signals.
ARADDR[31:0] Master Read address. The Read address gives the address of the first transfer in a read burst transaction
ARLEN[3:0] Master Burst length. The burst length gives the exact number of transfers in a burst.
ARSIZE[2:0] Master Burst size. This signal indicates the size of each transfer in the burst.
ARBURST[1:0] Master Burst type. The burst type and the size information, determine how the address for each transfer within the burst is
calculated.
ARLOCK[1:0] Master Lock type. Provides additional information about the atomic characteristics of the transfer.
ARCACHE[3:0] Master Memory type. This signal indicates how transactions are required to progress through a system.
ARPROT[2:0] Master Protection type. This signal indicates the privilege and security level of the transaction, and whether the transaction
is a data access or an instruction access.
ARQOS Master Quality of Service, QoS. The QoS identifier sent for each Read transaction. Implemented only in AXI4.
ARREGION Master Region identifier. Permits a single physical interface on a slave to be used for multiple logical interfaces.
ARUSER Master User signal. Optional User-defined signal in the Read address channel. Supported only in AXI4.
ARVALID Master Read address valid. This signal indicates that the channel is signaling valid read address and control information.
ARREADY Slave Read address ready. This signal indicates that the slave is ready to accept an address and associated control signals.

Read data channel signals
RID[3:0] Slave Read ID tag. This signal is the ID tag of the read data transfer. Supported only in AXI3.
RDATA[31:0] Slave Read data
RRESP[1:0] Slave Read response. This signal indicates the status of the read transfer.
RLAST Slave Read last. This signal indicates the last transfer in a read burst.
RUSER Slave User signal. Optional User-defined signal in the read data channel.
RVALID Slave Read valid. This signal indicates that the channel is signaling the required read data.
RREADY Master
Read ready. This signal indicates that the master can accept the read data and response
information.

Write channels in AXI
• Write address
• Write data
• Write response

Cont..
• Write data can be interleaved, but not out of order.
• Write response can be out of order.

Read channels in AXI
• The data bus can be up to 1024 bits wide
• Read address
• Read data

Read channel ordering
• Read data can be interleaved

Cont..
• Read data can be interleaving or out of order

• Out-of-order transactions can improve system performance in two ways:
• The interconnect can enable transactions with fast-responding slaves to complete
in advance of earlier transactions with slower slaves.
• Complex slaves can return read data out of order. For example, a data item for a
later access might be available from an internal buffer before the data for an
earlier access is available.
• Although complex devices can make use of the out-of-order facility, simple
devices are not required to use it. Simple masters can issue every transaction
with the same ID tag, and simple slaves can respond to every transaction in order,
irrespective of the ID tag.

VALID – READY handshake mechanism
• All the 5 channels have VALID-READY handshake mechanisms.
• Any channel’s signals are valid only
when that channels VALID is
asserted.

Transaction Attributes
• Burst Length
- ARLEN, AWLEN Signals
- Actual number of beats is AxLEN + 1
• Burst Size
- ARSIZE, AWSIZE Signals
- Actual number of bytes transferred in a beat is 2^AxSIZE

Cont..
• Burst Type
- ARBURST, AWBURST Signals
1) FIXED: Memory access to same address.
- It is only used for FIFO type memory.
2) INCR: Normal memory access
Transaction addr = 0x04, AxSIZE = 4bytes, Burst type = INCR, AxLEN =1
08 04 00
1st
beat
2nd
beat
(FIXED)
Addr = 0
DBW = 4bytes
Size 4bytes
Len =3, 3+1 =4 beats
B1 3 2 1 0
B2 3 2 1 0
B3 3 2 1 0
B4 3 2 1 0

Cont..
3) WRAP: Address wraps to lower boundary or reaching a maximum
address.
Note:: Wrap burst restrictions
- The start address must aligned to the size of each transfer.
- The length of WRAP burst must be 2,4,8,16 transfers.
Transaction addr = 0x04, AxSIZE = 4bytes, Burst type = WRAP, AxLEN =1
08 04 00
1st
beat 2nd
beat

Cont..
• Bus address:
- AWADDR, ARADDR Signals
- The address to which transaction sent.
• Memory attribute signaling:
- ARCACHE, AWCACHE Signals
- Bufferable, Cacheable, Allocate attributes of the transaction
• Protection type:
- ARPROT, AWPROT Signals
- Provides access permissions
• Write data strobes:
- WSTRB Signal
- De-asserted for all invalid lanes
Start addr = 0x03
Len = 4beats
INCR
DWB 64bits(8bytes)
Size 4bytes
B1 7 6 5 4 3 2 1 0
1 0 0 0
B2 7 6 5 4 3 2 1 0
1 1 1 1
B3 F E D C B A 9 8
1 1 1 1
B4 F E D C B A 9 8
1 1 1 1

Cache Support
• Support for system level caches and other performance enhancing
components.
- Bufferable (B) bit, ARCACHE [0] and AWCACHE [0]
- Cacheable (C) bit, ARCACHE [1] and AWCACHE [1]
- Read Allocate (RA) bit, ARCACHE [2] and AWCACHE [2]
- Write Allocate (WA) bit, ARCACHE [3] and AWCACHE [3]
AxCACHE [0] 0 Non-bufferable
1 Bufferable
AxCACHE [2] 0 No Read-allocate
1 Read allocate
AxCACHE [1] 0 Non-cacheable
1 Cacheable
AxCACHE [3] 0 No Write-allocate
1 Write allocate

Bufferable bit
• When the bit is asserted, the interconnect or component can delay
the transaction reaching it’s final destination for any no. of cycles.
• Normally, bufferable attribute is only relevant to writes.
Master1
Master2
Slave1
AXI
Interconnect
A1 A2 A3
B1 B2 B3
A1 B1 A2 B2 A3 B3

Cont..
• If bufferable, it is acceptable for a bridge or system level cache to
provide write response.
• If non-bufferable, final destination to provide response.
Master1
Master2
Slave1
AXI
Interconnect
Bufferable
Non-bufferable

Protection unit
• To support complex system design, for the interconnect and other
devices in the system to provide protection against illegal
transactions.
- Normal or Privileged, ARPROT [0] and AWPROT [0]
LOW HIGH
- Secure or Non-Secure, ARPROT [1] and AWPROT [1]
LOW HIGH
- Data or Instruction, ARPROT [2] and AWPROT [2]
LOW HIGH

Normal/Privileged
• This is used by some masters to indicate their processing mode.
Master1
Master2
Slave1
AXI
Interconnect
Normal
access
Privileged
access
Slave2

Secure/Non-Secure
• This is used in system when a greater degree of differentiation
between processing modes is required.
Master1
Slave1
(Secure)
AXI
Interconnect
Slave2
(Non-
Secure)
Slave3
(Non-
Secure)
Non-Secure
Secure

LOCK Transfers
• Used when an AXI master require special access for bus, it will run a
lock transfer and no other master should interfere in between.
• Start a locked write or read.
• Finish by issuing an unlocked read or write. (it removes lock)
AxLock[1:0] Access Type
00 Normal Access
01 Exclusive Access
10 Locked Access
11 Reserved
AXI3 Atomic Access Signaling
AxLock Access Type
0 Normal Access
1 Exclusive Access
AXI4 Atomic Access Signaling

Exclusive Transaction
• Read-modify-write kind of transaction.
- Issue an exclusive read txn to some
address
- Monitor the address exclusively.
- Issue matching exclusive write txn
to address.
Addr 00
D1 = 11110
D2 = 00101
D3= 11110^00101
D1^D2 = D3
Write D3 to addr 00

Cont..
- Exclusive fail/pass
If address updated by other master.
It respond with OKAY. (error)
- Exclusive fail/pass
If address not updated by other master.
It responds with EXOKAY (no error)

AXI Responses
• BRESP [1:0]/RRESP [1:0]
write read
- OKAY, normal access successes
Success of a normal access
Failure of an exclusive access
An exclusive access to a slave that does not support exclusive
- EXOKAY, exclusive access successes
Success of an exclusive access

Cont..
- SLVERR, slave error
FIFO or buffer overflow, underflow condition
Unsupported transfer size attempt
- DECERR, decode error
Returns DECERR in case interconnect cannot successfully decode a
slave access.

AXI4 – Difference with AXI3
• AWLEN/ARLEN now 8 bits wide to support INCR bursts of up to 256 data
beats.
• In WRAP, it’s still supports 2,4,8,16.
• AWLOCK/ARLOCK “locked” transfer is dropped.
• No WID signal and interleaving of write data transfers no longer
supported.
• Additional handshake rule describing that write response can only be
returned after both the address and data channel transfers have
completed.
• New AxQoS, AxREGION and AxUSER signals are added.

AXI4 Lite – Difference with AXI4
• No burst supported.
- Here all the write and read transactions in order.
• All transactions are burst length of 1.
• All data accesses are the same size as the width of the data bus.
• Support for data bus width of 32 or 64 bits.
• Exclusive accesses are not supported.
• AXI4 lite does not support AXI IDs. All transactions must be in order.

010 (2bytes) [start addr must be equal to size of each transfer in aligned]
0000 0010 0100 0110 1000 1010 1100 1110 (aligned transfers)
0 2 4 6 8 A C E
0001 0011 0101 0111 1001 1011 1101 1111 (unaligned transfer)
1 3 5 7 9 B D F
100 (4bytes)
0000 0100 1000 1100 (aligned transfers)
0 4 8 C
(unaligned transfer)
0001 0010 0011 0101 0110 0111 1001 1010 1011 1101 1110 1111
1 2 3 5 6 7 9 A B D E F

• AXI unaligned transfers
Addr 0x07 1 0 0 0
Size = 4bytes 0x07 0x06 0x05 0x04 b1
Incr 0xb 0xa 0x9 0x8 b2
Len = 4beats 0xf 0xe 0xd 0xc b3
0x13 0x12 0x11 0x10 b4
100 0x07
0 4 8 c 10 14 18 1c
0111

• Size 4bytes, start addr =0x00, INCR, DBW 64bit
07 06 05 04 03 02 01 00 b1
07 06 05 04 03 02 01 00 b2
F E D C B A 9 8 b3
F E D C B A 9 8 b4
• Size 4bytes, start addr =0x04, WRAP, Len = 4, DBW 64bit
07 06 05 04 03 02 01 00 b1
F E D C B A 9 8 b2
F E D C B A 9 8 b3
07 06 05 04 03 02 01 00 b4
Valid

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