Presentation on 8086 Microprocessor
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The document provides information on the 8086 microprocessor, including: - It was designed by Intel in the late 1970s and was used in early PCs. - It has a 16-bit architecture and 20-bit address bus, allowing access to 1MB of memory. - The 8086 CPU logic is partitioned into a Bus Interface Unit and Execution Unit, with the BIU handling bus operations and the EU executing instructions. - The BIU generates physical addresses from logical addresses using segment registers and the instruction pointer. It also contains an instruction queue and registers. - The EU contains general purpose registers, flags, and an ALU for arithmetic and logical operations.
![20-bit physical address
1.Programmer-provided logical address(16-bit contents of CS and IP) by
logically shifting the contents of CS four bits to left and then adding the
16-bit contents of IP.
2.For example, if [CS] = (456A)16 and [IP] = (1620)16, then the 20-bit
physical address is generated by the BIU as follows:
Four times logically shifted [CS] to left = (456A0) 16
+ [IP] as offset = (1620)16
20-bit physical address = (46CC0)16](https://image.slidesharecdn.com/presentationon8086-161129170652/85/Presentation-on-8086-Microprocessor-8-320.jpg)
Presentation on 8086 Microprocessor
- 1. Presentation On 8086 MICROPROCESSOR ARCHITECTURE Group Name: Bug Free Group Members:
- 2. History of 8086 microprocessor • The 8086 is a 16-bit microprocessor chip designed by Intel between early 1976 and mid-1978. • The Intel 8088, released in 1979. • The processor used in the original IBM PC. • The 8086 gave rise to the x86 architecture which eventually became Intel's most successful processors.
- 3. Features of Intel – 8086 microprocessor • It is a 16-bit microprocessor. • 8086 has a 20 bit address bus can access up to 220 memory locations (1 MB). • It can support up to 64K I/O ports. • It provides 16 -bit registers • It has multiplexed address and data bus AD0- AD15 and A16 – A19.
- 4. Features of Intel – 8086 microprocessor •8086 is designed to operate in two modes --- Minimum and Maximum •A 40 pin dual in line package •Address ranges from 00000H to FFFFFH •It requires +5V power supply.
- 5. Internal Architecture of 8086 • The 8086 CPU logic has been partitioned into two functional units namely Bus Interface Unit (BIU) and Execution Unit (EU)
- 6. Internal Architecture of 8086 • The BIU performs all bus operations such as instruction fetching, reading and writing operands for memory and calculating the addresses of the memory • EU executes instructions from the instruction system byte queue • The BIU contains a dedicated adder, which is used to produce the 20-bit address.
- 7. Internal Architecture of 8086 The BIU handles all transactions of data and addresses on the buses for EU The major reason for this separation is to increase the processing speed of the processor
- 8. 20-bit physical address 1.Programmer-provided logical address(16-bit contents of CS and IP) by logically shifting the contents of CS four bits to left and then adding the 16-bit contents of IP. 2.For example, if [CS] = (456A)16 and [IP] = (1620)16, then the 20-bit physical address is generated by the BIU as follows: Four times logically shifted [CS] to left = (456A0) 16 + [IP] as offset = (1620)16 20-bit physical address = (46CC0)16
- 9. 9 20-bit physical address Physical Address (20 Bits) Adder Segment Register (16 bits) 0 0 0 0 Offset Value (16 bits) Physical address= segment x 1Oh+ offset
- 10. Bus Interface Unit • The BIU has • Instruction stream byte queue • A set of segment registers • Instruction pointer
- 11. BIU – Instruction Byte Queue • 8086 instructions vary from 1 to 6 bytes • Therefore fetch and execution are taking place concurrently in order to improve the performance of the microprocessor • The BIU feeds the instruction stream to the execution unit through a 6 byte prefetch queue
- 12. Segment Registers • CS - points at the segment containing the current program. • DS - generally points at segment where variables are defined. • ES - extra segment register, it's up to a coder to define its usage. • SS - points at the segment containing the stack.
- 13. Instruction pointer • IP - the instruction pointer: 1. Always points to next instruction to be executed 2. Offset address relative to CS • IP register always works together with CS segment register and it points to currently executing instruction.
- 14. Execution Unit • General registers • Arithmetic and Logical Unit (ALU) • Flag register
- 16. General registers SI - source index register: 1. Can be used for pointer addressing of data 2. Used as source in some string processing instructions DI - destination index register: 1. Can be used for pointer addressing of data 2. Used as destination in some string processing instructions BP - base pointer: 1. Primarily used to access parameters passed via the stack 2. Offset address relative to SS SP - stack pointer: 1. Always points to top item on the stack 2. Offset address relative to SS
- 17. Flag register
- 18. Arithmetic and Logical Unit • An arithmetic logic unit (ALU) represents the fundamental building block of the central processing unit of a computer. An ALU is a digital circuit used to perform arithmetic and logic operations.
Editor's Notes
- #10: 9