8086 architecture and pin description
- 1. 8086 Microprocessor D. ASWINI ASSISTANT PROFESSOR
- 2. What is Microprocessor? A microprocessor is a multipurpose, programmable, clock-driven, register- based electronic device. Reads binary instructions from a storage device called memory Accepts binary data as input and processes data according to those instructions and provide results as output Microprocessor is a single IC package in which a number of useful functions are integrated and fabricated on a single silicon semiconductor chip
- 3. Introduction 8086 is a 16-bit μp. 8086 has a 20 bit address bus can access up to 220 memory locations (1 MB). Address ranges from 00000H to FFFFFH 3
- 4. introduction Memory is byte addressable - Every byte has a separate address. It has 16 bit Databus. Word size is 16 bits. It has multiplexed address and data bus AD0- AD15 and A16 – A19. 8086 is designed to operate in two modes, Minimum and Maximum. It can prefetch up to 6 instruction bytes from memory and queues them in order to speed up instruction execution. It requires +5V power supply. A 40 pin dual in line package. 4
- 7. Internal architecture of 8086 8086 has two blocks BIU and EU. The BIU handles all transactions of data and addresses on the buses for EU. BIU performs all bus operations such as instruction fetching, reading and writing operands for memory and calculating addresses of the memory operands. The instruction bytes are transferred to the instruction queue. EU executes instructions from the instruction system byte queue. Both units operate asynchronously to give the 8086 an overlapping instruction fetch and execution mechanism which is called as Pipelining. This results in efficient use of the system bus and system performance. BIU contains Instruction queue, Segment registers, Instruction pointer, Address adder. EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register, Flag register. 7
- 8. BUS INTERFACE UNIT (BIU) Contains 6-byte Instruction Queue (Q) The Segment Registers (CS, DS, ES, SS). The Instruction Pointer (IP) The Address Summing block (Σ) – To generate 20 bit address 8
- 9. Instruction Queue The BIU uses a mechanism known as an instruction stream queue to implement a pipeline architecture. This queue permits pre-fetch of up to 6 bytes of instruction code. BIU is free to look ahead in the program by pre-fetching the next sequential instruction. These pre-fetching instructions are held in its FIFO queue. With its 16 bit data bus, the BIU fetches two instruction bytes in a single memory cycle. The EU accesses the queue from the output end. It reads one instruction byte after the other from the output of the queue. 9
- 10. Pipelining
- 11. Memory Segmentation Code segment (64KB) Data segment (64KB) Extra segment (64KB) Stack segment (64KB) 1MB The memory in an 8086/88 based system is organized as segmented memory. 8086 addresses 1MB of memory The physical memory may be divided into logical segments. The 4 segments are Code, Data, Extra and Stack The size of each segment is 64 KB • A segment begins at a location which is divisible by 16(10H) Each of these segments can be used for a specific function. • Code segment is used for storing the instructions. • stack segment is used as a stack and used to store the return address. • Data and extra segments are used for storing data bytes. • In the assembly language programming, more than one data/ code/ stack segments can be defined. But only one segment of each type can be accessed at any time. 00000 FFFFF Physical Memory
- 12. The 16 bit contents of the segment registers in the BIU actually point to the starting location of a particular segment. Segments may be overlapped or non-overlapped
- 13. Advantages of Segmented memory Scheme Allows the memory capacity to be 1Mb although the actual addresses are of 16 bit size. Allows the placing of code, data and stack portions of the same program in different parts (segments) of the m/y, for data and code protection. Permits a program / data to be put into different areas of memory each time program is executed, i.e. provision for relocation may be done . segment registers are used to allow the instruction, data or stack portion of a program to be more than 64Kb long by using more than one code, data or stack segments. 13
- 14. 34BA 44EB 54EB 695E 14 CSR DSR ESR SSR Segment Registers BIU CODE (64k) DATA (64K) EXTRA (64K) STACK (64K) 1MB 00000 34BA0 44B9F 44EB0 54EAF 54EB0 64EAF 695E0 795DF Each segment register store the upper 16 bit of the starting address of the segments MEMORY
- 15. Instruction pointer & summing block Instruction pointer register contains a 16-bit offset address of instruction that is to be executed next. IP always references the Code segment register (CS). The value contained in the IP is called as an offset as this value must be added to the base address of the code segment to find the 20-bit physical address. IP is incremented after executing every instruction. To form a 20bit address of the next instruction, the 16 bit address of the IP is added (by the address summing block) to the address contained in the CS , which has been shifted four bits to the left. 15
- 17. Example For Address Calculation (segment: offset) If the data segment starts at location 1000h and a data reference contains the address 29h where is the actual data? 17 Required Address Offset Segment Address 0000 0000 0010 1001 0000 0001 0000 0000 0010 1001 0001 0000 0000 0000
- 18. Segment and Address register combination CS:IP SS:SPSS:BP DS:BX DS:SI DS:DI (for other than string operations) ES:DI (for string operations) 18
- 19. EXECUTION UNIT Decodes instructions fetched by the BIU Generate control signals, Executes instructions. The main parts are: Control Circuitry Instruction decoder ALU 19
- 20. EXECUTION UNIT – General Purpose Registers AH AL BH BL CH CL DH DL SP BP SI DI 20 8 bits 8 bits 16 bits Accumulator Base Count Data Stack Pointer Base Pointer Source Index Destination Index AX BX CX DX Pointer Index 8 bits 8 bits 16 bits Accumulator Base Count Data Stack Pointer Base Pointer Source Index Destination Index
- 21. Pointer And Index Registers used to keep offset addresses. Used in various forms of memory addressing. In the case of SP and BP the default reference to form a physical address is the Stack Segment. The index registers (SI & DI) and the BX generally default to the Data segment register (DS). 21
- 22. SP: Stack pointer – Used with SS to access the stack segment BP: Base Pointer – Primarily used to access data on the stack – Can be used to access data in other segments SI: Source Index register – is required for some string operations –SI is associated with the data segment (DS) reg. in string operations. DI: Destination Index register – is also required for some string operations. – DI is associated with ES register in string operations. The SI and the DI registers may also be used to access data stored in arrays. 22
- 23. Control Circuit Instruction Register and Instruction Decoder: (Present inside the Control Unit) The EU fetches an opcode from the queue into the instruction register. The instruction decoder decodes it and sends the information to the control circuit for execution.
- 24. Flag Register
- 25. Memory banking
- 26. Features of 8086 It has an instruction queue, which is capable of storing six instruction bytes from the memory resulting in faster processing. It was the first 16-bit processor having 16-bit ALU, 16-bit registers, internal data bus, and 16-bit external data bus resulting in faster processing. It is available in 3 versions based on the frequency of operation − 8086 → 5MHz 8086-2 → 8MHz 8086-1 → 10 MHz It uses two stages of pipelining, i.e. Fetch Stage and Execute Stage, which improves performance. Fetch stage can prefetch up to 6 bytes of instructions and stores them in the queue. Execute stage executes these instructions. It has 256 vectored interrupts.
- 27. 8086 Pin Details
- 29. PIN Details Intel 8086 is a 16-bit HMOS microprocessor. It is available in 40 pin DIP chip It uses a 5V DC supply for its operation The 8086 uses 20-line address bus It has a 16-line data bus. The 20 lines of the address bus operate in multiplexed mode The 16-low order address bus lines have been multiplexed with data and 4 high-order address bus lines have been multiplexed with status signals.
- 30. PIN Details AD0-AD15 : Address/Data bus. These are low order address bus. They are multiplexed with data. When AD lines are used to transmit memory address the symbol A is used instead of AD, for example A0-A15. When data are transmitted over AD lines the symbol D is used in place of AD, for example D0-D7, D8-D15 or D0-D15. A16-A19 : High order address bus. These are multiplexed with status signals.
- 31. PIN DIAGRAM A16/S3, A17/S4, A18/S5, A19/S6 : The specified address lines are multiplexed with corresponding status signals.
- 33. Pin details
- 34. Pin details