Ms 2443 final

Technical Article
MS-2443
.
www.analog.com
Page 1 of 10 ©2013 Analog Devices, Inc. All rights reserved.
Safeguard Your RS-485
Communication Networks
from Harmful EMC Events
by James Scanlon, Senior Evaluation Engineer, Analog
Devices, Inc., and Koenraad Rutgers, Senior Field
Applications Engineer, Bourns, Inc.
IDEA IN BRIEF
In real industrial and instrumentation (I&I) applications,
RS-485 interface links must work in harsh electromagnetic
environments. Large transient voltages caused by lightning
strikes, electrostatic discharge, and other electromagnetic
phenomenon can damage communications ports. To ensure
that these data ports can survive in their final installation
environments, they must meet certain electromagnetic
compatibility (EMC) regulations.
These requirements include three main transient immunity
standards: electrostatic discharge, electrical fast transients,
and surge.
Many EMC problems are not simple or obvious, so they must
be considered at the start of the product design. Leaving
these considerations to the end of the design cycle can lead
to overruns in engineering budget and schedule.
This article describes each of these main transient types and
presents and demonstrates three different EMC compliant
solutions for three different cost/protection levels on RS-485
communication ports.
Analog Devices, Inc., and Bourns, Inc., have partnered
to extend their offering of system oriented solutions by
co-developing the industry’s first EMC compliant RS-485
interface design tool that provides up to Level 4 protection
levels for IEC61000-4-2 ESD, IEC61000-4-4 EFT, and
IEC61000-4-5 surge. It gives designers the design options
depending on the level of protection required and available
budgets. These design tools allow designers to reduce risk of
project slippage due to EMC problems by considering them
at the start of the design cycle.
RS-485 STANDARD
I&I applications require data transmission between multiple
systems, often over very long distances. The RS-485 electrical
standard is one of the most widely used physical layer
specifications in I&I applications, such as industrial
automation, process control, motor control, and motion
control; remote terminals; building automation, such as
heating, ventilation, and air conditioning (HVAC); security
systems; renewable energy.
Some of the key features of the RS-485 that make it ideal for
use in I&I communications applications are:
• Long distance links—up to 4000 feet
• Bidirectional communications possible over a single
pair of twisted cables
• Differential transmission increases common-mode
noise immunity and decreases noise emissions
• Multiple drivers and receivers can be connected on the
same bus
• Wide common-mode range (–7 V to +12 V) allows for
differences in ground potential between the driver and
receiver
• TIA/EIA-485-A allows for data rates of up to 10’s
of Mbps
TIA/EIA-485-A describes the physical layer of the RS-485
interface and is normally used with a higher-level protocol,
such as Profibus, Interbus, Modbus, or BACnet. This allows
for robust data transmission over relatively long distances.
In real applications, however, lightning strikes, power
induction and direct contact, power source fluctuations,
inductive switching, and electrostatic discharge can damage
RS-485 transceivers by generating large transient voltages.
Designers must ensure that equipment does not only work
under ideal conditions but that it will also work in the “real
world”. To ensure that these designs can survive in electrically
harsh environments, various government agencies and
regulatory bodies have imposed EMC regulations. Compliance
with these regulations gives the end user assurance that
designs will operate as desired in these harsh environments.

MS-2443 Technical Article
Page 2 of 10
ELECTROMAGNETIC COMPATIBILITY
An electromagnetic environment is composed of both
radiated and conducted energy, so EMC has two aspects:
emission and susceptibility. Thus, EMC has the ability of an
electronic system to function satisfactorily in its intended
electromagnetic environment without introducing intolerable
electromagnetic disturbances to that environment. This
article deals with increasing the protection level for EMC
susceptibility of RS-485 ports against the three main EMC
transients.
The International Electrotechnical Commission (IEC) is
the world’s leading organization that prepares and publishes
international standards for all electrical, electronic, and
related technologies. Since 1996, all electronic equipment
sold to or within the European Community must meet EMC
levels as defined in specifications IEC61000-4-x.
The IEC61000 specifications define the set of EMC immunity
requirements that apply to electrical and electronic equipment
intended for use in residential, commercial, and light industrial
environments. This set of specifications includes three types
of high voltage transients that electronic designers need to
be concerned about for the data communication lines:
• IEC 61000-4-2 electrostatic discharge (ESD)
• IEC 61000-4-4 electrical fast transients (EFT)
• IEC 61000-4-5 surge immunity
Each of these specifications defines a test method to assess
the immunity of electronic and electrical equipment against
the defined phenomenon. The following sections summarize
each of these tests.
ELECTROSTATIC DISCHARGE
ESD is the sudden transfer of electrostatic charge between
bodies at different potentials caused by near contact or
induced by an electric field. It has the characteristics of high
current in a short time period. The primary purpose of the
IEC61000-4-2 test is to determine the immunity of systems
to external ESD events outside the system during operation.
IEC61000-4-2 describes testing using two coupling methods.
These are known as contact discharge and air-gap discharge.
Contact discharge implies a direct contact between the
discharge gun and the unit under test. During air discharge
testing, the charged electrode of the discharge gun is moved
toward the unit under test until a discharge occurs as an arc
across the air gap. The discharge gun does not make direct
contact with the unit under test. A number of factors affect
the results and repeatability of the air discharge test, including
humidity, temperature, barometric pressure, distance, and
rate of approach to the unit under test. This method is a
better representation of an actual ESD event but is not as
repeatable. Therefore, contact discharge is the preferred test
method.
During testing, the data port is subjected to at least 10 positive
and 10 negative single discharges with a one second interval
between each pulse. Selection of the test voltage is dependent
on the system end environment. The highest specified test is
Level 4, which defines a contact discharge voltage of ±8 kV
and an air discharge voltage of ±15 kV.
Figure 1 shows the 8 kV contact discharge current waveform
as described in the specification. Some of the key waveform
parameters are rise times of less than 1 ns and pulse widths
of approximately 60 ns. This equates to a pulse with a total
energy in the range of 10's of mJ.
Figure 1. IEC61000-4-2 ESD Waveform (8 kV)
ELECTRICAL FAST TRANSIENTS
Electrical fast transient testing involves coupling a number
of extremely fast transient impulses onto the signal lines to
represent transient disturbances associated with external
switching circuits that are capacitively coupled onto the
communication ports, which may include relay and switch
contact bounce or transients originating from the switching
of inductive or capacitive loads—all of which are very
common in industrial environments. The EFT test defined
in IEC61000-4-4 attempts to simulate the interference
resulting from these types of events.
Figure 2 shows the EFT 50 Ω load waveform. The EFT
waveform is described in terms of a voltage across 50 Ω
impedance from a generator with 50 Ω output impedance.
The output waveform consists of a 15 ms burst of 2.5 kHz
to 5 kHz high voltage transients repeated at 300 ms intervals.
Each individual pulse has a rise time of 5 ns and pulse duration
of 50 ns, measured between the 50% point on the rising and
falling edges of the waveform. The total energy in a single
EFT pulse is similar to that in an ESD pulse. The total energy
in a single pulse is typically 4 mJ. Voltages applied to the data
ports can be as high as 2 kV.

Technical Article MS-2443
Page 3 of 10
Figure 2. IEC61000-4-4 EFT 50 Ω Load Waveforms
These fast burst transients are coupled onto the communication
lines using a capacitive clamp. The EFT is capacitively
coupled onto the communication lines by the clamp rather
than direct contact. This also reduces the loading caused by
the low output impedance of the EFT generator. The coupling
capacitance between the clamp and cable depends on cable
diameter, shielding, and insulation on the cable.
SURGE TRANSIENTS
Surge transients are caused by overvoltage from switching
or lightning transients. Switching transients can result from
power system switching, load changes in power distribution
systems or various system faults such as short circuits.
Lightning transients can be a result of high currents and
voltages injected into the circuit from nearby lightning
strikes. IEC61000-4-5 defines waveforms, test methods, and
test levels for evaluating immunity against these destructive
surges.
The waveforms are specified as the outputs of a waveform
generator in terms of open circuit voltage and short circuit
current. Two waveforms are described. The 10/700 µs
combination waveform is used to test ports intended for
connection to symmetrical communication lines: for
example, telephone exchange lines. The 1.2/50 µs combination
waveform generator is used in all other cases, in particular
short distance signal connections. For RS-485 ports, the
1.2/50 µs waveform is predominantly used and will be
discussed in this section. The waveform generator has an
effective output impedance of 2 Ω; hence, the surge transient
has high currents associated with it.

Page 4 of 10
Figure 3 shows the 1.2/50 µs surge transient waveform. ESD
and EFT have similar rise times, pulse widths, and energy
levels; however, the surge pulse has a rise time of 1.25 µs and
the pulse width is 50 µs. Additionally, the surge pulse energy
can reach up to almost 90 J, which is three to four orders of
magnitude larger than the energy in an ESD or EFT pulse.
Therefore, the surge transient is considered the most severe
of the EMC transients. Due to the similarities between ESD and
EFT, the design of the circuit protection can be similar, but
due to its high energy, surge must be dealt with differently.
This is one of the main issues in developing protection that
improves the immunity of data ports to all three transients
while remaining cost effective.
Resistors couple the surge transient onto the communication
line. Figure 4 shows the coupling network for a half-duplex
RS-485 device. The total parallel sum of the resistance is 40 Ω.
For the half-duplex device, each resistor is 80 Ω.
During the surge test, five positive and five negative pulses
are applied to the data ports with a maximum time interval
of one minute between each pulse. The standard states that
the device should be set up in normal operating conditions
for the duration of the test.
Figure 3. IEC61000-4-5 Surge 1.2/50 µs Waveform
Figure 4. Coupling/Decoupling Network for a Half-Duplex RS-485 Device

Page 5 of 10
PASS/FAIL CRITERIA
When transients are applied to the system under test, the
results are categorized into four pass/fail criteria. Following
is a list of the pass/fail criteria giving examples of how each
one might relate to an RS-485 transceiver:
• Normal performance; no bit errors would occur during
or after the transient is applied
• Temporary loss of function or temporary degradation
of performance not requiring an operator; bit errors
might occur during and for a limited time after the
transient is applied
• Temporary loss of function or temporary degradation
of performance requiring an operator; a latch up event
may occur that could be removed after a power on reset
with no permanent or degradation to the device
• Loss of function with permanent damage to equipment;
the device fails the test
Criteria A is the most desirable with Criteria D being
unacceptable. Permanent damage results in system down
time and the expense of repair and replacement. For mission
critical systems, Category B and Category C will also be
unacceptable, as the system must operate without errors
during transient events.
TRANSIENT PROTECTION
When designing circuitry to protect against transients, the
designer must consider a few main items:
1. The circuitry must prevent or limit damage caused by
the transient and allow the system to return to normal
operation with minimal impact on performance.
2. The protection scheme should be robust enough to deal
with the type of transients and voltage levels the system
would be subjected to in the field.
3. The length of time associated with the transient is an
important factor. For long transients, heating effects
can cause certain protection schemes to fail.
4. Under normal conditions, the protection circuitry
should not interfere with system operation.
5. If the protection circuitry fails during overstress, it
should fail in such a way as to protect the system.
Figure 5 shows a typical protection scheme, which can be
characterized as having primary and secondary protection.
Primary protection, which diverts most of the transient
energy away from the system, is typically located at the
interface between the system and the environment. It is
designed to remove the majority of the energy by diverting
the transient to ground.
Secondary protection protects various parts of the system
from any transient voltages and currents let through by the
primary protection. It is optimized to ensure that it protects
against these residual transients while allowing normal
operation of these sensitive parts of the system. It is essential
that both primary and secondary designs are specified to work
together in conjunction with the system I/O to minimize the
stress on the protected circuit. These designs typically
include a coordinating element such as a resistance or a
nonlinear overcurrent protection device between the
primary and secondary protection devices to ensure that
coordination occurs.
Figure 5. Protection Scheme - Block Diagram
RS-485 TRANSIENT SUPPRESSION NETWORKS
By nature, EMC transient events vary in time, so the dynamic
performance and the matching of the dynamic characteristics
of the protection components with the input/output stage
of the protected device leads to successful EMC design.
Component data sheets generally only contain dc data,
which is of limited value given that the dynamic breakdowns
and I/V characteristics can be quite different from the dc
values. Careful design, characterization and an understanding
of the dynamic performance of the input/output stage of the
protected device and the protection components is required
to ensure that the circuit meets EMC standards.

Page 6 of 10
The circuits shown in Figure 6 illustrate three different fully
characterized EMC compliant solutions. Each solution was
certified by an independent external EMC compliance test
house, and each provides different cost/protection levels for
the Analog Devices ADM3485E 3.3 V RS-485 transceiver
with enhanced ESD protection using a selection of Bourns
external circuit protection components. The Bourns external
circuit protection components used consist of transient
voltage suppressors (CDSOT23-SM712), transient blocking
unit (TBU-CA065-200-WH), thyristor surge protectors
(TISP4240M3BJR-S), and gas discharge tubes (2038-15-SM-
RPLF).
Each solution was characterized to ensure that the dynamic
I/V performance of the protection components protects the
dynamic I/V characteristics of the ADM3485E RS-485 bus
pins such that the interaction between the input/output stage
of the ADM3485E and the external protection components
function together to protect against the transient events.
Figure 6. Three EMC Compliant ADM3485E Circuits (Simplified Schematic, All Connections Not Shown)

Page 7 of 10
PROTECTION SCHEME 1
As described earlier, the EFT and ESD transient have similar
energy levels, while the surge waveform has energy levels
three to four magnitudes greater. Protecting against ESD
and EFT is accomplished in a similar manner, but protecting
against high levels or surge requires more complex solutions.
The first solution described here protects up to Level 4 ESD
and EFT and Level 2 surge. The 1.2/50 μs waveform is used
in all surge testing described in this article.
This solution uses the Bourns CDSOT23-SM712 transient
voltage suppressor (TVS) array, which consists of two
bidirectional TVS diodes optimized to protect RS-485
systems with minimal overstress while allowing the full
range of RS-485 signal and common mode excursions
(–7 V to + 12 V) on the RS-485 transceiver. Table 1 shows
the voltage levels protected against for ESD, EFT, and surge
transients.
Table 1. Solution 1 Protection Levels
ESD (-4-2) EFT (-4-4) Surge (-4-5)
Level Voltage (contact/air) Level Voltage Level Voltage
4 8 kV/15 kV 4 2 kV 2 1 kV
A TVS is a silicon based device. Under normal operating
conditions, the TVS has high impedance to ground; ideally,
it is an open circuit. The protection is accomplished by
clamping the overvoltage from a transient to a voltage limit.
This is done by the low impedance avalanche breakdown of
a PN junction. When a transient voltage larger than the
breakdown voltage of the TVS is generated, the TVS clamps
the transient to a predetermined level that is less than the
breakdown voltage of the devices that it is protecting. The
transients are clamped instantaneously (< 1 ns), and the
transient current is diverted away from the protected device
to ground.
It is important to ensure that the breakdown voltage of the
TVS is outside the normal operating range of the pins
protected. The unique feature of the CDSOT23-SM712 is
that it has asymmetrical breakdown voltages of +13.3 V and
–7.5 V to match the transceiver common mode range of
+12 V to –7 V, therefore providing optimum protection
while minimizing overvoltage stresses on the ADM3485E
RS-485 transceiver.
Figure 7. CDSOT23-SM712 I/V Characteristic
PROTECTION SCHEME 2
The previous solution protects up to Level 4 ESD and EFT
but only to Level 2 surge. To improve the surge protection
level, the protection circuitry gets more complex. The following
protection scheme will protect up to Level 4 surge.
The CDSOT23-SM712 is specifically designed for RS-485
data ports. The next two circuits build on the CDSOT23-
SM712 to provide higher levels of circuit protection. The
CDSOT23-SM712 provides secondary protection while the
TISP4240M3BJR-S provides the primary protection. Co-
ordination between the primary and secondary protection
devices and overcurrent protection is accomplished using
the TBU-CA065-200-WH. Table 2 shows the voltage levels
protected against for ESD, EFT, and surge transients with
this protection circuit.
ESD (-4-2) EFT (-4-4) Surge (-4-5)
4 8 kV/15 kV 4 2 kV 4 4 kV
When a transient is applied to the protection circuit, the
TVS will break down, protecting the device by providing a
low impedance path to ground. With large voltages and
currents, the TVS must also be protected by limiting the
current through it. This is done using a transient blocking
unit (TBU), which is an active high speed overcurrent
protection element. The TBU in this solution is the Bourns
TBU-CA065-200-WH.
A TBU blocks current rather than shunting it to ground. As
a series component, it reacts to current through the device
rather than the voltage across the interface. A TBU is a high
speed overcurrent protection component with a preset
current limit and a high voltage withstand capability. When
an overcurrent occurs and the TVS breaks down due to the
transient event, the current in the TBU will rise to the current

Page 8 of 10
limiting level set by the device. At this point, the TBU
disconnects the protected circuitry from the surge in less
than 1 µs. During the remainder of the transient, the TBU
remains in the protected blocking state, with very low
current (<1 mA) passing through to the protected circuit.
Under normal operating conditions, the TBU exhibits low
impedance, so it has minimal impact on normal circuit
operation. In blocking mode, it has very high impedance to
block transient energy. After the transient event, the TBU
automatically resets to its low impedance state and allows
resumption of normal system operation.
Like all overcurrent protection technologies, the TBU has
a maximum breakdown voltage, so a primary protection
device must clamp the voltage and redirect the transient
energy to ground. This is commonly done using technologies
such as gas discharge tubes or solid-state thyristors, such as
the totally integrated surge protector (TISP). The TISP acts
as a primary protection device. When its predefined protection
voltage is exceeded, it provides a crowbar low impedance
path to ground, hence diverting the majority of the transient
energy away from the system and other protection devices.
The nonlinear voltage-current characteristic of the TISP
limits overvoltage by diverting the resultant current. As a
thyristor, a TISP has a discontinuous voltage-current
characteristic caused by the switching action between high
and low voltage regions. Figure 9 shows the voltage current
characteristic of the device. Before the TISP device switches
into a low voltage state, with low impedance to ground to
shunt the transient energy, a clamping action is caused by
the avalanche breakdown region. In limiting an overvoltage,
the protected circuitry will be exposed to a high voltage for
the brief time period that the TISP device is in the breakdown
region before it switches into a low-voltage protected on-
state. The TBU will protect the downstream circuitry from
high currents resulting from this high voltage. When the
diverted current falls below a critical value, the TISP device
automatically resets allowing normal system operation to
resume.
As described, all three components work together in
conjunction with the system I/O to protect the system from
high voltage and current transients.
Figure 9. TISP Switching Characteristic and Voltage Limiting Waveshape

Page 9 of 10
PROTECTION SCHEME 3
Protection levels above Level 4 surge are often required.
This protection scheme will protect RS-485 ports up to and
including 6 kV surge transients. It operates in a similar
fashion to protection scheme 2, but in this circuit, a gas
discharge tube (GDT) is used in place of the TISP to protect
the TBU, which is, in turn, protecting TVS, the secondary
protection device. The GDT will provide protection to
higher overvoltage and overcurrent stress than the TISP
described in the previous protection scheme. The GDT for
this protection scheme is the Bourns 2038-15-SM-RPLF. The
TISP is rated at 220 amps versus the GDT rating of 5 kA per
conductor. Table 3 shows the protection levels provided by
this design.
ESD (-4-2) EFT (-4-4) Surge (-4-5)
4 8 kV/15 kV 4 2 kV X 6 kV
Predominately used as a primary protection device, a GDT
provides a low impedance path to ground to protect against
overvoltage transients. When a transient voltage reaches the
GDT spark-over voltage, the GDT will switch from a high
impedance off-state to arc mode. In arc mode, the GDT
becomes a virtual short, providing a crowbar current path to
ground and diverting the transient current away from the
protected device.
Figure 10 shows the typical characteristics of a GDT. When
the voltage across a GDT increases, the gas in the tube starts
to ionize due to the charge developed across it. This is known as
the glow region. In this region, the increased current flow
will create an avalanche effect that will transition the GDT
into a virtual short circuit, allowing current to pass through
the device. During the short circuit event, the voltage
developed across the device is known as the arc voltage. The
transition time between the glow and arc region is highly
dependent on the physical characteristics of the device.
Figure 10. GDT Characteristic Waveform
CONCLUSION
This article described the three IEC standards of interest that
deal with transient immunity. In real industrial applications,
RS-485 communication ports subjected to these transients
can be damaged. EMC problems discovered late in a product
design cycle may require expensive redesign and can often
lead to schedule overruns. EMC problems should, therefore,
be considered at the start of the design cycle and not at a
later stage where it may be too late to achieve the desired
EMC performance.
The key challenge in designing EMC compliant solutions for
RS-485 networks is matching the dynamic performance of the
external protection components with the dynamic performance
of the input/output structure of the RS-485 device
This article demonstrated three different EMC compliant
solutions for RS-485 communication ports, giving the
designer options depending on the level of protection
required. The EVAL-CN0313-SDPZ is the industry's first
EMC compliant RS-485 customer design tool, providing up
to Level 4 protection levels for ESD, EFT, and surge. The
protection levels offered by the different protection schemes
are summarized in Table 4. While these design tools do not
replace the due diligence or qualification required at the
system level, they allow the designer to reduce risk of project
slippage due to EMC problems at the start of the design
cycle, hence reducing design time and time to market. For
more information, please visit: www.analog.com/RS485emc.
Table 4. Three ADM3485E EMC Compliant Solutions
ESD (-4-2) EFT (-4-4) Surge (-4-5)
Protection Scheme Level Voltage (contact/air) Level Voltage Level Voltage
TVS 4 8 kV/15 kV 4 2 kV 2 1 kV
TVS/TBU/TISP 4 8 kV/15 kV 4 2 kV 4 4 kV
TVS/TBU/GDT 4 8 kV/15 kV 4 2 kV X 6 kV

Page 10 of 10
REFERENCES:
ADM3485E Data Sheet.
Analog Devices Interface and Isolation.
http://www.analog.com/en/interface-
isolation/products/index.html.
Bourns Telecom Protection Guide.
www.bourns.com/data/global/pdfs/bourns_circuit_protectio
n_selection_guide.pdf.
CDSOT23-SM712. www.bourns.com/pdfs/CDSOT23-
SM712.pdf.
Electromagnetic Compatibility (EMC) Part 4-2: Testing and
Measurement Techniques—Electrostatic Discharge
Immunity Test (IEC61000-4-2:2008 (Ed. 2.0)).
Measurement Techniques—Electrical Fast Transient/Burst
Immunity Test (IEC61000-4-4:2012 (Ed. 3.0)).
Measurement Techniques—Surge Immunity Test
(IEC61000-4-5:2005 (Ed. 2.0)).
EVAL-CN0313-SDPZ. www.analog.com/RS485emc.
GDT First Principles.
www.bourns.com/pdfs/bourns_gdt_white_paper.pdf.
Marais, Hein. Application Note AN-960. RS-485/RS-422
Circuit Implementation Guide, April, 2008.
TBU-CA065-200-WH.
www.bourns.com/data/global/pdfs/TBU-CA.pdf.
TISP4240M3BJR-S.
www.bourns.com/data/global/pdfs/TISP4xxxM3BJ.pdf.
2038-15-SM-RPLF.
www.bourns.com/data/global/pdfs/2038-xx-SM.pdf.
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