M-TECH 4th SEM PRESENTATION

A presentation on
Design of OPAMP Based R-2R Ladder Type 4-bit Digital to
Analog Converter (DAC) Using 90nm CMOS Technology
Submitted by Under the guidance of
Subhajit Shaw Mr. Soumen Pal
M.TECH in Micro Electronics & VLSI Designs
NARULA INSTITUTE OF TECHNOLOGY
UNIVERSITY Roll No: 12710414002.
UNIVERSITY Registration No: 141270410002 of 2014-2015.
113/06/2016 Narula Institute of Technology

Contents
 INTRODUCTION
 TWO STAGE CMOS OP-AMP
 GIVEN SPECIFICATIONS OF OP-AMP
 DESIGN PARAMETERS OF OP-AMP
 SPICE CIRCUIT DIAGRAM OF CMOS OP-AMP(Using T-SPICE Tool)
 SIMULATED RESULTS OF CMOS OP-AMP
 R-2R LADDER DAC
 SPECIFICATIONS OF R-2R LADDER DAC
 SPICE CIRCUIT DIAGRAM OF R-2R LADDER DAC (Using T-SPICE Tool)
 SIMULATED RESULTS OF R-2R LADDER DAC
 CONCLUSION
 FURTHER ENHANCEMENT
 REFFERENCES
2

Introduction
 High resolution digital to analog converters (DACs) are highly
demanded in today’s wireless communication applications.
 The basic theory of the R-2R ladder network is that current
flowing through any input resistor (2R) encounters two possible
paths at the far end.
 The total resistances of both paths are the same (also 2R), so the
incoming current splits equally along both paths.
 The R-2R resistor ladder network directly converts a parallel
digital symbol/word into an analog voltage.
 The goal of this thesis is to design the R-2R Ladder type 4-bit
digital to analog converter (DAC) using 90nm CMOS technology
which is based on two stage CMOS Op-Amp.
13/06/2016 3Narula Institute of Technology

Two Stage CMOS Op-Amp
 The two stage CMOS Op-amp is widely used because of its simple structure
,robustness and very high Gain.
 Current mirror are used extensively in CMOS Op-amp circuits both as
active load elements and biasing circuits to get a high AC voltage gain.
 Designing of an Op-amp requires some predefined electrical specifications
such as gain ,band width, slew rate, input common mode range and
maximum output swing .
 Op-amp are designed to be operated with negative feedback connection to
ensure the stability of the system.
 The basic structure of two stage CMOS op-amp is shown in the following
diagram Which includes differential gain stage(First stage), output
stage(Second stage), compensation circuit and biasing circuit.

Basic circuit diagram of two stage op-amp
5

Given design specifications
Electrical Parameters Expected values
Supply voltage ±1V
Load Capacitance 1 pF
Unity gain frequency 100MHz
Slew rate ±10 volt/µsec
Input Common mode range ±0.4volt
Output swing ±0.9 volt

Design procedure of two stage op-amp

Design procedure of two stage op-amp
cont’d

Design parameters of op-amp
Parameters Value Unit
Cc 200 fF
CL 1 pF
(W/L)1,2 9500/100 nm/ nm
(W/L)3,4
2170/100 nm/ nm
(W/L)5,8
120/100 nm / nm
(W/L)6
21400/100 nm/ nm
(W/L)7
480/100 nm / nm
(W/L)9
120/100 nm/ nm
9
13/06/2016
Narula Institute of Technology

Circuit diagram of two stage op-
amp(Using T-SPICE Tool)

DC response of designed op-amp in non
inverting mode

Transient response in non inverting mode
V(IN)

Transient response in non inverting mode
V(OUT)

AC response[Magnitude vs Frequency]

AC response[Phase vs Frequency]

What is a DAC?
DAC
100101…
 A digital to analog
converter (DAC) is a
device that converts
digital numbers (binary)
into an analog voltage or
current output.

What is a DAC?
 Each sample is converted from binary to analog, between 0 and Vref for
Unipolar, or Vref and –Vref for Bipolar
10111001 10100111 10000110010101000011001000010000
Digital Input Signal
AnalogOutputSignal

R-2R Ladder D/A Converter
 The 4-bit R-2R ladder type DAC is the most popular DAC.
 It uses a ladder network containing series-parallel combinations
of values R and 2R.
 It is easily scalable to any desired number of bits.
 It’s uses only two values of resistors which make for easy and
accurate fabrication and integration.
 Output impedance is equal to R, regardless of the number of
bits, simplifying filtering and further analog signal processing
circuit design.
13/06/2016 18Narula Institute of Technology

R-2R Ladder D/A Converter
0
4 bit converter
0 0 0
Each bit corresponds to a switch:
• If the bit is high, the
corresponding switch is
connected to the inverting
input of the op-amp.
• If the bit is low, the
corresponding switch is
connected to ground.
 Requires only two precision resistance value (R and 2R)

R-2R Ladder Example
Convert 0001 to analog
1
1/ 2 1/ 2
eqR R
R R
 

0 1 1
1
2
R
V V V
R R
 

1 2 2
1
2
R
V V V
R R
 

2 3 3
1
2
R
V V V
R R
 


R-2R Ladder Example
Convert 0001 to analog
R
2R
0
1
8
refV V
out 0
R 1
V
2R 16
refV V   

R-2R DAC Summary
 Conversion results for each bit
Digital bit Analog Conversion
0001
0010
0100
1000
,0 /16out refV V 
,1 /8out refV V 
,2 / 4out refV V 
,3 / 2out refV V 
3 ,3 2 ,2
1 ,1 0 ,0
out out out
out out
V b V b V
bV b V
 
 
for
3 2 1 0 ( 0 or 1)ib b b b b 
 Conversion equation for N-bit DAC
( )
1 2
N
ref
out N i i
i
V
V b 

  Resolution
2
ref
N
V


 Advantages
 Only two resistor values
 Does not need as precision resistors as Binary weighted DACs
 Cheap & Easy to manufacture
 Faster response time
 Disadvantages
 Slower conversion rate
 More confusing analysis
R-2R DAC Summary

Specification of DAC
Resolution
Speed
Settling time
Linearity
Reference voltage

Specification - Resolution
25
 Resolution of a DAC is the change in output voltage for a
change in the least significant bit (LSB) of the digital input.
 Resolution is specified in “bits”.
 Most DACs have a resolution of 8 to 16 bits
 Example: A DAC with 10 bits has a resolution of
 Higher resolution (more bits) = smoother output.
ref10
ref
1024
1
2
Resolution V
V

bitsofnumberN
V
V N
ref
LSB


where
2
Resolution

Also called the conversion rate or sampling rate
- rate at which the register value is updated
Rate of conversion of a single digital input to its
analog equivalent
Conversion Rate depends on
 clock speed of input signal
 settling time of converter
When the input changes rapidly, the DAC
conversion speed must be high.
Specification - Speed

 The time required for the input signal voltage to settle to the expected
output voltage (within +/- ½ of VLSB).
 Ideally, an instantaneous change in analog voltage would occur when a
new binary word enters into DAC
 Fast converters reduce slew time, but usually result in longer ring time.
Specification – Settling Time
tdelay
tslew tring

Specification – Linearity
Linearity(Ideal Case)
Digital Input
Perfect Agreement
Desired/Approximate Output
AnalogOutput
Voltage
NON-Linearity(Real World)
AnalogOutput
Voltage
Digital Input
Desired Output
Miss-alignment
Approximate
output
 The difference between the desired analog output and the actual
output over the full range of expected values.
 Ideally, a DAC should produce a linear relationship between a digital
input and the analog output, this is not always the case.

 A specified voltage used to determine how each digital input will
be assigned to each voltage division.
 Types:
 Non-multiplier DAC: Vref is fixed (specified by the
manufacturer)
 Multiplier DAC: Vref is provided via an external source
Specification – Reference Voltage
 Full Scale Voltage
 Defined as the output when digital input is all 1’s.
1
1
0
2 1
1
2 2
N N
ref
fs refi N
i
V
V V



 
    
 
 


Circuit diagram of R-2R Ladder D/A
Converter(Using T-SPICE Tool)

Output Waveform of D /A Converter

Comparison between
Expected Output & Simulated Output
 Table 1:- Performance summary
Sl.No. Input Pulse
(Bit Value)
Ideal Output
(mV)
Simulated Output
(mV)
1 0000 0.0 0.0
2 0001 062.5 55.80
3 0010 125.0 112.79
4 0011 187.5 167.24
5 0100 250.0 242.44
6 0101 312.5 294.79
7 0110 375.0 366.68
8 0111 437.5 419.07

Comparison between
Expected Output and Simulated Output
Sl.No. Input Pulse
(Bit Value)
Ideal Output
(mV)
Simulated Output
(mV)
9 1000 500.0 489.16
10 1001 562.5 547.73
11 1010 625.0 602.18
12 1011 687.5 672.34
13 1100 750.0 730.66
14 1101 812.5 770.87
15 1110 875.0 802.23
16 1111 937.5 821.78

Comparison between
 Table 2:-Deviation among successive outputs
Sl.No. Expected Result
(mV)
Simulated Output
(mV)
1 62.5 56.99
2 62.5 54.45
3 62.5 75.20
4 62.5 52.35
5 62.5 71.89
6 62.5 52.99
7 62.5 69.49

Comparison between
Sl.No. Expected Result
(mV)
Simulated Output
(mV)
8 62.5 58.57
9 62.5 54.45
10 62.5 70.16
11 62.5 58.32
12 62.5 40.21
13 62.5 31.36
14 62.5 19.55

Conclusion
 In this work, a two stage op-amp has been designed using
90nm CMOS technology and a 4-bit R-2R ladder type
digital to analog converter is also realised using designed
Op-Amp. The simulation results confirm that the design
procedure is suitable for op-amp based DAC design in
90nm CMOS technology. The designed DAC is simulated
using TANNER Tool using 90nm CMOS technology. The
simulation results shows that the deviations among
successive outputs become more non-linear for higher order
digital input bits as depicted in Table 2.

Future plan
 In this work 90nm CMOS technology has been used. Further
reduction in MOSFET channel length can be done to ensure
more integration.
 The design of DAC can be enhanced further, considering the
specifications like resolution, offset error, Differential Non-
Linearity (DNL) and Integral Non-Linearity (INL).
 In Communication System and signal processing purpose,
A/D converter and D/A converter are inseparably used as a
front end and rare end blocks respectively. The designed D/A
converter can also be utilised to design A/D converter.

References
1. Phillip E. Allen and Douglas R. Holberg, “CMOS AnalogCircuit
Design”. Second Edition. Prentice-Hall, 2002.
2. D. Johns, and K. Martin, “Analog integrated circuit design," John
Wiley & Sons, 1997,ISBN: 0-471-14448-7.
3. Fateh Moulahcene, Nour-Eddine Bouguechal, Imad Benacer and
Saleh Hanfoug, “Design of CMOS Two-stage Operational
Amplifier for ECG Monitoring System Using 90nm Technology”,
International Journal of Bio-Science and Bio-Technology Vol.6,
No.5 (2014), pp.55-66.
4. J. Huynh, B. Ngo, M. Pham, and L. He, “Design of a 10 Bit TSMC
0.25μm CMOS Digital to Analog Converter”, 2005 IEEE,
lhe@email.sjsu.edu
5. J. Baker, H. Li, and D. Boyce, “CMOS - circuit design, layout, and
simulation," IEEE Press, 1998, ISBN 0-7803-3416-7.

6. Amana Yadav , “Design of Two-Stage CMOS Op-Amp and
Analyze the Effect of Scaling”, Vol. 2, Issue 5, September-
October 2012, pp.647-654.
7. Basanta Bhowmik, Manisha Pattanaik, Pankaj Srivastava, “A Low
Power Low Noise Two Stage CMOS Operational Amplifier for
Biopotential Signal Acquisition System”, ISSN 2250-2459, ISO
9001:2008 Certified Journal, Volume 3, Issue 4, April 2013,
Website: www.ijetae.com.
8. A Sowjanya , “Implementation of 4-bit R-2R DAC on CADENCE
Tools”, ISSN: 2321-9939, Volume 4, Issue 1, IJEDR 2016.
9. Ankit Upadhyay, Rajanikant M. Soni , “3-bit R-2R Digital to
Analog Converter with Better INL & DNL ” , IJEAT Journal
,ISSN: 2249 – 8958, Volume-2, Issue-3, February 2013.
10. Benjamin Jankunas , “ Design and Calibration of a 12- Bit
Current-Steering Dac Using Data-Interleaving” , Approved
September 2014 by the Graduate Supervisory Cmmittee.
References

11. “ world’s fastest Digital to Analog Converter (DAC)” from
Tektronix Component Solutions.
12. https://www.google.co.in/url?sa=t&rct=j&q=&esrc=s&source=we
b&cd=1&cad=rja&uact=8&ved=0ahUKEwjVlPOWxd7MAhWL
QY8KHWT6A1oQFggcMAA&url=http%3A%2F%2Fume.gatech.
edu%2Fmechatronics_course%2FDAC_S06.ppt&usg=AFQjCNFs
hvpTBjo_2PpiDda4yBOR7-fW9g&bvm=bv.122129774,d.c2I
13. B. Razavi, “Design of Analog CMOS Integrated Circuits”,
McGraw-Hill Higher Education, 2002
14. Mr. Soumen Pal, Ms. Pinky Ghosh, “ Design & simulation of two
stage low power cmos op-amp in nm range”,ICCACCS, pp-425-
432, Springer, 2014.
15. Etienne SICARD Professor, INSA-Dgei,“Introducing 90 nm
technology in Microwind3”, Website: Etienne, sicardtdlinsa-
toulouse. Fr .
References

16. Scott E. Thompson et al:“A 90-nm Logic Technology
Featuring Strained-Silicon”,IEEE Transactions On
Electron Devices, Vol. 51, No. 11, November 2004.
17. Yoshihiro Takao, Satoshi Nakai and Naoto Horiguchi,
“Extended 90 nm CMOS Technology with High
Manufacturability for High- Performance, Low-Power,
RF/Analog Applications”, Manuscript received
December 9, 2002.
18. Alexander gurney et al:
ume.gatech.edu/mechatronics_course/DAC_F10. .pptx.
References

Questions

Thank you.

M-TECH 4th SEM PRESENTATION

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