Multi-threading your way out
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The document discusses multi-threading, race conditions, and the importance of memory barriers in concurrent programming. It explains how compiler optimizations and out-of-order execution can lead to unexpected behavior when multiple threads access shared variables. Various techniques, such as atomic operations and memory barriers, are suggested to ensure correct synchronization and prevent issues related to memory consistency.
Multi-threading your way out
- 1. Multi-threading your way out Rokas Antanas Balevičius
- 2. Why we have “race conditions” ?
- 3. RAM L3 L2 L1 RAX L1 RAX
- 5. public void Thread1 { a = 1; b = 1; } public void Thread2 { while(b == 0) {continue;} Assert(a == 1); } public void Thread1 { b = 1; a = 1; } public void Thread2 { while(b == 0) {continue;} Assert(a == 1); }
- 6. Compiler and JIT optimizations
- 7. var b = 0; public void Thread1 { b = 1; } public void Thread2 { while(b == 0) {continue;} Foo(); } var b = 0; public void Thread1 { b = 1; } public void Thread2 { if (b == 0) { while(true) { continue; } } Foo(); }
- 8. Preemption
- 9. T1 T2 T3 TN 20 ms 20 ms 20 ms 20 ms
- 10. Limit Compiler and Jit optimizations Limit CPU optimizations Do things atomically
- 13. “In practice, however, they are informal prose documents” - Smart people at Cambridge University
- 15. Everything goes through Cache Reads are simple and pull based
- 18. Writes are exclusive Modern cache is write-back Cache is coherent (MESI)
- 20. L1 (A) CPU1 (A+) Bus L1 (A) CPU2
- 23. Everything goes through Cache Reads are pull based Writes are exclusive Cache is coherent (MESI)
- 24. Problem: idle on writes
- 26. public void Thread1 { a = 1; b = 1; } public void Thread2 { while(b == 0) {continue;} Assert(a == 1); }
- 27. L1 (B, A) CPU1 Bus Store Buffer L1 (A) CPU2 Store Buffer
- 28. L1 (B, A) CPU1 Bus Store Buffer (A+) L1 (A) CPU2 Store Buffer
- 29. L1 (B+, A) CPU1 Bus Store Buffer (A+) L1 (A) CPU2 Store Buffer
- 30. L1 (B+, A) CPU1 Bus Store Buffer (A+) L1 (A, B+) CPU2 Store Buffer
- 31. Boom!
- 32. CPU2 saw writes in different order CPU1 did everything in order
- 33. L1 (A+, B+) CPU1 Bus Store Buffer L1 (A+, B+) CPU2 Store Buffer
- 35. public void Thread1 { a = 1; Thread.MemoryBarrier() ; b = 1; } public void Thread2 { while(b == 0) {continue;} Assert(a == 1); }
- 36. L1 (B, A) CPU1 Bus Store Buffer (A+) L1 (A) CPU2 Store Buffer
- 37. L1 (B, A) CPU1 Bus Store Buffer (A+, B+) L1 (A) CPU2 Store Buffer
- 38. L1 (A+, B) CPU1 Bus Store Buffer (B+) L1 (A) CPU2 Store Buffer
- 39. L1 (A+, B+) CPU1 Bus Store Buffer L1 (A, B+) CPU2 Store Buffer
- 40. L1 (A+, B+) CPU1 Bus Store Buffer L1 (A+, B+) CPU2 Store Buffer
- 41. Acknowledging invalidates is slow
- 42. Lets improve performance again
- 44. L1 (A, B) CPU1 Bus Store Buffer (A+, B+) Invalidate Queue L1 (A) CPU2 Store Buffer Invalidate Queue
- 45. L1 (A, B) CPU1 Bus Store Buffer (A+, B+) Invalidate Queue L1 (A) CPU2 Store Buffer Invalidate Queue (A)
- 46. L1 (A+, B+) CPU1 Bus Store Buffer Invalidate Queue L1 (A) CPU2 Store Buffer Invalidate Queue (A)
- 47. L1 (A+, B+) CPU1 Bus Store Buffer Invalidate Queue L1 (A, B+) CPU2 Store Buffer Invalidate Queue (A)
- 49. public void Thread1 { a = 1; Thread.MemoryBarrier() ; b = 1; } public void Thread2 { while(b == 0) {continue;} Thread.MemoryBarrier() ; Assert(a == 1); }
- 50. L1 (A+, B+) CPU1 Bus Store Buffer Invalidate Queue L1 (A, B+) CPU2 Store Buffer Invalidate Queue (A)
- 51. L1 (A+, B+) CPU1 Bus Store Buffer Invalidate Queue L1 (A, B+) CPU2 Store Buffer Invalidate Queue
- 52. L1 (A+, B+) CPU1 Bus Store Buffer Invalidate Queue L1 (A+, B+) CPU2 Store Buffer Invalidate Queue
- 53. Memory barriers also limit compiler and JIT optimizations
- 55. OK OK OK OK OK OK Memory Barrier Code Line 1 Code Line 2 Code Line 3 Code Line 1 Code Line 2 Code Line 1 Code Line 2 Memory Barrier
- 56. Memory Barrier Code Line 1 Code Line 2 Code Line 3 Code Line 1 Code Line 2 Code Line 1 Code Line 2 Memory Barrier NO! NO!NO! NO!
- 57. Barrier pairing
- 58. Part 2: Atomic operation
- 59. LOCK CMPXCHG
- 60. int locker = 0; Interlocked.CompareExchange(ref locker, 1, 0) == 0
- 62. Time to get back to reality
- 63. C# Thread vs OS Thread
- 64. High level critical sections
- 65. OK OK OK OK OK OK Atomic Acquire Barrier Code Line 1 Code Line 2 Code Line 3 Code Line 1 Code Line 2 Code Line 1 Code Line 2 Atomic Release Barrier
- 66. Atomic Acquire Barrier Code Line 1 Code Line 2 Code Line 3 Code Line 1 Code Line 2 Code Line 1 Code Line 2 NO! NO!Atomic Release Barrier
- 67. Kind of ok Kind of ok Atomic Acquire Barrier Code Line 1 Code Line 2 Code Line 3 Code Line 1 Code Line 2 Code Line 1 Code Line 2 Atomic Release Barrier
- 68. Memory Barrier Atomic Memory Barrier Memory Barrier Atomic Memory Barrier C# Primitive C# Primitive Code Line 1 Code Line 2 Code Line 3 Code Line 1 Code Line 2 Code Line 1 Code Line 2
- 69. Spinning
- 70. Blocking
- 72. It is all about Speculations
- 74. Multithread GC More non-blocking algorithms Signaling IO bound scenarios ….
- 75. Thank you