Nikita Resume
- 1. Nikita S. Patel 3674 Sutton Loop, Fremont CA 94536, (Ph) (408)887-8912, nikita_sanjose@yahoo.com OBJECTIVE: Seeking an Entry level Full Time Position in the Field of Electrical Engineering EDUCATION: M.S. in Electronic Materials and Devices (VLSI Design) San Jose State University, San Jose G.P.A 3.5 May 2009 B.E. in Electrical Engineering, Gujarat University, S.V.I.T, Vasad G.P.A 3.54 June 2005 Related Coursework: High Speed CMOS Design ASIC Design Analog and Mixed Signal Design Semiconductor Devices IC Process Design System Engineering Engineering Analysis Engineering Management Master’s Project-1 Master’s Project-2 KNOWLEDGE AND SKILLS: Operating systems: DOS, Windows, UNIX. CAD Tool: Virtuoso -Cadence IC Design tool, Synopsys TCAD tool, AutoCAD Programming languages: Assembly Language (For Microprocessors 8085, 8086), C, C++ Simulation tools: Cadence specters spice simulation, Hspice IC Fabrication: Fabrication Lab experience (Clean Room). Lab Equipment: Oscilloscope, Parametric Analyzer Computer Software Tool: MS Excel, MS Office, MS PowerPoint, PROJECTS: 16-Bit ALU: Designed a 16-bit ALU in IBM0.13u process in four phase clock dynamic logic, using “Virtuoso” -Cadence IC Design tool. Jan 2007 - Achieved latency =13 phase & design met 80ps phase time at 3.125 GHz Clock requirement. - Used Spectra spice simulation tool to simulate the entire logic block. The ALU perform all the basic 24 function (XOR, AND, OR, Addition, Subtraction, Increment, decrement etc.) The different functions were verified by observing the transient analysis waveforms. - Extracted the layouts of individual blocks and performed LVS check. The extracted layout was verified using analog extracted simulation. - The project started with conceptual design stage where by we made block diagrams, did load calculation from back to front end, transistor sizing, Schematic generation, floor planning, Layout, Waveforms from spectra spice and analog extracted simulation. 6-Bit DAC: Designed a 6-BitDAC (Schematic and Layout) in TSMC 0.18u process, Clock rate ~ 200 MHz, using “Virtuoso” Cadence IC design tool. Aug 2007 - The current steering DAC logic was used for this project. The stable current reference designed for voltage variation and temperature variation. It was extremely challenging to design stable current source. - The digital code is converted in to thermometer code in four phase clock dynamic logic. The digital part was relatively simple than the analog part. - Another challenge was to control glitch appearing on analog output at each digital code change. We used pass gate controlled through evaluation phase of next stage as control signal that eliminate the output to go low. We placed two stage static inverters with weak keeper on each inverter to hold last control status which will keep current source either ON or OFF permanently during precharge phase of the last stage.
- 2. - Used Spectra spice simulation tool to simulate entire logic block and performed tone test and observed transient analysis. - Extracted the layouts of individual blocks and performed LVS check. The extracted layout was verified by using analog extracted simulation. Fabrication Project: The project includes basic fabrication processes of integrated circuits; material preparation, oxidation, diffusion; photolithographic, thin-film deposition and etching. Jan 2007 - Performed component layout - The Device wafer evaluated using HP4145 Parametric analyzer - Measured the threshold voltage and effective channel length of the transistors - Verified the Id-Vd characteristic of the transistor and diode High Speed 8-Bit Microcontroller: Designed 8 bit embedded microcontroller (Schematic and Layout) in IBM0.13u process. May2009 - Designed at 1.5GHz clock frequency using the four phase clocked dynamic logic - Implemented Xilinx soft core Pico blaze microcontroller design for the high speed application. - The project started with conceptual design stage where we first made architectural block diagrams of 8-bit microcontroller, list of all control signals, Schematic of individual block , load calculation from back to front , transistor sizing and implemented the four stage pipelining (Fetch, Decode, Execute and Write back) to improve the instruction through put. - The designed microcontroller will support the following features 16- byte wide general purpose data register 1K×18 Instruction PROM Byte wide Arithmetic Logical Unit with CARRY and ZERO flags indicator 16-byte internal Scratchpad RAM 31-location CALL/RETURN stack Clock rate 1.5GHz - Used “Virtuoso” – Cadence IC design tool, Cadence specters spice simulation, Espresso logic reduction software and Dynsize software for transistor sizing in this project WORK EXPERIENCE: Electrical Engineering Intern: Adaptive Technology (INDIA) Pvt. Ltd. June 2004-June 2005 • Trained in multilayer Printed Circuit Board design • Learned routing signals, clocks, and component placement • Designed burn-in boards with high speed signal for high pin count devices • Designed Burn-In boards for HAST, OP-LIFE and THB environment • Used the Auto CAD Tool to design the Burn-In board. SJSU Volunteer work at present: • MSE Student Champion: Have been selected by department head to help out students with their MSE related questions. ACHIEVEMENTS: - Presented technical paper on the “Fuel Cell Buses “and” Efficient Illumination” in the competition held by ISTE, India. - Presented Technical paper on the “Phase Locked Loop (PLL) “in the ENGR200w class by referring IEEE papers. - Presented paper (case study project) on the “Management of Biogas Plant” in Management Class which includes the Project Planning, Organizing, Forecasting and Financial Controlling. - Presented paper on the topic of “Supply Chain Management” in the management class which covers the basic idea about the supply chain and the selection methods that are currently used in
- 3. the industries to select the supplier. REFERENCES: Will be furnished on request.