Non Ideal Transistor Theory- Mosfet second order effects

Lecture 4:
Nonideal
Transistor
Theory

CMOS VLSI Design
CMOS VLSI Design 4th Ed.
4: Nonideal Transistor Theory 2
Outline
 Nonideal Transistor Behavior
– High Field Effects
• Mobility Degradation
• Velocity Saturation
– Channel Length Modulation
– Threshold Voltage Effects
• Body Effect
• Drain-Induced Barrier Lowering
• Short Channel Effect
– Leakage
• Subthreshold Leakage
• Gate Leakage
• Junction Leakage
 Process and Environmental Variations

CMOS VLSI Design
Ideal Transistor I-V
 Shockley long-channel transistor models
 
2
cutoff
linear
saturatio
0
2
2
n
gs t
ds
ds gs t ds ds dsat
gs t ds dsat
V V
V
I V V V V V
V V V V



 

  
   
 

 


 



CMOS VLSI Design
Ideal vs. Simulated nMOS I-V Plot
 65 nm IBM process, VDD = 1.0 V
0 0.2 0.4 0.6 0.8 1
0
200
400
600
800
1000
1200
Vds
Ids (A)
Vgs = 1.0
Vgs = 1.0
Vgs = 0.8
Vgs = 0.6
Vgs = 0.4
Vgs = 0.8
Vgs = 0.6
Channel length modulation:
Saturation current increases
with Vds
Ion = 747 mA @
Vgs = Vds = VDD
Simulated
Ideal
Velocity saturation & Mobility degradation:
Saturation current increases less than
quadratically with Vgs
Velocity saturation & Mobility degradation:
Ion lower than ideal model predicts

CMOS VLSI Design
ON and OFF Current
 Ion = Ids @ Vgs = Vds = VDD
– Saturation
 Ioff = Ids @ Vgs = 0, Vds = VDD
– Cutoff
0 0.2 0.4 0.6 0.8 1
0
200
400
600
800
1000
Vds
Ids (A)
Vgs = 1.0
Vgs = 0.4
Vgs = 0.8
Vgs = 0.6
Ion = 747 mA @
Vgs = Vds = VDD

CMOS VLSI Design
Electric Fields Effects
 Vertical electric field: Evert = Vgs / tox
– Attracts carriers into channel
– Long channel: Qchannel proportional to Evert
 Lateral electric field: Elat = Vds / L
– Accelerates carriers from drain to source
– Long channel: v = μElat

CMOS VLSI Design
Coffee Cart Analogy
 Tired student runs from VLSI lab to coffee cart
 Freshmen are pouring out of the physics lecture hall
 Vds is how long you have been up
– Your velocity = fatigue × mobility
 Vgs is a wind blowing you against the glass (SiO2) wall
 At high Vgs, you are buffeted against the wall
– Mobility degradation
 At high Vds, you scatter off freshmen, fall down, get up
– Velocity saturation
• Don’t confuse this with the saturation region

CMOS VLSI Design
Mobility Degradation
 High Evert effectively reduces mobility
– Collisions with oxide interface

CMOS VLSI Design
Velocity Saturation
 At high Elat, carrier velocity rolls off
– Carriers scatter off atoms in silicon lattice
– Velocity reaches vsat
• Electrons: 107
cm/s
• Holes: 8 x 106
cm/s
– Better model

CMOS VLSI Design
Vel Sat I-V Effects
 Ideal transistor ON current increases with VDD
2
 Velocity-saturated ON current increases with VDD
 Real transistors are partially velocity saturated
– Approximate with α-power law model
– Ids scales with VDD
α
– 1 < α < 2 determined empirically (≈ 1.3 for 65 nm)
 
 
2
2
ox
2 2
gs t
ds gs t
V V
W
I C V V
L



  

CMOS VLSI Design
-Power Model
0 cutoff
linear
saturation
gs t
ds
ds dsat ds dsat
dsat
dsat ds dsat
V V
V
I I V V
V
I V V
 


 


 

 
 
/2
2
dsat c gs t
dsat v gs t
I P V V
V P V V



 
 

CMOS VLSI Design
Channel Length Modulation
 Reverse-biased p-n junctions form a depletion region
– Region between n and p with no carriers
– Width of depletion Ld region grows with reverse bias
– Leff = L – Ld
 Shorter Leff gives more current
– Ids increases with Vds
– Even in saturation
n
+
p
Gate
Source Drain
bulk Si
n
+
VDD
GND VDD
GND
L
Leff
Depletion Region
Width: Ld

CMOS VLSI Design
Chan Length Mod I-V
 λ = channel length modulation coefficient
– not feature size
– Empirically fit to I-V characteristics
   
2
1
2
ds gs t ds
I V V V


  

CMOS VLSI Design
Threshold Voltage Effects
 Vt is Vgs for which the channel starts to invert
 Ideal models assumed Vt is constant
 Really depends (weakly) on almost everything else:
– Body voltage: Body Effect
– Drain voltage: Drain-Induced Barrier Lowering
– Channel length: Short Channel Effect

CMOS VLSI Design
Body Effect
 Body is a fourth transistor terminal
 Vsb affects the charge required to invert the channel
– Increasing Vs or decreasing Vb increases Vt
 Vt0 = nominal threshold voltage
 s = surface potential at threshold
– Depends on doping level NA
– And intrinsic carrier concentration ni
 γ = body effect coefficient
 
0
t t s sb s
V V V
  
   
2 ln A
s T
i
N
v
n
 
si
ox
si
ox ox
2q
2q A
A
N
t
N
C

 

 

CMOS VLSI Design
Body Effect Cont.
 For small source-to-body voltage, treat as linear

CMOS VLSI Design
DIBL
 Electric field from drain affects channel
 More pronounced in small transistors where the
drain is closer to the channel
 Drain-Induced Barrier Lowering
– Drain voltage also affect Vt
 High drain voltage causes current to increase.
t t ds
V V V

  

CMOS VLSI Design
Short Channel Effect
 In small transistors, source/drain depletion regions
extend into the channel
– Impacts the amount of charge required to invert
the channel
– And thus makes Vt a function of channel length
 Short channel effect: Vt increases with L
– Some processes exhibit a reverse short channel
effect in which Vt decreases with L

CMOS VLSI Design
Leakage
 What about current in cutoff?
 Simulated results
 What differs?
– Current doesn’t
go to 0 in cutoff

CMOS VLSI Design
Leakage Sources
 Subthreshold conduction
– Transistors can’t abruptly turn ON or OFF
– Dominant source in contemporary transistors
 Gate leakage
– Tunneling through ultrathin gate dielectric
 Junction leakage
– Reverse-biased PN junction diode current

CMOS VLSI Design
Subthreshold Leakage
 Subthreshold leakage exponential with Vgs
 n is process dependent
– typically 1.3-1.7
 Rewrite relative to Ioff on log scale
 S ≈ 100 mV/decade @ room temperature
0
0e 1 e
gs t ds sb ds
T T
V V V k V V
nv v
ds ds
I I


   
 
 
 
 
 

CMOS VLSI Design
Gate Leakage
 Carriers tunnel thorough very thin gate oxides
 Exponentially sensitive to tox and VDD
– A and B are tech constants
– Greater for electrons
• So nMOS gates leak more
 Negligible for older processes (tox > 20 Å)
 Critically important at 65 nm and below (tox ≈ 10.5 Å)
From [Song01]

CMOS VLSI Design
Junction Leakage
 Reverse-biased p-n junctions have some leakage
– Ordinary diode leakage
– Band-to-band tunneling (BTBT)
– Gate-induced drain leakage (GIDL)
n well
n+
n+ n+
p+
p+
p+
p substrate

CMOS VLSI Design
Diode Leakage
 Reverse-biased p-n junctions have some leakage
 At any significant negative diode voltage, ID = -Is
 Is depends on doping levels
– And area and perimeter of diffusion regions
– Typically < 1 fA/μm2
(negligible)
e 1
D
T
V
v
D S
I I
 
 
 
 
 

CMOS VLSI Design
Band-to-Band Tunneling
 Tunneling across heavily doped p-n junctions
– Especially sidewall between drain & channel
when halo doping is used to increase Vt
 Increases junction leakage to significant levels
– Xj: sidewall junction depth
– Eg: bandgap voltage
– A, B: tech constants

CMOS VLSI Design
Gate-Induced Drain Leakage
 Occurs at overlap between gate and drain
– Most pronounced when drain is at VDD, gate is at
a negative voltage
– Thwarts efforts to reduce subthreshold leakage
using a negative gate voltage

CMOS VLSI Design
Temperature Sensitivity
 Increasing temperature
– Reduces mobility
– Reduces Vt
 ION decreases with temperature
 IOFF increases with temperature
Vgs
ds
I
increasing
temperature

CMOS VLSI Design
So What?
 So what if transistors are not ideal?
– They still behave like switches.
 But these effects matter for…
– Supply voltage choice
– Logical effort
– Quiescent power consumption
– Pass transistors
– Temperature of operation

CMOS VLSI Design
Parameter Variation
 Transistors have uncertainty in parameters
– Process: Leff, Vt, tox of nMOS and pMOS
– Vary around typical (T) values
 Fast (F)
– Leff: short
– Vt: low
– tox: thin
 Slow (S): opposite
 Not all parameters are independent
for nMOS and pMOS
nMOS
pMOS
fast
slow
slow
fast
TT
FF
SS
FS
SF

CMOS VLSI Design
Environmental Variation
 VDD and T also vary in time and space
 Fast:
– VDD: high
– T: low
Corner Voltage Temperature
F 1.98 0 C
T 1.8 70 C
S 1.62 125 C

CMOS VLSI Design
Process Corners
 Process corners describe worst case variations
– If a design works in all corners, it will probably
work for any variation.
 Describe corner with four letters (T, F, S)
– nMOS speed
– pMOS speed
– Voltage
– Temperature

CMOS VLSI Design
Important Corners
 Some critical simulation corners include
Purpose nMOS pMOS VDD Temp
Cycle time S S S S
Power F F F F
Subthreshold
leakage
F F F S

Non Ideal Transistor Theory- Mosfet second order effects

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