OLA Conf 2002 - OLA in SoC Design Environment - slides
- 1. Benefits of OLA Integration into Nano-Technology SoC Design Nano-Technology Environments Timothy J. Ehrler PS - OLA in SoC DE - tje - 1 PS - OLA in SoC DE - tje - 1 Senior Principal Methodology Engineer SoC Methodology Development Design Technology Group Philips Semiconductors 2002 OLA Developers Conference
- 2. Outline Introduction Technology Advancement Design Complexity Trends Traditional & Timing Closure Design Flow Open Library Architecture (OLA) OLA Based Design Flow PS - OLA in SoC DE - tje - 2 PS - OLA in SoC DE - tje - 2 Extended Integration Benefits Conclusion 2002 OLA Developers Conference
- 3. Introduction Technology is reaching to sub-100nm range sub-100nm increased density allows greater die functionality SoC evolving from multiple ASIC implementations increased demand on tools and methodologies Timing closure heavily impacts design cycle inconsistent/divergent timing algorithms PS - OLA in SoC DE - tje - 3 tool specific, non-standard/proprietary views PS - OLA in SoC DE - tje - 3 non-standard/proprietary expanding overhead of information exchange OLA positively impacts SoC design cycle consistent library-embedded algorithms, timing library-embedded elimination/reduction of information exchange 2002 OLA Developers Conference
- 4. Technology Advancement Increased gate density >= Moore’s Law 700 500 Feature Size (nm) 350 250 180 PS - OLA in SoC DE - tje - 4 PS - OLA in SoC DE - tje - 4 130 100 70 50 1993 1995 1997 1999 2001 2003 2005 2007 2002 OLA Developers Conference
- 5. Impact on Timing Decreased cell delay Increased input slew, output load dependency Increased IR drop susceptibility Increased interconnect concerns Coupling capacitance Signal noise dff PS - OLA in SoC DE - tje - 5 PS - OLA in SoC DE - tje - 5 q d Slew propagation ck RLC, not just RC 2002 OLA Developers Conference
- 6. Design Complexity Trends 1999 1.1M gates average 1.1M gates average 53% < 1M gates 53% < 1M gates 18% > 2M gates 18% > 2M gates 2000 30 1.6M gates average 1.6M gates average 2001 52% > 1M gates 52% > 1M gates 30% > 2M gates 20 30% > 2M gates 2000 PS - OLA in SoC DE - tje - 6 10 PS - OLA in SoC DE - tje - 6 2001 1999 2M+ gates average 2M+ gates average 0 1999 < 200k 200-500k >3 500k-1M 1M-2M 2M-3M 65% > 1M gates 65% > 1M gates 40% > 2M gates 40% > 2M gates 2000 20% > 3M gates 20% > 3M gates 2001 2002 OLA Developers Conference
- 7. IP Reuse Trend System solution, not functional design Extensive IP, design re-use re-use 250 200 150 PS - OLA in SoC DE - tje - 7 PS - OLA in SoC DE - tje - 7 100 IP Portfolio size IP Deliveries 50 0 1999 2000 2001 2002 OLA Developers Conference
- 8. SoC Implementation Over 10M gates Over 10M gates Less than 700ps clock slew Less than 700ps clock slew Sea of Gates Sea of Gates Cores (DSP, MicroP) Cores (DSP, MicroP) PS - OLA in SoC DE - tje - 8 PS - OLA in SoC DE - tje - 8 Memories Memories Analog Analog 2002 OLA Developers Conference
- 9. Design Flow Complexity Hierarchical design IP, complex cores, “glue” IP IP Program Extensive interconnect Memory Program inter-cell, intra-block inter-cell, intra-block Memory inter-block inter-block Program DSP Memory over-the-block over-the-block Program PS - OLA in SoC DE - tje - 9 PS - OLA in SoC DE - tje - 9 Memory Increased interconnect to cell delay ratio LOGIC LOGIC Complex parasitics Xtalk, noise, inductance Xtalk, 2002 OLA Developers Conference
- 10. Technology & Design Information Multiple sub-flows sub-flows RTL Development/Analysis RTL Development/Analysis multiple tools Technology Packages + Libraries + IP Technology Packages + Libraries + IP Sub Flow Sub-Flow Sub-Flow Sub Flow Sub-Flow Sub-Flow multiple algorithms Design Synthesis Design Synthesis Design Methodologies Design Methodologies Multiple libraries Sub-Flow Sub-Flow Sub-Flow Sub-Flow tool-specific tool-specific Logic/Timing Verification Logic/Timing Verification representations Sub-Flow Sub-Flow Sub-Flow Sub-Flow Sub-Flow Sub-Flow PS - OLA in SoC DE - tje - 10 PS - OLA in SoC DE - tje - 10 Information exchange Partitioning & Floor Planning Partitioning & Floor Planning Sub-Flow Sub-Flow Sub-Flow Sub-Flow Sub-Flow Sub-Flow inter-tool inter-tool Layout & Chip Finishing Layout & Chip Finishing representations Sub-Flow Sub-Flow Sub-Flow Sub-Flow interpretation 2002 OLA Developers Conference
- 11. Traditional Design Flow SPEC SDB Contents: Contents: RTL Simulation Hierarchy planning Architectural Analysis Partitioning & Behavioral RTL Automatic flatten for P&R Bus interfaces Ref Libs Floorplanning pre-route P/G, clock nets pre- pre-route IP Design Software code development Verilog or VHDL Area estimation RSP platform Feasibility: Performance, Area, Power, Clocking, Test management LDB Verilog or VHDL RTL description Contents: Contents: Block level synthesis Ref Libs Layout: Cell and Block P&R Create top level design (CPU, DSP, Cell & Block Timing driven extensions Library Functional Design analog, memory, HDLi templates, Models Verilog or VHDL I/O, schematics) DFT (scan insertion, MBIST, LDB JTAG, padring) PS - OLA in SoC DE - tje - 11 PS - OLA in SoC DE - tje - 11 Floorplanning Verilog or VHDL Contents: Structural Netlist Layout: Ref Libs Chip Assembly Insert core & pad fillers Contents: Symbolic verification Delay Calculation Design Finishing Bond diagram Logic & Timing Static Timing Analysis Library Gate-level Simulation Gate- Gate-level Verification Models Verilog or VHDL Power Estimation LDB GDS-II Verification Screener Lib Rules, Verification of specification Timing, Package Contents: DRC, LVS, Contents: DRC, LVS, To Factory Finish Plots, Extraction, Circuit Plots, Extraction, Circuit Simulation, Back-annotation Simulation, Back- Back-annotation and Mask Making & Timing Analysis & Timing Analysis Layout Test Program Generation 2002 OLA Developers Conference
- 12. Timing Closure Flow Static Timing Analysis (STA) based delay calculation SDF exchange Wireload Extraction Custom Wireloads Multiple closures Delay LIB RTL Calculation LIB (Custom WL) pre-route wireload pre-route LIB Delay Calculation (Tech. WL) Synthesis Optimization Scan Insertion Netlist SDF Slew Report FP custom wireload Slew Place & Route Static Design Database SDF Netlist Clock Tree Timing LIB Report Pad Ring Analysis post-rout extraction post-rout LIB Static Timing Analysis Parasitics Extraction SPEF PS - OLA in SoC DE - tje - 12 PS - OLA in SoC DE - tje - 12 Delay Functional Closure impediments LIB Calculation LIB Simulation (Parasitics) Formal calculation algorithms Slew Verification Netlist SDF Report Import LIB Library Static interconnect analysis Floor Timing LIB Planning Analysis Formal timing view consistency Verification LIB timing information exchange, interpretation 2002 OLA Developers Conference
- 13. OLA Concept Replaces traditional parsing, interpretation of library formats compiled library API access instead of textual data compiled library API access instead of textual data protect IP from user access and “hacking” protect IP from user access and “hacking” Provides single consistent, accurate method for library information access, calculation embedded algorithms for timing, power for all tools embedded algorithms for timing, power for all tools single “view” so no interpretation, annotation issues single “view” so no interpretation, annotation issues Synthesis PS - OLA in SoC DE - tje - 13 PS - OLA in SoC DE - tje - 13 Static Timing OLA Compliant Library Design for Test OLA Floorplanning (API) includes Timing and Place & Route Power Calculation Routines Semiconductor Sign-Off 2002 OLA Developers Conference
- 14. OLA Based Design Flow STA sub-flows replaced sub-flows RTL OLA LIB STA tool interfaces with OLA Synthesis Optimization Scan Insertion tool-specific calculation algorithms tool-specific Static Timing Netlist replaced by library embedded ones Analysis Functional Delay & Power Calculation System (OLA) delay calculation tool removed Simulation Formal SDF file eliminated Verification Design Database Floor Planning tools use OLA directly Wireload Custom Extraction timing consistent for all tools Wireloads PS - OLA in SoC DE - tje - 14 PS - OLA in SoC DE - tje - 14 Static Netlist Timing exchange medium unnecessary Analysis Place & Route Clock Tree resource overhead eliminated Pad Ring Parasitics SPEF Libraries, views reduced Extraction Static Netlist Timing consistent information from OLA Analysis Formal Verification annotation interpretation issues eliminated 2002 OLA Developers Conference
- 15. Extended Integration Benefits Power analysis, closure tool support more flexible, consistent, accurate power in conjunction with timing closure Function graph based tool support synthesis, optimization functional simulation PS - OLA in SoC DE - tje - 15 PS - OLA in SoC DE - tje - 15 formal verification Physical, back-end flow support back-end floor planning placement 2002 OLA Developers Conference
- 16. Library, IP Provider Benefit Major Reduction in Supported File Formats corresponding reduction of generation/verification requirements corresponding reduction of generation/verification requirements eliminate generation/translation tool requirements eliminate generation/translation tool requirements reduce generation & verification resources (h/w, personnel, time) reduce generation & verification resources (h/w, personnel, time) Design Process Tools Standard / Total OLA Total Format Proprietary Formats Replaceable/ Formats Reduction Formats Deleteable RTL Development/Analysis 5 3/0 3 2/0 2 33% Design Synthesis 7 4/6 10 4/1 6 40% Logic/Timing Verification 17 5/11 16 6/5 6 63% PS - OLA in SoC DE - tje - 16 PS - OLA in SoC DE - tje - 16 Partitioning & Floor Planning 11 3/9 12 5/0 8 33% Layout & Chip Finishing 21 4/15 19 6/2 12 37% Even Greater Savings for Multiple Libraries relative to OLA Replaceable/Deleteable numbers relative to OLA Replaceable/Deleteable numbers 16 libraries per technology ~= 16-fold reduction 16 libraries per technology ~= 16-fold reduction dependent on tool set choices and interfaces dependent on tool set choices and interfaces 2002 OLA Developers Conference
- 17. Conclusion OLA significantly improves timing closure consistent, accurate timing calculation timing closure through all design phases reduction, elimination of timing iteration cycles OLA improves interconnect analysis consistent coupling, signal integrity handling OLA provides instance specific timing PS - OLA in SoC DE - tje - 17 PS - OLA in SoC DE - tje - 17 PVT per instance for IR drop, thermal issues incremental timing “on-demand” “on-demand” SDF timing exchange eliminated generation, parsing, interpretation, annotation issues gone Consistent, Accurate Timing Closure Achieved !!! 2002 OLA Developers Conference
- 18. 2002 OLA Developers Conference Questions & Answers PS - OLA in SoC DE - tje - 18 PS - OLA in SoC DE - tje - 18
- 19. Biography Timothy received his BS in Computer and Information Science from The Ohio State Timothy received his BS in Computer and Information Science from The Ohio State University, College of Engineering, in 1977, taking a position as Test Systems Analyst with University, College of Engineering, in 1977, taking a position as Test Systems Analyst with Industrial Nucleonics Corporation, followed shortly thereafter by 14 years with Honeywell Industrial Nucleonics Corporation, followed shortly thereafter by 14 years with Honeywell Information Systems, now Groupe Bull, in developing and managing their proprietary HDL- Information Systems, now Groupe Bull, in developing and managing their proprietary HDL- based Design Language System for large mainframe computer system design. based Design Language System for large mainframe computer system design. Timothy joined VLSI Technology, Inc., in 1993 as a staff software engineer, heavily involved Timothy joined VLSI Technology, Inc., in 1993 as a staff software engineer, heavily involved in the development of the integrated ASIC design environment, from library view in the development of the integrated ASIC design environment, from library view generation to tool development, during which time he received a patent for timing model generation to tool development, during which time he received a patent for timing model analysis and optimization, with a related patent pending. He subsequently managed the analysis and optimization, with a related patent pending. He subsequently managed the ASIC tools development group for 4 years and, shortly after the acquisition of VLSI by ASIC tools development group for 4 years and, shortly after the acquisition of VLSI by Philips Semiconductors, became the manager of ASIC Technical Programs, and now holds Philips Semiconductors, became the manager of ASIC Technical Programs, and now holds his present position as Senior Principal Methodology Engineer. his present position as Senior Principal Methodology Engineer. PS - OLA in SoC DE - tje - 19 PS - OLA in SoC DE - tje - 19 Timothy has been a contributing member of both the Advanced Library Format (ALF) and Timothy has been a contributing member of both the Advanced Library Format (ALF) and Open Library Architecture (OLA) working groups since their inception. He led the migration Open Library Architecture (OLA) working groups since their inception. He led the migration effort within VLSI/Philips from a proprietary-based ASIC design environment to that based effort within VLSI/Philips from a proprietary-based ASIC design environment to that based on ALF, and is currently leading the effort within Philips Semiconductors in establishing on ALF, and is currently leading the effort within Philips Semiconductors in establishing the development and support of OLA libraries and EDA tools. the development and support of OLA libraries and EDA tools. 2002 OLA Developers Conference