OPTIMIZATION TECHNIQUES FOR SOURCE FOLLOWER BASED TRACK-AND-HOLD CIRCUIT FOR HIGH SPEED WIRELESS COMMUNICATION
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The document discusses the optimization techniques for track-and-hold (T&H) circuits used in high-speed wireless communication, focusing on their critical role in analog-to-digital converters. It examines various design schemes and circuit topologies to achieve high resolution, low power consumption, and low noise, highlighting the advantages and limitations of open-loop versus closed-loop architectures. The study presents findings on the performance characteristics, sampling networks, and the impact of device choices on T&H circuit efficiency.
![International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.1,
DOI : 10.5121/vlsic.2011.2105
OPTIMIZATION TECHNIQU
FOLLOWER BASED
HIGH SPEED WIRELESS
Manoj Kumar
1
Department of Electronics & Comm., Vidya College of Engg., Meerut (U.P)
2
Department of Electronics & Comm., NIT Hamirpur, Hamirpur (H.P)
ABSTRACT
Since the current demand for high-
need for track and hold amplifiers (T&H) operating at RF frequencies. A
circuit is the key element in any modern wideband data acquisition system. Applications like a cable
or a broad variety of different radio standards require high processing speeds with high resolution. The
track-and-hold (T&H) circuit is a fundamental block for analog
allows most dynamic errors of A/D converters to be reduced, especially those showing up when using
high frequency input signals. Having a wideband and precise acquisition system
today’s trend towards multi-standard flexible radios, with as much signal processing as possible in
digital domain. This work investigates effect of various design schemes and circuit topology for track
and-hold circuit to achieve acceptable linearly, high slew rate, low power consumption and low noise
KEYWORDS
Track and Hold Circuit, Low Power Consumption, Slew Rate,
Analog to Digital Converter
1. INTRODUCTION
Track and hold circuit is the fundam
and hold circuit is inserted in front of a comparator array of a flash A/D converter to keep
comparator’s input voltages constant while the comparators are settling their output voltage
levels. Track and hold architecture can be classified into two classes (fig.1): open
closed-loop architecture [1]-[5].
Figure 1a. Open-loop T/H
The open loop T/H circuit is suitable for high precision but not
T/H circuits proposed/implemented so far employ closed
8 bit accuracy. However closed loop architectures suffer from relatively lower sampling
frequency and higher power consumption as compa
ournal of VLSI design & Communication Systems (VLSICS) Vol.2, No.1, March
PTIMIZATION TECHNIQUES FOR SOURCE
FOLLOWER BASED TRACK-AND-HOLD CIRCUIT FOR
HIGH SPEED WIRELESS COMMUNICATION
Manoj Kumar1
and Gagnesh Kumar2
Electronics & Comm., Vidya College of Engg., Meerut (U.P)
Manoj.kr.nit@gmail.com
Electronics & Comm., NIT Hamirpur, Hamirpur (H.P)
Gagnesh@nitham.ac.in
-resolution and fast analog to digital converters (ADC) is driving the
need for track and hold amplifiers (T&H) operating at RF frequencies. A very fast and linear T&H
circuit is the key element in any modern wideband data acquisition system. Applications like a cable
or a broad variety of different radio standards require high processing speeds with high resolution. The
ircuit is a fundamental block for analog-to digital (A/D) converters. Its use
allows most dynamic errors of A/D converters to be reduced, especially those showing up when using
high frequency input signals. Having a wideband and precise acquisition system is a prerequisite for
standard flexible radios, with as much signal processing as possible in
This work investigates effect of various design schemes and circuit topology for track
eptable linearly, high slew rate, low power consumption and low noise
, Low Power Consumption, Slew Rate, Peak Power, Sampling S
Track and hold circuit is the fundamental block for analog to digital (A/D) converters. Track
and hold circuit is inserted in front of a comparator array of a flash A/D converter to keep
comparator’s input voltages constant while the comparators are settling their output voltage
k and hold architecture can be classified into two classes (fig.1): open
loop T/H Figure 1b. Closed-loop T/H
The open loop T/H circuit is suitable for high precision but not for high speed. Most CMOS
T/H circuits proposed/implemented so far employ closed-loop architecture to obtain better than
8 bit accuracy. However closed loop architectures suffer from relatively lower sampling
frequency and higher power consumption as compared to open-loop architecture [6]. Open
March 2011
45
ES FOR SOURCE
HOLD CIRCUIT FOR
COMMUNICATION
Electronics & Comm., Vidya College of Engg., Meerut (U.P)
Electronics & Comm., NIT Hamirpur, Hamirpur (H.P)
resolution and fast analog to digital converters (ADC) is driving the
very fast and linear T&H
circuit is the key element in any modern wideband data acquisition system. Applications like a cable-TV
or a broad variety of different radio standards require high processing speeds with high resolution. The
to digital (A/D) converters. Its use
allows most dynamic errors of A/D converters to be reduced, especially those showing up when using
is a prerequisite for
standard flexible radios, with as much signal processing as possible in
This work investigates effect of various design schemes and circuit topology for track-
eptable linearly, high slew rate, low power consumption and low noise.
Switch, Flash
ental block for analog to digital (A/D) converters. Track
and hold circuit is inserted in front of a comparator array of a flash A/D converter to keep
comparator’s input voltages constant while the comparators are settling their output voltage
k and hold architecture can be classified into two classes (fig.1): open-loop and
loop T/H
for high speed. Most CMOS
loop architecture to obtain better than
8 bit accuracy. However closed loop architectures suffer from relatively lower sampling
loop architecture [6]. Open-](https://image.slidesharecdn.com/2111vlsics05-180517115933/85/OPTIMIZATION-TECHNIQUES-FOR-SOURCE-FOLLOWER-BASED-TRACK-AND-HOLD-CIRCUIT-FOR-HIGH-SPEED-WIRELESS-COMMUNICATION-1-320.jpg)
![International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.1,
loop architectures tend to consume lower power and work at high sampling frequencies than
closed-loop ones. Open-loop architectures have been used
Source-follower-based T/H circuit has be
speed and power consumption.This paper investigates effect of various design schemes and
circuit topology for track-and-hold circuit to achieve acceptable linearly, high slew rate, low
power consumption and low noise. Superior speed &
makes it promising candidate for the purpose of this work.
2. SAMPLING SWITCHES FO
The sampling network consists of a sampling switch (M
value of sampled signal during the hold mode. During the tracking phase, the combination of
the switch and the capacitor forms a first
maximum achievable sampling frequency. The speed of sampling netwo
serious limitation in this work because as will be seen the chosen operating frequency is far less
than the time-constant of the switch network and is basically limited by other parts of the
circuit [15].
The noise contribution due to the sampling network is dependent on the sampling capacitance
value and the width of the switching transistor. In addition to the noise added by the switch, the
non-linearity due to the signal-
linearity of the T/H circuit.
2.1. Single MOS Switch
The maximum output voltage that an NMOS transistor can deliver is approximately equal to
Vdd-Vth.
Figure 2. Single MOS sampling switch
The on-resistance of a long-channel MOS device operating in the linear (triode) regions is given
by:
From the above expression it is clear that the resistance of NMOS
approaches infinity when Vin approaches Vdd
transistor [10].
2.2. Transmission-Gate Switch
To circumvent the above problem with a varying switch resistance the benefit of NMOS for
low input voltages and the PMOS for
connecting them in parallel and thereby forming a transmission gate
ournal of VLSI design & Communication Systems (VLSICS) Vol.2, No.1, March 2011
loop architectures tend to consume lower power and work at high sampling frequencies than
architectures have been used in high-speed ADCs [3][4].
based T/H circuit has been optimized with respect to linearity, noise, and
This paper investigates effect of various design schemes and
hold circuit to achieve acceptable linearly, high slew rate, low
nd low noise. Superior speed & acceptable linearity of source
makes it promising candidate for the purpose of this work.
SAMPLING SWITCHES FOR T/H
The sampling network consists of a sampling switch (Msw) and a hold capacitor (Cs) to store the
value of sampled signal during the hold mode. During the tracking phase, the combination of
the switch and the capacitor forms a first-order RC network, the time-constant of which sets the
maximum achievable sampling frequency. The speed of sampling network appears not to be a
serious limitation in this work because as will be seen the chosen operating frequency is far less
constant of the switch network and is basically limited by other parts of the
e to the sampling network is dependent on the sampling capacitance
value and the width of the switching transistor. In addition to the noise added by the switch, the
-dependent behaviour of the switch can degrade the overall
The maximum output voltage that an NMOS transistor can deliver is approximately equal to
Single MOS sampling switch
channel MOS device operating in the linear (triode) regions is given
From the above expression it is clear that the resistance of NMOS switch is non-linear that is
pproaches infinity when Vin approaches Vdd-Vth,which is the upper limit of the NMOS
Gate Switch
To circumvent the above problem with a varying switch resistance the benefit of NMOS for
low input voltages and the PMOS for high input voltages can be Utilized.it is done simply by
connecting them in parallel and thereby forming a transmission gate.
March 2011
46
loop architectures tend to consume lower power and work at high sampling frequencies than
speed ADCs [3][4].
en optimized with respect to linearity, noise, and
This paper investigates effect of various design schemes and
hold circuit to achieve acceptable linearly, high slew rate, low
acceptable linearity of source-followers
) to store the
value of sampled signal during the hold mode. During the tracking phase, the combination of
constant of which sets the
rk appears not to be a
serious limitation in this work because as will be seen the chosen operating frequency is far less
constant of the switch network and is basically limited by other parts of the
e to the sampling network is dependent on the sampling capacitance
value and the width of the switching transistor. In addition to the noise added by the switch, the
dependent behaviour of the switch can degrade the overall
The maximum output voltage that an NMOS transistor can deliver is approximately equal to
channel MOS device operating in the linear (triode) regions is given
linear that is
Vth,which is the upper limit of the NMOS
To circumvent the above problem with a varying switch resistance the benefit of NMOS for
high input voltages can be Utilized.it is done simply by](https://image.slidesharecdn.com/2111vlsics05-180517115933/85/OPTIMIZATION-TECHNIQUES-FOR-SOURCE-FOLLOWER-BASED-TRACK-AND-HOLD-CIRCUIT-FOR-HIGH-SPEED-WIRELESS-COMMUNICATION-2-320.jpg)
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Figure 3. Transmission gate sampling switch
NMOS transistor shows the non
transistor works poorly for high voltages. A PMOS transistor on the other hand , is known to
work poorly for low voltages and rather for high voltages.
The transmission-gate-switch (
the solution to the problem faced by single NMOS and PMOS switches. As seen in figure, the
resistance for the transmission
switches can be wise choice to get acceptable li
Figure 5.
3. CONVENTIONAL T/H USING SOURCE FOLLO
Source follower was used in this work to drive the load c
devices in the source-follower contribute to the noise in both the track and hold modes of
ournal of VLSI design & Communication Systems (VLSICS) Vol.2, No.1, March 2011
Transmission gate sampling switch Figure 4. On-resistance of the
transmission gate
the non-linear characterisitcs for high voltages. This is why NMOS
transistor works poorly for high voltages. A PMOS transistor on the other hand , is known to
work poorly for low voltages and rather for high voltages.
NMOS-and-PMOS transistor connected in parallel
the solution to the problem faced by single NMOS and PMOS switches. As seen in figure, the
resistance for the transmission-gate-switch is much linear that is why transmission
choice to get acceptable linearty and large output gain [18].
Resistance magnitude of sampling switches
H USING SOURCE FOLLOWER
Source follower was used in this work to drive the load capacitance of the T/H stage. The active
follower contribute to the noise in both the track and hold modes of
March 2011
47
resistance of the
linear characterisitcs for high voltages. This is why NMOS
transistor works poorly for high voltages. A PMOS transistor on the other hand , is known to
PMOS transistor connected in parallel ) might be
the solution to the problem faced by single NMOS and PMOS switches. As seen in figure, the
switch is much linear that is why transmission-gate-
apacitance of the T/H stage. The active
follower contribute to the noise in both the track and hold modes of](https://image.slidesharecdn.com/2111vlsics05-180517115933/85/OPTIMIZATION-TECHNIQUES-FOR-SOURCE-FOLLOWER-BASED-TRACK-AND-HOLD-CIRCUIT-FOR-HIGH-SPEED-WIRELESS-COMMUNICATION-3-320.jpg)
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48
operation. The noise of these devices mainly due consists of channel thermal noise and gate
flicker noise.
3.1. Analysis of T/H Circuit Using NMOS Sampling Switch
A conventional source follower T/H circuit basically consists of input, output buffers, a switch
and a sampling capacitor. An output buffer is usually used to charge and discharge the input
capacitances of following comparators.
A T/H circuit has two operation phases named “track phase” and “hold phase”. During a track
phase the switch is shorted and Vout becomes equal to Vin. On the other hand, during a hold
phase the switch is opened and the T/H circuit keeps its output voltage equal to the value at end
of track phase. A required hold time of a T/H circuit is usually decided by a settling time of the
following comparators since the comparators must settle their output voltage during a hold
time [9].
Figure 6. Single ended conventional T/H
Table 1. Design specification of T/H
Power supply voltage 1.8 v
Maximum input signal
frequency
500 MHz
Sampling frequency 1GHz
Maximum output voltage
swing (Ain)
1 Vp-p
Resolution 6 bit
Load capacitance (CL) 10pf
Input offset 0.8 v
CMOS technology 0.18µm
An input voltage represented by
ܸ ൌ ܣ sinሺ߱ ߮ሻ (2)
Where Ain is equal to the maximum input voltage given by the specifications and ωin is set to 2π
( fs/2 ). fs means its sampling frequency.
3.2. Analytical Modeling of Conventional T/H Circuit
Figure 7. Small signal model of conventional T/H](https://image.slidesharecdn.com/2111vlsics05-180517115933/85/OPTIMIZATION-TECHNIQUES-FOR-SOURCE-FOLLOWER-BASED-TRACK-AND-HOLD-CIRCUIT-FOR-HIGH-SPEED-WIRELESS-COMMUNICATION-4-320.jpg)
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53
3.5.1 Noise Analysis of fully-differential T/H circuit
Table 8. Noise results of fully differential
T/H circuit
Total output noise
voltage
2.981e-019 Sq
V/Hz
= 546.01522 p
V/Rt(Hz)
Transfer function
value (Vout/Vin)
0
Equivalent input
noise at Vin
0
Total equivalent
input noise voltage
0 V
Figure 18. O/P Noise of fully-differential T/H
3.5. Analysis of Two-Stage T/H using Conventional T/H Circuit
In two-stage T/H circuit, two conventional T/H circuits are connected in cascade. The output of
the first T/H serves as the input to the next T/H. If the input voltage of a T/H circuit is kept
constant during its track phase, only one of charging or discharging is occurred in a track phase.
In this case the output voltage of the T/H circuit settles monotonously into the constant voltage
from the beginning of the track phase and its hold time must be as long as possible. This
reduction of the tracking time results in a low power consumption. In order to apply such a
constant voltage to the T/H circuit an additional small T/H circuit is inserted in front of the
original T/H circuit as shown in Figure 19. Inverting and non-inverting clocks are applied to the
two switches, Msw0 and Msw1, respectively so that the two T/H circuits act reciprocally.
Figure 19. Two stage T/H circuit Figure 20. Output waveform of two stage T/H
circuit
When the second T/H circuit is in a track phase the first T/H circuit is always in a hold phase
whose output voltage is constant. The first T/H circuit also charges and discharges its load
capacitance during a track phase, however, it can operate very fast because its load capacitance
is much smaller than that of the conventional T/H circuit. The first T/H circuit consumes very
low power when the first T/H circuit and the conventional one have the same operation speed.
The output voltage of the first stage is applied to the second T/H circuit. When the second T/H
circuit is in the track phase, its input voltage is always constant because the first T/H circuit is
already in the hold phase. Therefore, its output voltage approaches to the final value directly and
it’s settling time decreases drastically [8].](https://image.slidesharecdn.com/2111vlsics05-180517115933/85/OPTIMIZATION-TECHNIQUES-FOR-SOURCE-FOLLOWER-BASED-TRACK-AND-HOLD-CIRCUIT-FOR-HIGH-SPEED-WIRELESS-COMMUNICATION-9-320.jpg)
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Thus the maximum occurs at zero crossing of I/P sinusoidal. If
of the input buffer the output wa
rate of change of the input sinusoidal at its zero crossing & hence source follower slews [7].
There is a specific frequency fM
source follower begins to show distortion due to slew
Figure 23.
When the step voltage whose amplitude is larger than (Vgs
of source follower T/H circuit, M
load capacitor is discharged by a constant current I
The output voltage during the slewing can be represented by
Where Vgs1 is the gate-to-source bias voltage of M
Msw1 is adequately small, this slewing continues as
3.7 COMPARISON OF POWER
Figure 24. Comparison of power consumption
Figure 24. Shows that average power consumed by two stage Track
0
50
100
150
200
76.94 78.3389.08
ournal of VLSI design & Communication Systems (VLSICS) Vol.2, No.1, March 2011
Thus the maximum occurs at zero crossing of I/P sinusoidal. If exceeds the slew rate
of the input buffer the output waveform will be distorted. Output cannot keep up with this large
rate of change of the input sinusoidal at its zero crossing & hence source follower slews [7].
M called the full-power bandwidth at which output voltage of the
source follower begins to show distortion due to slew-rate limitation
Figure 23. Single stage of source follower T/H
When the step voltage whose amplitude is larger than (Vgs – VT) is applied to the single stage
lower T/H circuit, M1 goes into the cut-off region at t = t0. When M1 is cut off, its
load capacitor is discharged by a constant current IM2. The slew rate is limited to IM2/C
The output voltage during the slewing can be represented by
source bias voltage of M1 On the assumption that an on-resistance of
is adequately small, this slewing continues as
COMPARISON OF POWER
omparison of power consumption
that average power consumed by two stage Track-and-Hold circuit is minimum.
78.33 93.64
162
64.3
90.91 103.5
182
69.8
Average
Power(mw)
March 2011
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exceeds the slew rate
Output cannot keep up with this large
rate of change of the input sinusoidal at its zero crossing & hence source follower slews [7].
power bandwidth at which output voltage of the
) is applied to the single stage
. When M1 is cut off, its
/C1.
resistance of
Hold circuit is minimum.](https://image.slidesharecdn.com/2111vlsics05-180517115933/85/OPTIMIZATION-TECHNIQUES-FOR-SOURCE-FOLLOWER-BASED-TRACK-AND-HOLD-CIRCUIT-FOR-HIGH-SPEED-WIRELESS-COMMUNICATION-11-320.jpg)
![International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.1, March 2011
57
3. CONCLUSIONS
It is found that the on-resistance of transmission-gate-switch (NMOS and MOS-transistor
connected in parallel) is much more linear. Later on, NMOS switches are replaced with
transmission-gate-switch.
Two stage Track-and-Hold circuit shows 16.42% decrease in power consumption as compared
to conventional Track-and-Hold circuit. Further, track time of two-stage T/H circuit is found to
be .16(ns) which is minimum among all Track-and-Hold circuits. Hence two-stage structure is
fastest among all designs. Fully differential Track-and-Hold circuit shows the highest slew rate
(181 mv/ns) while two-stage T/H shows minimum slew (40 mv/ns). There is an 8.90% increase
in Vout of two stage Track-and-hold circuit as compared to conventional Track-and-Hold circuit.
Two-stage T/H circuit shows 67.19% reduction in output noise voltage as compared to
conventional Track-and-Hold circuit. Two Stage T/H Circuit based on source follower buffers
mitigates the problem of power consumption, large track time and noise but at the cost of small
value of slew rate. A unity-gain buffer is capable to achieve high slew rates in both positive and
negative directions. By sensing the drain current of the common-drain device in an NMOS
source follower, the extent of slewing could be achieved. So the future work of this dissertation
would be implementation of high slew rate Track-and-Hold circuit by using an enhanced slew
rate source follower buffers [7].
ACKNOWLEDGEMENTS
I express my heart-felt gratitude to Mr. Gagnesh Kumar, Assistant Professor, E&C
Department, NIT Hamirpur for his invaluable guidance and support throughout this work. His
encouragement was very helpful for me to go ahead in this project.
I acknowledge with gratitude the technical and financial support from DIT, Ministry of
Communications & Information Technology, Govt. of India, New Delhi, through VLSI SMDP-
II Project at NIT Hamirpur HP.
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OPTIMIZATION TECHNIQUES FOR SOURCE FOLLOWER BASED TRACK-AND-HOLD CIRCUIT FOR HIGH SPEED WIRELESS COMMUNICATION
- 1. International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.1, DOI : 10.5121/vlsic.2011.2105 OPTIMIZATION TECHNIQU FOLLOWER BASED HIGH SPEED WIRELESS Manoj Kumar 1 Department of Electronics & Comm., Vidya College of Engg., Meerut (U.P) 2 Department of Electronics & Comm., NIT Hamirpur, Hamirpur (H.P) ABSTRACT Since the current demand for high- need for track and hold amplifiers (T&H) operating at RF frequencies. A circuit is the key element in any modern wideband data acquisition system. Applications like a cable or a broad variety of different radio standards require high processing speeds with high resolution. The track-and-hold (T&H) circuit is a fundamental block for analog allows most dynamic errors of A/D converters to be reduced, especially those showing up when using high frequency input signals. Having a wideband and precise acquisition system today’s trend towards multi-standard flexible radios, with as much signal processing as possible in digital domain. This work investigates effect of various design schemes and circuit topology for track and-hold circuit to achieve acceptable linearly, high slew rate, low power consumption and low noise KEYWORDS Track and Hold Circuit, Low Power Consumption, Slew Rate, Analog to Digital Converter 1. INTRODUCTION Track and hold circuit is the fundam and hold circuit is inserted in front of a comparator array of a flash A/D converter to keep comparator’s input voltages constant while the comparators are settling their output voltage levels. Track and hold architecture can be classified into two classes (fig.1): open closed-loop architecture [1]-[5]. Figure 1a. Open-loop T/H The open loop T/H circuit is suitable for high precision but not T/H circuits proposed/implemented so far employ closed 8 bit accuracy. However closed loop architectures suffer from relatively lower sampling frequency and higher power consumption as compa ournal of VLSI design & Communication Systems (VLSICS) Vol.2, No.1, March PTIMIZATION TECHNIQUES FOR SOURCE FOLLOWER BASED TRACK-AND-HOLD CIRCUIT FOR HIGH SPEED WIRELESS COMMUNICATION Manoj Kumar1 and Gagnesh Kumar2 Electronics & Comm., Vidya College of Engg., Meerut (U.P) Manoj.kr.nit@gmail.com Electronics & Comm., NIT Hamirpur, Hamirpur (H.P) Gagnesh@nitham.ac.in -resolution and fast analog to digital converters (ADC) is driving the need for track and hold amplifiers (T&H) operating at RF frequencies. A very fast and linear T&H circuit is the key element in any modern wideband data acquisition system. Applications like a cable or a broad variety of different radio standards require high processing speeds with high resolution. The ircuit is a fundamental block for analog-to digital (A/D) converters. Its use allows most dynamic errors of A/D converters to be reduced, especially those showing up when using high frequency input signals. Having a wideband and precise acquisition system is a prerequisite for standard flexible radios, with as much signal processing as possible in This work investigates effect of various design schemes and circuit topology for track eptable linearly, high slew rate, low power consumption and low noise , Low Power Consumption, Slew Rate, Peak Power, Sampling S Track and hold circuit is the fundamental block for analog to digital (A/D) converters. Track and hold circuit is inserted in front of a comparator array of a flash A/D converter to keep comparator’s input voltages constant while the comparators are settling their output voltage k and hold architecture can be classified into two classes (fig.1): open loop T/H Figure 1b. Closed-loop T/H The open loop T/H circuit is suitable for high precision but not for high speed. Most CMOS T/H circuits proposed/implemented so far employ closed-loop architecture to obtain better than 8 bit accuracy. However closed loop architectures suffer from relatively lower sampling frequency and higher power consumption as compared to open-loop architecture [6]. Open March 2011 45 ES FOR SOURCE HOLD CIRCUIT FOR COMMUNICATION Electronics & Comm., Vidya College of Engg., Meerut (U.P) Electronics & Comm., NIT Hamirpur, Hamirpur (H.P) resolution and fast analog to digital converters (ADC) is driving the very fast and linear T&H circuit is the key element in any modern wideband data acquisition system. Applications like a cable-TV or a broad variety of different radio standards require high processing speeds with high resolution. The to digital (A/D) converters. Its use allows most dynamic errors of A/D converters to be reduced, especially those showing up when using is a prerequisite for standard flexible radios, with as much signal processing as possible in This work investigates effect of various design schemes and circuit topology for track- eptable linearly, high slew rate, low power consumption and low noise. Switch, Flash ental block for analog to digital (A/D) converters. Track and hold circuit is inserted in front of a comparator array of a flash A/D converter to keep comparator’s input voltages constant while the comparators are settling their output voltage k and hold architecture can be classified into two classes (fig.1): open-loop and loop T/H for high speed. Most CMOS loop architecture to obtain better than 8 bit accuracy. However closed loop architectures suffer from relatively lower sampling loop architecture [6]. Open-
- 2. International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.1, loop architectures tend to consume lower power and work at high sampling frequencies than closed-loop ones. Open-loop architectures have been used Source-follower-based T/H circuit has be speed and power consumption.This paper investigates effect of various design schemes and circuit topology for track-and-hold circuit to achieve acceptable linearly, high slew rate, low power consumption and low noise. Superior speed & makes it promising candidate for the purpose of this work. 2. SAMPLING SWITCHES FO The sampling network consists of a sampling switch (M value of sampled signal during the hold mode. During the tracking phase, the combination of the switch and the capacitor forms a first maximum achievable sampling frequency. The speed of sampling netwo serious limitation in this work because as will be seen the chosen operating frequency is far less than the time-constant of the switch network and is basically limited by other parts of the circuit [15]. The noise contribution due to the sampling network is dependent on the sampling capacitance value and the width of the switching transistor. In addition to the noise added by the switch, the non-linearity due to the signal- linearity of the T/H circuit. 2.1. Single MOS Switch The maximum output voltage that an NMOS transistor can deliver is approximately equal to Vdd-Vth. Figure 2. Single MOS sampling switch The on-resistance of a long-channel MOS device operating in the linear (triode) regions is given by: From the above expression it is clear that the resistance of NMOS approaches infinity when Vin approaches Vdd transistor [10]. 2.2. Transmission-Gate Switch To circumvent the above problem with a varying switch resistance the benefit of NMOS for low input voltages and the PMOS for connecting them in parallel and thereby forming a transmission gate ournal of VLSI design & Communication Systems (VLSICS) Vol.2, No.1, March 2011 loop architectures tend to consume lower power and work at high sampling frequencies than architectures have been used in high-speed ADCs [3][4]. based T/H circuit has been optimized with respect to linearity, noise, and This paper investigates effect of various design schemes and hold circuit to achieve acceptable linearly, high slew rate, low nd low noise. Superior speed & acceptable linearity of source makes it promising candidate for the purpose of this work. SAMPLING SWITCHES FOR T/H The sampling network consists of a sampling switch (Msw) and a hold capacitor (Cs) to store the value of sampled signal during the hold mode. During the tracking phase, the combination of the switch and the capacitor forms a first-order RC network, the time-constant of which sets the maximum achievable sampling frequency. The speed of sampling network appears not to be a serious limitation in this work because as will be seen the chosen operating frequency is far less constant of the switch network and is basically limited by other parts of the e to the sampling network is dependent on the sampling capacitance value and the width of the switching transistor. In addition to the noise added by the switch, the -dependent behaviour of the switch can degrade the overall The maximum output voltage that an NMOS transistor can deliver is approximately equal to Single MOS sampling switch channel MOS device operating in the linear (triode) regions is given From the above expression it is clear that the resistance of NMOS switch is non-linear that is pproaches infinity when Vin approaches Vdd-Vth,which is the upper limit of the NMOS Gate Switch To circumvent the above problem with a varying switch resistance the benefit of NMOS for low input voltages and the PMOS for high input voltages can be Utilized.it is done simply by connecting them in parallel and thereby forming a transmission gate. March 2011 46 loop architectures tend to consume lower power and work at high sampling frequencies than speed ADCs [3][4]. en optimized with respect to linearity, noise, and This paper investigates effect of various design schemes and hold circuit to achieve acceptable linearly, high slew rate, low acceptable linearity of source-followers ) to store the value of sampled signal during the hold mode. During the tracking phase, the combination of constant of which sets the rk appears not to be a serious limitation in this work because as will be seen the chosen operating frequency is far less constant of the switch network and is basically limited by other parts of the e to the sampling network is dependent on the sampling capacitance value and the width of the switching transistor. In addition to the noise added by the switch, the dependent behaviour of the switch can degrade the overall The maximum output voltage that an NMOS transistor can deliver is approximately equal to channel MOS device operating in the linear (triode) regions is given linear that is Vth,which is the upper limit of the NMOS To circumvent the above problem with a varying switch resistance the benefit of NMOS for high input voltages can be Utilized.it is done simply by
- 3. International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.1, Figure 3. Transmission gate sampling switch NMOS transistor shows the non transistor works poorly for high voltages. A PMOS transistor on the other hand , is known to work poorly for low voltages and rather for high voltages. The transmission-gate-switch ( the solution to the problem faced by single NMOS and PMOS switches. As seen in figure, the resistance for the transmission switches can be wise choice to get acceptable li Figure 5. 3. CONVENTIONAL T/H USING SOURCE FOLLO Source follower was used in this work to drive the load c devices in the source-follower contribute to the noise in both the track and hold modes of ournal of VLSI design & Communication Systems (VLSICS) Vol.2, No.1, March 2011 Transmission gate sampling switch Figure 4. On-resistance of the transmission gate the non-linear characterisitcs for high voltages. This is why NMOS transistor works poorly for high voltages. A PMOS transistor on the other hand , is known to work poorly for low voltages and rather for high voltages. NMOS-and-PMOS transistor connected in parallel the solution to the problem faced by single NMOS and PMOS switches. As seen in figure, the resistance for the transmission-gate-switch is much linear that is why transmission choice to get acceptable linearty and large output gain [18]. Resistance magnitude of sampling switches H USING SOURCE FOLLOWER Source follower was used in this work to drive the load capacitance of the T/H stage. The active follower contribute to the noise in both the track and hold modes of March 2011 47 resistance of the linear characterisitcs for high voltages. This is why NMOS transistor works poorly for high voltages. A PMOS transistor on the other hand , is known to PMOS transistor connected in parallel ) might be the solution to the problem faced by single NMOS and PMOS switches. As seen in figure, the switch is much linear that is why transmission-gate- apacitance of the T/H stage. The active follower contribute to the noise in both the track and hold modes of
- 4. International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.1, March 2011 48 operation. The noise of these devices mainly due consists of channel thermal noise and gate flicker noise. 3.1. Analysis of T/H Circuit Using NMOS Sampling Switch A conventional source follower T/H circuit basically consists of input, output buffers, a switch and a sampling capacitor. An output buffer is usually used to charge and discharge the input capacitances of following comparators. A T/H circuit has two operation phases named “track phase” and “hold phase”. During a track phase the switch is shorted and Vout becomes equal to Vin. On the other hand, during a hold phase the switch is opened and the T/H circuit keeps its output voltage equal to the value at end of track phase. A required hold time of a T/H circuit is usually decided by a settling time of the following comparators since the comparators must settle their output voltage during a hold time [9]. Figure 6. Single ended conventional T/H Table 1. Design specification of T/H Power supply voltage 1.8 v Maximum input signal frequency 500 MHz Sampling frequency 1GHz Maximum output voltage swing (Ain) 1 Vp-p Resolution 6 bit Load capacitance (CL) 10pf Input offset 0.8 v CMOS technology 0.18µm An input voltage represented by ܸ ൌ ܣ sinሺ߱ ߮ሻ (2) Where Ain is equal to the maximum input voltage given by the specifications and ωin is set to 2π ( fs/2 ). fs means its sampling frequency. 3.2. Analytical Modeling of Conventional T/H Circuit Figure 7. Small signal model of conventional T/H
- 5. International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.1, March 2011 49 A Transfer functions from Vin to V1 , and from V1 to Vout is represented by ܶଵሺݏሻ ൌ ݒଵ ݒ ൌ 1 1 ܥݏଵ ൬ 1 ݃ଵ ݎ௦௪ଵ൰ ൌ 1 1 ߬ݏଵ ሺ3ሻ ܶଶሺݏሻ ൌ ݒ௨௧ ݒଵ ൌ 1 1 ܥݏ ൬ 1 ݃ଶ ൰ ൌ 1 1 ߬ݏଶ ሺ4ሻ Respectively, where ߬ଵ and ߬ଶ is time constant which is defined by ߬ଵ ൌ ܥଵ ቀ ଵ భ ݎ௦௪ଵቁ , ߬ଶ ൌ ಽ మ ሺ5ሻ ݃మ ൌ ܥ ߬ଶ , 1 ݃ଵ ൌ ඥߙ ඥߙ ඥߚ ߬ଵ ܥଵ , rୱ୵ଵ ൌ ඥβ୬ √α୬ ඥβ୬ τଵ Cଵ ሺ6ሻ Whereߙ, ߚ is defined as follows ߙ ൌ ൫ೞି൯భ ଶ , ߚ ൌ ೞೢభ మ ೞ ఓ൫ೞି൯ ଵ ೞೢభ ሺ7ሻ On the assumption that an acceptable gain error at the input buffer of the T/H circuit is e1 an optimum ߬ଵ must satisfy |Tଵሺjω୫ୟ୶ሻ| ൌ 1 ඥ1 ω୫ୟ୶ ଶ τଵ2 ൌ 1 െ eଵ ሺ8ሻ and v୭୳୲ሺtሻ ൌ Lିଵ 1 1 sτଶ . Vଵሺsሻ൨ ሺ9ሻ Where V1(s) is the output of the input buffer of conventional T/H circuit. Table 2. Hspice smulation of conventional T/H circuit Vout 1.46 v Average power consumption 76.94 mw peak power over a cycle 89.08 mw Slew rate 89.64 mv/ns Track time 0.92 ns Hold time 0.76 ns Figure 8. Output waveform for conventional T/H
- 6. International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.1, March 2011 50 3.2.1 Noise Analysis of Conventional T/H Circuit Table 2. Noise results of conventional T/H Total output noise voltage 6.945e-01 Sq V/Hz=833.37p V/Rt(Hz) Transfer function value ( Vout/Vin ) 1.64882n Equivalent input noise at Vin 505.43604m Total equivalent input noise voltage 1.14265K V Figure 9. Output noise of conventional T/H 3.3. Analysis of T/H Circuit using Transmission-Gate Sampling Switch Here NMOS sampling switch is replaced with Transmission-gate sampling switch. As discussed earlier that On-resistance of Transmission-gate shows the linear characteristics hence linearity in output waveform is expected this is confirmed by the HSPICE simulation result. It improves the linearity but at the cost of area overhead. We require one more clock to use transmission- gate sampling switch Figure 10. Conventional T/H using Transmission-gate sampling switch Table 3. Hspice simulation results for conventional Track-and-Hold using Transmission-Gate Vout 1.57v Average power consumption 78.33 mw Peak power over a cycle 90.91 mw Slew rate 110.48 mv/ns Track time 0.92 ns Hold time 0.81 ns Figure 11. Output waveform for T/H using Transmission-gate sampling switch
- 7. International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.1, March 2011 51 From the output waveform it is clear that Vout is linear in behaviour. 3.3.1 Noise Analysis of Conventional T/H Circuit using Transmission-Gate Table 4. Noise results of conventional T/H using Transmission-Gate Total output noise voltage 4.473e-019 Sq V/Hz = 668.83807p V/Rt(Hz) Transfer function value (Vout/Vin) 1.06742n Equivalent input noise at Vin 626.59340m Total equivalent input noise voltage 1.43876K V Figure 12. Output noise of conventional T/H using Transmission-Gate 3.4. Analysis of Pseudo-differential T/H circuit The T/H circuit is implemented in a pseudo-differential fashion to suppress even–order nonlinearities as well as offset and common-mode noise. The biasing branch of the source- follower is, however, shared between the two half circuits to cancel the noise contribution of biasing devices. Figure 13. Pseudo-deferential T/H Figure 14. Output waveform for pseudo- deferential T/H Table 5. Hspice Simulation Result of Pseudo-Differential T/H Vout 1.50 v Average power consumption 93.64 mw Peak power over a cycle 103.5 mw Slew rate 135mv/ns Track time 0.88 ns Hold time 0.77 ns
- 8. International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.1, March 2011 52 3.4.1 Noise Analysis of Pseudo-differential T/H circuit Table 6. Noise results of conventional T/H using Transmission-Gate Total output noise voltage 5.674e-019 Sq V/Hz =753.29254p V/Rt(Hz) Transfer function value (Vout/Vin) 1.04183n Equivalent input noise at Vin 723.05050m Total equivalent input noise voltage 1.63118K V Figure 15. Output noise of pseudo-differential T/H 3.5. Analysis of fully-differential T/H circuit Figure 16. shows that input and output buffers of conventional Track-and-Hold circuit are modified in differential manner so that common mode noise could be suppressed. This architecture suppress the noise upto 60-70% as compared to conventional one but at the cost of power consumption and area overhead. Figure 16. Fully-deferential T/H Figure 17. Output waveform of fully- deferential T/H Table 7. Hspice simulation results of fully-differential T/H Vout 1.56 v Average power consumption 162 mw Peak power over a cycle 182 mw Slew rate 181 mv/ns Track time 0.92 ns Hold time 0.81 ns
- 9. International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.1, March 2011 53 3.5.1 Noise Analysis of fully-differential T/H circuit Table 8. Noise results of fully differential T/H circuit Total output noise voltage 2.981e-019 Sq V/Hz = 546.01522 p V/Rt(Hz) Transfer function value (Vout/Vin) 0 Equivalent input noise at Vin 0 Total equivalent input noise voltage 0 V Figure 18. O/P Noise of fully-differential T/H 3.5. Analysis of Two-Stage T/H using Conventional T/H Circuit In two-stage T/H circuit, two conventional T/H circuits are connected in cascade. The output of the first T/H serves as the input to the next T/H. If the input voltage of a T/H circuit is kept constant during its track phase, only one of charging or discharging is occurred in a track phase. In this case the output voltage of the T/H circuit settles monotonously into the constant voltage from the beginning of the track phase and its hold time must be as long as possible. This reduction of the tracking time results in a low power consumption. In order to apply such a constant voltage to the T/H circuit an additional small T/H circuit is inserted in front of the original T/H circuit as shown in Figure 19. Inverting and non-inverting clocks are applied to the two switches, Msw0 and Msw1, respectively so that the two T/H circuits act reciprocally. Figure 19. Two stage T/H circuit Figure 20. Output waveform of two stage T/H circuit When the second T/H circuit is in a track phase the first T/H circuit is always in a hold phase whose output voltage is constant. The first T/H circuit also charges and discharges its load capacitance during a track phase, however, it can operate very fast because its load capacitance is much smaller than that of the conventional T/H circuit. The first T/H circuit consumes very low power when the first T/H circuit and the conventional one have the same operation speed. The output voltage of the first stage is applied to the second T/H circuit. When the second T/H circuit is in the track phase, its input voltage is always constant because the first T/H circuit is already in the hold phase. Therefore, its output voltage approaches to the final value directly and it’s settling time decreases drastically [8].
- 10. International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.1, Table 9. Hspice simulation results of two Vout Average power consumption Peak power over a cycle Slew rate Track time Hold time HSpice simulation result (fig.20) shows that track circuit is reduced drastically while the hold time in output waveform is increased. 3.5.1 Noise Analysis of two-stage T/H circuit Table 10. Noise results of two-stage T/H Total output noise voltage 7.473e- V/Hz =273.36864p V/Rt(Hz) Transfer function value (Vout/Vin) 115.94659f Equivalent input noise at Vin 2.35771K Total equivalent input noise voltage 734.89198K V 3.6 SLEW RATE LIMITATION OF SOURCE FOLLOWER T/H CIRCUIT When input signal is such that it demands an o/p response is faster than the specified value of slew rate (SR), non linear distortion will occur due to slew rate limitation. Figure 22. Slew rate distortion due to slewing Slew rate limitation cause non linear distortion when I/P is sinusoidal ournal of VLSI design & Communication Systems (VLSICS) Vol.2, No.1, March 2011 spice simulation results of two-stage T/H 1.59 v Average power consumption 64.30 mw Peak power over a cycle 69.80 mw 37 mv/ns .16 ns 0.62 ns ) shows that track-time in output waveform for two circuit is reduced drastically while the hold time in output waveform is increased. stage T/H circuit stage T/H -020 Sq 273.36864p V/Rt(Hz) 115.94659f 2.35771K 734.89198K V Figure 21. Output noise of two-stage RATE LIMITATION OF SOURCE FOLLOWER T/H CIRCUIT When input signal is such that it demands an o/p response is faster than the specified value of ear distortion will occur due to slew rate limitation. Slew rate distortion due to slewing Slew rate limitation cause non linear distortion when I/P is sinusoidal March 2011 54 time in output waveform for two stages T/H stage T/H RATE LIMITATION OF SOURCE FOLLOWER T/H CIRCUIT When input signal is such that it demands an o/p response is faster than the specified value of
- 11. International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.1, Thus the maximum occurs at zero crossing of I/P sinusoidal. If of the input buffer the output wa rate of change of the input sinusoidal at its zero crossing & hence source follower slews [7]. There is a specific frequency fM source follower begins to show distortion due to slew Figure 23. When the step voltage whose amplitude is larger than (Vgs of source follower T/H circuit, M load capacitor is discharged by a constant current I The output voltage during the slewing can be represented by Where Vgs1 is the gate-to-source bias voltage of M Msw1 is adequately small, this slewing continues as 3.7 COMPARISON OF POWER Figure 24. Comparison of power consumption Figure 24. Shows that average power consumed by two stage Track 0 50 100 150 200 76.94 78.3389.08 ournal of VLSI design & Communication Systems (VLSICS) Vol.2, No.1, March 2011 Thus the maximum occurs at zero crossing of I/P sinusoidal. If exceeds the slew rate of the input buffer the output waveform will be distorted. Output cannot keep up with this large rate of change of the input sinusoidal at its zero crossing & hence source follower slews [7]. M called the full-power bandwidth at which output voltage of the source follower begins to show distortion due to slew-rate limitation Figure 23. Single stage of source follower T/H When the step voltage whose amplitude is larger than (Vgs – VT) is applied to the single stage lower T/H circuit, M1 goes into the cut-off region at t = t0. When M1 is cut off, its load capacitor is discharged by a constant current IM2. The slew rate is limited to IM2/C The output voltage during the slewing can be represented by source bias voltage of M1 On the assumption that an on-resistance of is adequately small, this slewing continues as COMPARISON OF POWER omparison of power consumption that average power consumed by two stage Track-and-Hold circuit is minimum. 78.33 93.64 162 64.3 90.91 103.5 182 69.8 Average Power(mw) March 2011 55 exceeds the slew rate Output cannot keep up with this large rate of change of the input sinusoidal at its zero crossing & hence source follower slews [7]. power bandwidth at which output voltage of the ) is applied to the single stage . When M1 is cut off, its /C1. resistance of Hold circuit is minimum.
- 12. International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.1, 3.8 COMPARISON OF O/P N Figure 25. Graph shows that the o/p noise voltage of two stage Track 3.9 COMPARISON OF SLEW RATE Figure 26. From figure 26. It is observeed that the slew is maximum. 0 100 200 300 400 500 600 700 800 900 833.37339 0 20 40 60 80 100 120 140 160 180 200 89.64 ournal of VLSI design & Communication Systems (VLSICS) Vol.2, No.1, March 2011 COMPARISON OF O/P NOISE 25. Comparison of O/P noise voltage shows that the o/p noise voltage of two stage Track-and-Hold circuit is minimum. COMPARISON OF SLEW RATE Figure 26. Comparison of Slew Rate that the slew rate of the fully-differential Track-and-Hold circuit 668.83807 753.29254 546.01522 273.36864 Total output Noise Voltage (p V/Rt(Hz)) 110.48 135 181 40 Slew Rate(mv/ns) March 2011 56 minimum. Hold circuit
- 13. International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.1, March 2011 57 3. CONCLUSIONS It is found that the on-resistance of transmission-gate-switch (NMOS and MOS-transistor connected in parallel) is much more linear. Later on, NMOS switches are replaced with transmission-gate-switch. Two stage Track-and-Hold circuit shows 16.42% decrease in power consumption as compared to conventional Track-and-Hold circuit. Further, track time of two-stage T/H circuit is found to be .16(ns) which is minimum among all Track-and-Hold circuits. Hence two-stage structure is fastest among all designs. Fully differential Track-and-Hold circuit shows the highest slew rate (181 mv/ns) while two-stage T/H shows minimum slew (40 mv/ns). There is an 8.90% increase in Vout of two stage Track-and-hold circuit as compared to conventional Track-and-Hold circuit. Two-stage T/H circuit shows 67.19% reduction in output noise voltage as compared to conventional Track-and-Hold circuit. Two Stage T/H Circuit based on source follower buffers mitigates the problem of power consumption, large track time and noise but at the cost of small value of slew rate. A unity-gain buffer is capable to achieve high slew rates in both positive and negative directions. By sensing the drain current of the common-drain device in an NMOS source follower, the extent of slewing could be achieved. So the future work of this dissertation would be implementation of high slew rate Track-and-Hold circuit by using an enhanced slew rate source follower buffers [7]. ACKNOWLEDGEMENTS I express my heart-felt gratitude to Mr. Gagnesh Kumar, Assistant Professor, E&C Department, NIT Hamirpur for his invaluable guidance and support throughout this work. His encouragement was very helpful for me to go ahead in this project. I acknowledge with gratitude the technical and financial support from DIT, Ministry of Communications & Information Technology, Govt. of India, New Delhi, through VLSI SMDP- II Project at NIT Hamirpur HP. REFERENCES [1] S. H. Lewis and P. R. Gray, “A pipelined 5-Msample/s 9-bit analog-to digital converter,” IEEE J. Solid-State Circuits, vol. 22, pp. 954–961,Dec.87. [2] A. M. Abo and P. R. Gray, “A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter,” IEEE J. Solid-State Circuits, vol. 34, pp. 599–606, May 1999. [3] S. Limotyrakis, S. D. Kulchycki, D. K. Su, and B. A. Wooley, “A 150- MS/s 8-b 71-mW CMOS time-interleaved ADC,” IEEE J. Solid-State Circuits, vol. 40, pp. 1057–1067, May 2005. [4] M. Choi and A. A. Abidi, “A 6-b 1.3-Gsample/s A/D converter in 0.35-µm CMOS,” IEEE J. Solid-State Circuits, vol. 36, pp. 1847–1858, Dec.2001.
- 14. International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.1, March 2011 58 [5] W. Yang, D. Kelly, L. Mehr, M. T. Sayuk, and L. Singer, “A 3-V 340- mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist input,”IEEE J. Solid-State Circuits, vol. 36, pp. 1931–1936, Dec. 2001. [6] A. Boni, A. Pierazzi, and C. Morandi, “A 10-b 185-MS/s track-and-hold in 0.35-µm CMOS,” IEEE J. Solid-State Circuits, vol. 36, pp. 195–203,Feb. 2001. [7] An Enhanced Slew Rate Source Follower. John G. Kenney, Giri Rangan, Karthik Ramamurthy, and Gabor Temes, IEEE J. Solid-State Circuits, Vol. 36,pp.195-203,Feb. 2001 [8] Takahide SATO†a), Member, Isamu MATSUMOTO, Nonmember, Shigetaka TAKAGI, Member, and Nobuo FUJII, Fellow, Design of Low Power Track and Hold Circuit Based on Two Stage Structure, IEICE TRANS. ELECTRON., VOL.E91–C, NO.6 JUNE 2008 [9] W. Yu, S. Sen and B. H. Leung, “Distortion Analysis of MOS Track-and-Hold Sampling Mixers Using Time-Varying Volterra Series”,IEEE Transactions on circuits and systems-II: Analog and Digital Signal Processing, vol. 46, No. 2, Feb.1999. [10] Behzad Razavi, “Design of Analog CMOS Integrated Circuits”, McGraw Hill Higher Education, 2001, ISBN 0-07-238032-2. [11] D.A. Johns and K. Martin, Analog integrated circuit design, John Wiley & Sons, 1997. [12] Ruby van de Plassche, CMOS integrated analog to digital and digital to analog converters, Kluwer Academic Publishers, 2003. [13] P. R. Gray, P. J. Hurst, H. Lewis, and R. G. Mayer, “Analysis and Design of Analog Integrated Circuits”, 4th ed., Johnson Wiley and Sons, New York 2001 [14] F. Liu, S. Jia, Z. Lu, and L. Ji, “CMOS folding and interpolating A/D Converter with differential compensative T/H circuit,” Proc.2003 IEEE Conference on Electron Devices andSolid-State Circuits, pp.453–456, 2003. [15] T. Sato, S. Takagi, N. Fujii, Y. Hashimoto, K. Sakata, and H. Okada,“4GB/s track and hold circuit using parasitic capacitance canceler,” Proc. European Solid-State Circuits Conference,pp.347–350, 2004. [16] Mohammad Hekmat and Vikram Garg, “Design and Analysis of a Source-Follower Track-and- Hold Circuit” , EE315 (VLSI data conversion circuits) project report June 2006 [17] A.N. Karanicolas, “A 2.7-V 300-MS/s track-and-hold amplifier,” IEEE J. Solid-State Circuits, vol.32, pp.1961–1967, Dec. 1997. [18] Tadeparthy P., Das M. “Techniques to improve linearity of CMOS Sample-and-Hold circuits for achieving 100 db performance at 80Msps”, IEEE Circuits and Systems, 2002 [19] Yasutaka Haga and Izzet Kale, ’’Class-AB Rail-to-Rail Cmos Buffer with Bulk-Driven Super Source Followers” ,applied DSP and VLSI research group school of Electronics and Computer Science University of Westminster, London, 978-1-4244-3896-9/09/©2009 IEEE [20] A. J. López-Martin, J. Ramírez-Angulo, R. G. Carvajal, and L. Acosta,“Power-efficient Class AB CMOS Buffer”, IEE J. Electronic Letters, 2009, 45, (2), pp. 89–90.
- 15. International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.1, March 2011 59 Authors Manoj Kumar received B.Tech. degree from A.K.G Engineering College, Ghaziabad (U.P), India, in 2007 and M.Tech. degree from National Institute of Technology, Hamirpur (H.P), India, in July 2010. Since August 2010, he has been an Assistant Professor of Vidya College of Engineering, Meerut (U.P). His main interest lies in the field of low power analog integrated circuits, Digital VLSI Design, Microprocessor/Microcontrollers Gagnesh Kumar received B.E. degree from National Institute of Technology, India, in 2000 and M.Tech degree from Punjab University, Chandigarh, India, in 2003. He has been an Assistant Professor of National Institute of Technology, Hamirpur (H.P). His main interest lies in the field of Microelectronics, VLSI, Artificial intelligence, Neural networks.