P C I L O C A L B U S
- 1. Software Generation of Configuration Transactions for PCI Local Bus PCI Local Bus Specification (Peripheral Component Interconnect ) PCI 1998
- 2. Outline Introduction Terminology and problem definition Bus Comparisons PCI Address Space The main approach Software Generation of Configuration Transactions Experimental Results Conclusion
- 3. Introduction Different level of Bus
- 5. Outline Introduction Terminology and problem definition Bus Comparisons PCI Address Space The main approach Software Generation of Configuration Transactions Experimental Results Conclusion
- 6. PCI Lines
- 7. Bus Comparisons Bus Type Bus Width Bus Speed MB/sec ISA 16 bits 8 MHz 16 MB EISA 32 bits 8 MHz 32 MB VL-bus 32 bits 25 MHz 100 MB VL-bus 32 bits 33 MHz 132 MB PCI 32 bits 33 MHz 132 MB PCI 64 bits 33 MHz 264 MB PCI 64 bits 66 MHz 512 MB PCI 64 bits 133 MHz 1 GB
- 8. Bus Comparisons 4GB 100MHz (Diff.) x8 PCI Express 8GB 100MHz (Diff.) X16 PCI Express 2GB 100MHz (Diff.) x4 PCI Express 1GB 100MHz (Diff.) x2 PCI Express 500MB 100MHz (Diff.) x1 PCI Express MB/sec Bus speed Bus width Bus Type
- 9. Outline Introduction Terminology and problem definition Bus Comparisons PCI Address Space The main approach Software Generation of Configuration Transactions Experimental Results Conclusion
- 10. Problem Definition Given a configuration of hardware, our objective is to maximum the PCI speed .
- 11. PCI Address Space A PCI target can implement up to three different types of address spaces — Configuration space – Stores basic information about the device – Allows the central resource or O/S to program a device with operational settings — I/O space – Used mainly with PC peripherals and not much else — Memory space – Used for just about everything else
- 12. Types of PCI Address Space Configuration space (cont’d) — Contains 256 bytes – The first 64 bytes (00h – 3Fh) make up the standard configuration header, predefined by the PCI spec – The remaining 192 bytes (40h – FFh) represent user-definable configuration space • This region may store, for example, information specific to a PC card for use by its accompanying software driver
- 14. IO Space This space is where basic PC peripherals (keyboard, serial port,etc.) are mapped — The PCI spec allows an agent to request 4 bytes to 2GB of I/O space – For x86 systems, the maximum is 256 bytes because of legacy ISA issues
- 15. Memory Space Memory space — This space is used by most everything else – it’s the general-purpose address space – The PCI spec recommends that a device use memory space, even if it is a peripheral — An agent can request between 16 bytes and 2GB of memory space – The PCI spec recommends that an agent use at least 4kB of memory space, to reduce the width of the agent’s address decoder
- 16. Outline Introduction Terminology and problem definition Bus Comparisons PCI Address Space The main approach Software Generation of Configuration Transactions Experimental Results Conclusion
- 17. Software Generation of Configuration Transactions
- 18. Example (Program) mov eax, 080000878h ; Bus: 0 Dev:1 Fun:0 Offest: 87h mov dx, 0 CF 8h ; PCI_IO_CONFIG_ INDEX out dx, eax m ov dx, 0 CFC h ; PCI_IO_CONFIG_DATA in eax, dx or ax, 01h out dx, ax PCI INDEX : 0CF8h PCI DATA : 0CFCh
- 19. Outline Introduction Terminology and problem definition Bus Comparisons PCI Address Space The main approach Software Generation of Configuration Transactions Experimental Results Conclusion
- 22. Outline Introduction Terminology and problem definition Bus Comparisons PCI Address Space The main approach Software Generation of Configuration Transactions Experimental Results Conclusion
- 23. Setting
- 24. Conclusion The x86 PCI bus are standard structure add more the PCI device configuration in your design computer.
- 25. References PCI Local Bus Specification Revision 2.2 December 18, 1998