電流臨界モード方式PFC制御回路の解説書

Rectifiers PFC D2
2 1
L1
PARAMETERS: Diode
1 2
f req = 50Hz L2
Vin = 100Vac 0 Q1
MOSFET
C1 TB6819AFG C2 ILoad
Vac, in
1uF
Controller 200u
0.5A
Circuit

R7

0

Design KIT:
Critical Conduction Mode (CRM)
PFC Circuit
All Rights Reserved Copyright (C) Bee Technologies Corporation 2010 1

Contents

• Introduction
• Application Circuit
• Design Specification
• Time Scaling
• Application Circuit with Time Scaling (tscale =10)
• Common Mode Choke Coil for PFC
• Design Steps (1-8)
• Switching Devices VPEAK and IPEAK at Steady State
• Switching Devices VPEAK and IPEAK at Start Up
Appendix
A.Excel Calculation Sheet
B.Simulation Index


Introduction

PARAMETERS: bulk Vbulk
DB1
f req = 50Hz Diode
Vin = 100Vac
Iline DB4
AC_IN1
Vin Load
Cbulk 1.414Adc
2000uF

DB3 DB2
AC_IN2

0

Most electronic ballasts and switching power supplies use a bridge rectifier
and a bulk storage capacitor to derive raw dc voltage from the utility ac line,
figure above: Vin=100Vac, 50Hz and PO=200W.


Introduction
200V
|VAC, in, 100V| (VPEAK, in=100*2=141.42V) and Vbulk

100V

SEL>>
0V
ABS( V(AC_IN1,AC_IN2) ) V(bulk)
20A
|Iline|
10A

0A
ABS( I(Vin) )
1.0
0.8 Power Factor Ratio = Pin, avg./(Vin, rms* Iin, rms)
0.6
0.4
0.2
0
160ms 164ms 168ms 172ms 176ms 180ms 184ms 188ms 192ms 196ms 200ms
AVG(ABS(W(Vin)))/(RMS(ABS(V(AC_IN1,AC_IN2)))*RMS(ABS(I(Vin))))
Time

The Uncorrected Power Factor rectifying circuit draws current from the ac line
when the ac voltage exceeds the capacitor voltage (Vbulk). The current (Iline) is non-
sinusoidal. This results in a poor power factor condition where the apparent input
power is much higher than the real power, figure above, power factor ratios of 0.5 to
0.7 are common.


Introduction

Rectifiers PFC D2 VDC, OUT
2 1
L1
PARAMETERS: Diode
1 2
f req = 50Hz L2
Vin = 100Vac 0
Iline Q1
MOSFET
C1 TB6819AFG C2 ILoad
Vac, in
1uF
Controller 200u
0.5A
Circuit

R7

0

The Power Factor Correction (PFC) circuit, as an off-line active preconverter, is
designed to draw a sinusoidal current from the AC line that is in phase with input
voltage. As a result, the power factor ratio is improved to be near to ideal (1).
The TB6819AFG is a critical conduction mode (CRM) PFC controller IC. The
description including equation and constants as a guide to understand its designing
process is included in this document.


Introduction
160V 600V
1 2 VAC, in, 100V and VDC, OUT, 400V

0V 400V

>>
-160V 200V
1 V(AC_IN1,AC_IN2) 2 V(VOUT)
8.0A
Iline

0A

SEL>>
-8.0A
-I(Vin)
1.0
0.8
0.6 Power Factor Ratio = 0.85
0.4
0.2
*simulation result at tscale = 10
0
AVG(ABS(W(Vin))) / (RMS(ABS(V(AC_IN1,AC_IN2)))*RMS(ABS(I(Vin))))
Time*10

The poor power factor load is corrected by keeping the ac line current sinusoidal and in
phase with the line voltage. This results with power factor ratio is 0.85.


Application Circuit
PARAMETERS:
L = 230u
N = {1/9.6}
D3 N=N2/N1, L2=(N^2)*L1
PO = 200W,
Diode
L1 K1 VDC, OUT = 400VDC
{L} D2
PARAMETERS: DB1 Rtf 2 1
K V1 VOUT
f req = 50 Diode K_Linear Diode
1 2 COUPLING = 1
Vin = 100 R11 L2
DB4 360k {N*N*L} L1 = L1
AC_IN1 L2 = L2

V2
0
D4 R8 R2
Vin DB3 DB2 Diode 100k R5 Q1 1.5MEG
FREQ = {f req} MOSFET
VAMPL = {Vin*1.414} 10

VCC R6 R12 C2 200uF
68k
AC_IN2 R9 C7 IC = {2.51*1509.53/9.53}
39k
C1 3MEG 8p
VAC, in=85-265VAC 1u

POUT

ZCD
Load
0.5A
U1

VCC

COMP POUT

ZCD
GND
TB6819AFG

*Analysis directives:

FB_IN

MULT
.TRAN 0 20ms 0 100n

IS
.OPTIONS ABSTOL= 100n MULT
.OPTIONS GMIN= 1.0E-8 FB_IN

.OPTIONS ITL1= 500 COMP
.OPTIONS ITL2= 200 C8 C9 R3
.OPTIONS ITL4= 40 R10
22k 47uF 0.1uF
D5
DZ18V
10k
IS
R4 100

.OPTIONS RELTOL= 0.01 C5 IC = 17.9
C6 3300p
C3 C4 R1
.OPTIONS VNTOL= 100u 10nF 0.47uF R7 9.53k
1uF 0.11

IC = 3.74
0


Application Circuit
200V 420V

0V 400V

>>
-200V 380V
10A
Iline

0A

SEL>>
-10A
0s 2ms 4ms 6ms 8ms 10ms 12ms 14ms 16ms 18ms 20ms
-I(Vin)
Time
1.0

Power Factor Ratio = 0.85
0.5

0
Time

Total simulation time = 1429.49 seconds


Design Specification

This application circuit is for 400VDC/200W output

Critical Conduction Mode (CRM) PFC Circuit :

• VAC, in,min = 85 (VAC)
• VAC, in,max = 265 (VAC)
• VO = 400 (VDC)
• Po = 200 (W)
• fs = 20kHz ~ 150kHz, 50kHz
•  (assumed) = 90%

Control IC :
• Part # TTB6819AFG (PFC Controller IC)
• Switching Technique: Critical Conduction Mode (CRM)


Time Scaling

The transient (cycle-by-cycle) simulation of PFC circuits is really time (and memory)
consuming exercise, even with a fast computer.
There is a way to speed up simulations by artificially altering some of the key element values
by using of time scaling ratio (tscale), passed as a parameter to the simulation engine:

• F line = F line  tscale

• C 2 = C 2  tscale





Application Circuit with Time Scaling (tscale =10)
PARAMETERS:
L = 230u
N = {1/9.6}
D3 N=N2/N1, L2=(N^2)*L1
PARAMETERS: PO = 200W,
tscale = 10 Diode
L1 K1 VDC, OUT = 400VDC
{L} D2
K V1 VOUT
1 2 COUPLING = 1
Vin = 100 R11 L2
DB4 360k {N*N*L} L1 = L1
AC_IN1 L2 = L2

V2
0
D4 R8 R2
FREQ = {f req*tscale} MOSFET
VAMPL = {Vin*1.414} 10

VCC R6 R12 C2 {200u/tscale}
68k
AC_IN2 R9 C7 IC = {2.51*1509.53/9.53}
39k
C1 3MEG 8p
VAC, in=85-265VAC 1u

POUT

ZCD
Load
0.5A
U1

VCC

COMP POUT

ZCD
GND
TB6819AFG


FB_IN

MULT
.TRAN 0 2ms 0 100n

IS
.OPTIONS ABSTOL= 100n MULT
.OPTIONS GMIN= 1.0E-8 FB_IN

.OPTIONS ITL4= 40 R10
22k 47uF 0.1uF
D5
DZ18V
10k
IS
R4 100

.OPTIONS RELTOL= 0.01 C5 IC = 17.9
C6 3300p
C3 C4 R1
.OPTIONS VNTOL= 100u {10n/tscale} {0.47u/tscale} R7 9.53k
0.11

IC = 3.74 {1u/tscale}
0


Application Circuit with Time Scaling (tscale =10)
200V 420V

0V 400V

>>
-200V 380V
10A
Iline

0A

SEL>>
-10A
-I(Vin)
Time*10
1.0

Power Factor Ratio = 0.85
0.5

0
Time*10



Common Mode Choke Coil for PFC

PARAMETERS: To model a simple common mode choke coil, the
L = 230u
SPICE primitive k, which describes the coupling ratio
between L1 and L2, can be used.
N = {1/9.6}
N=N2/N1, L2=(N^2)*L1
COUPLING=1 of K_Linear means there is no leakage
inductance in the common mode choke coil model.
L1 K1
{L}
2 1
K N is a ratio of L2 turns and L1 turns, or N2/N1
K_Linear
1 2 COUPLING = 1
L2 Input the parameters: L as an L1 inductance value
L1 = L1
{N*N*L} and N, then L2 is calculated using equation: L2 =
L2 = L2
N2L1


Design Steps (1-8)

(1) Output Voltage and Feedback Circuit

(2) Output Capacitor

(3) L1 Inductance

(4) Input Capacitor

(5) Auxiliary Winding L2

(6) Multiplier Input Circuit (MULT)

(7) Current Detection Circuit (IS)

(8) Zero Current Detection Circuit (ZCD)


(1) Output Voltage and Feedback Circuit

The output voltage is resistively divided and applied to the error amplifier, to set the V O
the R1 and R2 resistor value should satisfy the following equation :

VO  R1
 2.51
R1  R 2

Output DC Voltage, VO 400 V
Error Amplifier Reference Voltage Verr 2.51 V
R2 1.5 M
R1 9.47 k
R1 (actual) 9.53* k

*With VO=400V and R2=1.5M, R1 is calculated to be 9.47k, however a resistor of 9.53k , which
is available in the E96 series, is used as R1 (actual).



The output capacitance C2 is determined so that the PFC output ripple voltage dose not
exceed the VOPV-2, for the capacitor selection, the following equation should be satisfied:

PO
C2 
2  2f in  VO  VOVP-2 /Verr  - 1
2

PO 200 W
fin 50 Hz
VO 400 V
VOVP-2, min 2.63 V
Verr, min 2.46 V
C2  41 F
C2used 200 F

The value of VOVP-2, min and Verr, min are inform in the TB6819AFG datasheet.


Simulation of Step (1) and (2)
Vin = 100Vac with
PARAMETERS:
frequency 50Hz, L = 230u

tscale = 10 N = {1/9.6}
D3 N=N2/N1, L2=(N^2)*L1
PARAMETERS:
tscale = 10 Diode
L1 K1
{L} D2
K V1 VOUT
1 2 COUPLING = 1
Vin = 100 R11 L2
DB4 360k {N*N*L} L1 = L1
AC_IN1 L2 = L2

V2
0 C2 =
Vin DB3 DB2
D4
Diode
R8
100k R5 Q1
R2
1.5MEG
200F
VAMPL = {Vin*1.414} 10

68k
AC_IN2 R9 C7 IC = {2.51*1509.53/9.53}
39k
C1 3MEG 8p
1u

POUT

ZCD
Load
0.5A
U1

VCC

COMP POUT

ZCD
GND
TB6819AFG
Iload = 0.5A as
.TRAN 0 4ms 0 100n
R1=9.53k and

FB_IN

MULT
.OPTIONS ABSTOL= 100n PO=200W at

IS
.OPTIONS GMIN= 1.0E-8 R2=1.5M VO=400V
MULT
.OPTIONS ITL1= 500 FB_IN

R10 D5 10k
.OPTIONS RELTOL= 0.01 22k 47uF 0.1uF DZ18V IS
R4 100

.OPTIONS VNTOL= 100u C5 IC = 17.9
C3 C4 C6 3300p R1
{10n/tscale} {0.47u/tscale} R7 9.53k
0.11

0


200V
VAC, in,=100V (VPEAK, in,=100*1.4142=141.4V)

0V

-200V
V(AC_IN1,AC_IN2)
420V
VO=400Vdc with 2fline ripple

400V

SEL>>
380V
V(VOUT)
2.8
V(FB IN), VOVP-2, min.(2.63V), and Verr,min(2.46V)

2.6

2.4
0s 5ms 10ms 15ms 20ms 25ms 30ms 35ms 40ms
V(FB_IN) 2.63 2.46
Time*10


(3) L1 Inductance

The switching frequencyfs (Hz) depends on the L1 inductance and
input/output condition which the equation and the calculation data are as shown
below.
2
(VO  2  VAC, in, min )η  VAC, in, min

L1 
2 100  fs  VO  PO

Minimum AC Input Voltage, VAC, in, min 85 V
Power Efficiency,  (assumed) 90 %
Switching Frequency, fs* 50 kHz
Output Power, PO 200 W
Calculated Inductance, L1(calculated) 227 H
Selected (Actual) Inductance, L1(actual) 230 H

*The fs value should be within 20kHz and 150kHz, to avoid an occurrence of EMI
problem, fs=50kHz is used.

(4) Input Capacitor

C1 should be capable of supplying energy stored in the L1 while the FET is on. Assumed
that the on/off duty is 50%, the C1 should be temporarily able to supply twice the current.
A current reaches its maximum at the VAC, in, min. Thus, the following relationship should
be satisfied:

2
2  L1 PO
C1 4
VAC,in,min

L1 230 H
PO 200 W
VAC, in, min 85 V
C1  0.35 F
C1used 1 F


The Calculated L1 value
Vin, min = 85Vac with 227H (adjusted 230H PARAMETERS:
frequency 50Hz, is used) L = 230u

tscale = 10 N = {1/9.6}
D3 N=N2/N1, L2=(N^2)*L1
PARAMETERS:
tscale = 10 Diode
L1
I(L1) {L}
K1
K
D2
PARAMETERS: DB1 Rtf 2 1 V1 VOUT
1 2 COUPLING = 1
Vin = 85 R11 L2
DB4 360k {N*N*L} L1 = L1
AC_IN1 L2 = L2

V2
0
D4 R8 R2
VAMPL = {Vin*1.414} 10

68k
AC_IN2 R9 C7 IC = {2.51*1509.53/9.53}
39k
C1 3MEG 8p
1u

POUT

ZCD
Load
0.5A
C1 = 1F U1

VCC

COMP POUT

ZCD
GND
TB6819AFG
.TRAN 0 20ms 16m 100n Iload = 0.5A as

FB_IN

MULT

IS
.OPTIONS GMIN= 1.0E-8 MULT
VO=400V

R10 D5 10k
R4 100

C3 C4 C6 3300p R1
0.11

0


405V
VO=400Vdc with high switching ripple

400V

SEL>>
395V
V(VOUT)
10A

I(L1)

5A

0A
-I(L1)
20V
Switching Control Signal, fs = 48.4 kHz

10V

0V
16.45ms 16.46ms 16.47ms 16.48ms 16.49ms 16.50ms 16.51ms 16.52ms 16.53ms 16.54ms 16.55ms
V(POUT)
Time




The auxiliary winding L2 is used to detect the zero inductor current condition of the inductor L1.
Since the maximum reference voltage for the ZCD comparator is 1.9V (the IC specification) ,
N1/N2 should meet the following condition:

VO  2  VAC, in, max
N1/N2 
1.9

Maximum AC Input Voltage, VAC, in, max 265 V
Calculated Turn Number Ratio, N1/N2 < 14
Selected Transformer Turn Ratio, N1/N2 (actual) 9.6*

Where N1 is the number of winding of turns of L1, N2 is that of L2

*To ensure that the design requirements are met, N1/N2 should preferably about 10 (9.6 is
used) to allow for design margins.


Simulation of Step (5)
Vin, min = 265Vac with N1/N2=9.6, input
frequency 50Hz, parameter N = PARAMETERS:
L = 230u

tscale = 10 N2/N1 = 1/9.6 N = {1/9.6}
D3 N=N2/N1, L2=(N^2)*L1
PARAMETERS:
tscale = 10 Diode
I(L1) L1
{L}
K1
D2
K V1 VOUT
1 2 COUPLING = 1
Vin = 265 R11 L2
DB4 360k {N*N*L} L1 = L1
AC_IN1 L2 = L2

V2
0
D4 R8 R2
VAMPL = {Vin*1.414} 10

68k
AC_IN2 R9 C7 IC = {2.51*1509.53/9.53}
39k
C1 3MEG 8p
1u

POUT

ZCD
Load
0.5A
U1

VCC

COMP POUT

ZCD
GND
TB6819AFG
.TRAN 0 4ms 2ms 100n Iload = 0.5A as

FB_IN

MULT

IS
VO=400V

R10 D5 10k
R4 100

C3 C4 C6 3300p R1
0.11

0


400V

0V
VAC, in, min=265V (VPEAK, in, min=265*1.4142=374.8V)
-400V
V(AC_IN1,AC_IN2)
425V

VO=400V and PO=200W
400V

SEL>>
375V
V(VOUT)
5.0A
I(L1)
2.5A

0A
-I(L1)
7.5
V(ZCD) and the maximum reference voltage of the TB6819AFG’s ZCD comparator, 1.9V
5.0

2.5

0
V(ZCD) 1.9
Time*10



The AC input supply voltage (sinewave) is applied to the multiplier by dividing a full-wave
rectified voltage waveform.
The IC startup threshold voltages of the Brown Out Protection (BOP) function = 0.75V and
the MULT linear input voltage range of the multiplier = 0 to 3V, the R9 and R10 resistor should
satisfy the following condition:

VAC, in, min  2  R10 VAC, in, max  2  R10
0.75  and 3
R 9  R10 R9  R10

Maximum AC Input Voltage, VAC, in, min 400 V
Maximum AC Input Voltage, VAC, in, max 265 V
R9 3 M
R10 22 k
Minimum Condition for BOP 0.875 > 0.75
Maximum Condition for Linear MULT 2.728 <3

with excel calculation sheet PFC_Cal-Sht.xlsx you can input R9 and R10 values, then check the
calculated BOP and Linear MULT values to be within the maximum values.


Simulation of Step (6) at Vin, max
Vin, max = 265Vac with
PARAMETERS:

tscale = 10 N = {1/9.6}
D3 N=N2/N1, L2=(N^2)*L1
PARAMETERS:
tscale = 10 Diode
L1 K1
{L} D2
K V1 VOUT
1 2 COUPLING = 1
Vin = 265 R11 L2
DB4 360k {N*N*L} L1 = L1
AC_IN1 L2 = L2

V2
0
D4 R8 R2
VAMPL = {Vin*1.414} 10

68k
AC_IN2 R9 C7 IC = {2.51*1509.53/9.53}
39k
C1 3MEG 8p
1u

POUT

ZCD
Load
0.5A

R10=3M and U1

VCC

COMP POUT

ZCD
GND
TB6819AFG
R11=22k Iload = 0.5A as
.TRAN 0 4ms 2ms 100n

FB_IN

MULT

IS
VO=400V

R10 D5 10k
R4 100

C3 C4 C6 3300p R1
0.11

0


Simulation of Step (6) at Vin, max
400V

200V

0V
VAC, in, max=265V (VPEAK, in, min=265*1.4142=374.8V)
-200V
SEL>>
-400V
V(AC_IN1,AC_IN2)
400V

300V

200V

100V Full-wave rectified voltage
0V
V(Rtf)
4.0

3.0
V(MULT) < MULT linear input maximum voltage (3V)
2.0

1.0

0
V(MULT) 3
Time*10


Simulation of Step (6) at Vin, min
Vin, min = 85Vac with
PARAMETERS:

tscale = 10 N = {1/9.6}
D3 N=N2/N1, L2=(N^2)*L1
PARAMETERS:
tscale = 10 Diode
L1 K1
{L} D2
K V1 VOUT
1 2 COUPLING = 1
Vin = 85 R11 L2
DB4 360k {N*N*L} L1 = L1
AC_IN1 L2 = L2

V2
0
D4 R8 R2
VAMPL = {Vin*1.414} 10

68k
AC_IN2 R9 C7 IC = {2.51*1509.53/9.53}
39k
C1 3MEG 8p
1u

POUT

ZCD
Load
0.5A

R10=3M and U1

VCC

COMP POUT

ZCD
GND
TB6819AFG
.TRAN 0 20ms 16m 100n

FB_IN

MULT

IS
VO=400V

R10 D5 10k
R4 100

C3 C4 C6 3300p R1
0.11

0


Simulation of Step (6) at Vin, min
200V

0V
VAC, in, min=85V (VPEAK, in, min=85*1.4142=120.2V)

-200V
V(AC_IN1,AC_IN2)

120V
Full-wave rectified voltage

80V

40V
SEL>>
0V
V(Rtf)
1.0
V(MULT) > BOP threshold voltage (0.75V)

0.5

0
V(MULT) 0.75
Time*10



Iq1 (power switch current) is converted into voltage by R7, then applied to the IS pin. The R7
resistor value calculation follows these steps:
1) The maximum current of the Q1 current, Iq1 (max) should allow the output power PO to meet
the specification. Therefore, the following equation should be satisfied:

P  100  2  2
Iq1(max.) O

(η  VAC,in,min  2 )
2) the IS pin peak voltage (Visp) is calculated using the following equation:

0.65  VAC, in, min  2  R10
Visp 
R9  R10
3) R7 = Visp / Iq1(max.).
Minimum ac input voltage, VAC, in, min 85 V
Output power, PO 200 W
Power efficiency,  (assumed) 90 %
R9 3 M
R10 22 k
Power switch current, Iq1(max.) 5.23 A
TB6819AFG IS pin peak voltage Visp 0.57 V
R7 0.11 


PARAMETERS:

tscale = 10 N = {1/9.6}
D3 N=N2/N1, L2=(N^2)*L1
PARAMETERS:
tscale = 10 Diode
L1 K1
{L} D2
K V1 VOUT
1 2 COUPLING = 1
Vin = 85 R11 L2
DB4 360k {N*N*L} L1 = L1
AC_IN1 L2 = L2

V2
0
D4 R8 R2
VAMPL = {Vin*1.414} 10
R6 R12 C2 {200u/tscale}
VCC
68k Iq1
AC_IN2 R9 C7 IC = {2.51*1509.53/9.53}
39k
C1 3MEG 8p
1u

POUT

ZCD
Load
0.5A

R10=3M and U1

VCC

COMP POUT

ZCD
GND
TB6819AFG
.TRAN 0 20ms 16m 100n

FB_IN

MULT

IS
VO=400V

R7 =
.OPTIONS RELTOL= 0.01 R10
22k 47uF 0.1uF
D5
DZ18V
10k
IS
R4 100 0.11
C3 C4 C6 3300p R1
0.11

0


1.0V
V(MULT)

0.5V

0V
V(MULT)
8.0A
Iq1
6.0A

4.0A

2.0A
SEL>>
0A
ID(Q1)
1.0V
V(IS)

0.5V

0V
V(IS)
Time*10




The auxiliary winding L2 is connected to the ZCD pin. The current through L2 is limited to ZCD
pin rated current (3mA) by using the current limiting resistor R6. The following relationship
should be satisfied depending on whether the external FET is on or off:

VAC,in,max.  2  N2/N1
FET = On: R6 
3mA

VO  N2/N1
FET = Off: R6 
3mA

VAC, in, max 265 V
N2/N1 1/9.6 W
VO 400 V
FET = ON, R6 > 13.0 k
FET = OFF, R6 > 13.9 k
R6 (actual) 68 k

A resistor of 68k is used for limiting the current to 1/5 of the rated current


Vin, max = 265Vac with
PARAMETERS:

tscale = 10 N = {1/9.6}
D3 N=N2/N1, L2=(N^2)*L1
PARAMETERS:
tscale = 10 Diode
L1 K1
{L} D2
K V1 VOUT
1 2 COUPLING = 1
Vin = 265 R11 L2
DB4 360k {N*N*L} L1 = L1
AC_IN1 L2 = L2

V2
0
D4 R8 R2
VAMPL = {Vin*1.414} 10 ON/OFF
68k
AC_IN2 R9 C7 IC = {2.51*1509.53/9.53}
C1 3MEG 8p R6 = 39k

68k
1u

POUT

ZCD
Load
0.5A

R10=3M and U1

VCC

COMP POUT

ZCD
GND
TB6819AFG
.TRAN 0 4ms 2ms 100n

FB_IN

MULT

IS
VO=400V

R10 D5 10k
R4 100

C3 C4 C6 3300p R1
0.11

0


400V

0V
VAC, in, max=265V

SEL>>
-400V
V(AC_IN1,AC_IN2)
425V
V(VOUT)

400V

375V
V(VOUT)
1.0m
I(R6) and 1/5 of the ZCD rated current (3mA/5)

0

-1.0m
I(R6) 3m/5
Time*10


Switching Devices VPEAK and IPEAK at Steady State
PARAMETERS:

tscale = 10 N = {1/9.6} Switching
D3 N=N2/N1, L2=(N^2)*L1
PARAMETERS: Diode, D2
tscale = 10 Diode
L1 K1
{L} D2
K V1 VOUT
1 2 COUPLING = 1
Vin = 85 R11 L2
DB4 360k {N*N*L} L1 = L1
L2 = L2
I(D2)
AC_IN1

V2
0 ID(Q1)
D4 R8 R2
VAMPL = {Vin*1.414} 10

68k
AC_IN2 R9 C7 IC = {2.51*1509.53/9.53}
C1 3MEG 8p
39k
Switching
1u

POUT
MOSFET, Q1

ZCD
Load
0.5A
U1

VCC

COMP POUT

ZCD
GND
TB6819AFG

FB_IN

MULT

IS
VO=400V

R10 D5 10k
R4 100

C3 C4 C6 3300p R1
0.11

0


Switching Devices VPEAK and IPEAK at Steady State
600V
D2 VKA, Peak ≈ 400V at steady state
400V

200V

0V
V(D2:2,D2:1)
16A
D2 IF, Peak ≈ 12A at steady state
8A

SEL>>
-2A
I(D2)
600V
Q1 VDS, Peak ≈ 400V at steady state
400V

200V

0V
V(Q1:d,Q1:s)
12A
Q1 ID, Peak ≈ 7.2A at steady state
6A

0A

-6A
18.00ms 18.25ms 18.50ms 18.75ms 19.00ms 19.25ms 19.50ms 19.75ms 20.00ms
ID(Q1)
Time



Switching Devices VPEAK and IPEAK at Start Up
PARAMETERS:
tscale = 40 N = {1/9.6} Switching
N=N2/N1, L2=(N^2)*L1
PARAMETERS:
D3
Diode, D2
tscale = 40 Diode
L1 K1
{L} D2
K V1 VOUT
1 2 COUPLING = 1
Vin = 85 R11 L2
DB4 360k {N*N*L} L1 = L1 I(D2)
AC_IN1 L2 = L2

V2
0
ID(Q1)
D4 R8 R2
VAMPL = {Vin*1.414} 10


AC_IN2
Rectifier R9 C7
68k

Diode, DB1-4 C1
1u
3MEG 8p
39k
Switching

POUT
MOSFET, Q1

ZCD
Load
0.5A
U1

VCC

COMP POUT

ZCD
GND
TB6819AFG

FB_IN

MULT

IS
.OPTIONS GMIN= 1.0E-8 MULT VO=400V


R10 D5 10k
R4 100
C5 IC = 17.9
.OPTIONS VNTOL= 100u C3 C4 C6 3300p R1
0.11

{1u/tscale}
0


Switching Devices VPEAK and IPEAK at Start Up
600V
V(VOUT) at start up
400V

200V

0V
V(VOUT)
200V 16A
1 2 DB1-4 IF, Peak ≈ 10A at start up
100V 8A

>>
-10V 0A
1 V(DB1:2,DB1:1) 2 I(DB1)
600V 18A
1 2 D2 VKA, Peak ≈ 400V and IF, Peak ≈ 16A at start up
400V 12A

200V 6A
SEL>>
0V 0A
1 V(D2:2,D2:1) 2 I(D2)
500V 10A
1 2

0V 0A

>> Q1 V
DS, Peak ≈ 400V and ID, Peak ≈ 10A at start up
-500V -10A
1 V(Q1:d,Q1:s) 2 ID(Q1)
Time*40


Simulation with Models from the SpicePark (1/4)
Replace some default model with models from SpicePark
PARAMETERS:
L = 230u
N = {1/9.6} Schottky diode
D3 N=N2/N1, L2=(N^2)*L1
PARAMETERS: model
tscale = 10 Diode
L1 K1 D2
{L}
K V1 VOUT
f req = 50 Diode K_Linear
1 2 COUPLING = 1
Vin = 100 R11 L2 SCS110AG
DB4 360k {N*N*L} L1 = L1
AC_IN1 L2 = L2

V2
0 Capacitor
Vin DB3 DB2
D4
Diode
R8
100k R5
R2
1.5MEG model
FREQ = {f req*tscale}
VAMPL = {Vin*1.414} 10
Q2
VCC R6 R12 2SK2611 C2
68k RJJ-35V221MG5-T20
AC_IN2 R9 C7
39k
C1 3MEG 8p
1u

POUT

ZCD
MOSFET Load
0.5A
U1 professional

VCC

COMP POUT

ZCD
GND
TB6819AFG
*Analysis directives: model
.TRAN 0 2ms 0 100n

FB_IN

MULT
.OPTIONS ABSTOL= 100n

IS


R10 D5 10k
R4 100

C3 C4 C6 3300p R1
0.11

0


V(VOUT) with high frequency ripple which is caused by ESR and ESL of the capacitor model.
400V

392V
0s 0.2ms 0.4ms 0.6ms 0.8ms 1.0ms 1.2ms 1.4ms 1.6ms 1.8ms 2.0ms
V(VOUT)
Time
20V

10V
SEL>> Gate charge characteristics is include in the MOSFET Professional model.
V(Q2:g)
500V
V(V1)
250V

0V
V(V1)
10A
I (L1)
5A

0A
-I(L1)
40V
V(V2)
0V

484us 488us 492us 496us 500us 504us 508us 512us 516us 520us 524us
V(V2)
Time



The Simulation Waveform with the defaults models

V(VOUT) without high frequency ripple which is caused by ESR and ESL of the capacitor model.
400V

392V
0s 0.5ms 1.0ms 1.5ms 2.0ms
V(VOUT)
Time
20V

10V
Gate charge characteristics is not include in the default model.
SEL>>

V(Q1:g)
500V

250V V(V1)
0V
V(V1)
10A
I (L1)
5A

0A
-I(L1)
40V
V(V2)
0V

476us 480us 484us 488us 492us 496us 500us 504us 508us 512us 516us
V(V2)
Time



Select the device which is
capable of handling the SpicePark of MOSFET model
simulated peak values.


Excel Calculation Sheet (1/2)

Design Specification

VAC, in,min 85 V
VAC, in,max 265 V
fin 50 Hz
VO 400 V
PO 200 W
fs 50 kHz
 (assumed) 90 %

(1) Output Voltage & Feedback Circuit
R2 1.5 M ; Input R2 value, the R1 for the VO specification is
R1 9.47 k auto-calculated
R1 (actual) 9.53 k

VOVP-2, MIN. 2.63 V ; VOVP-2, MIN. and Verr, MIN. are TB6819AFG electrical
Verr, MIN. 2.46 V characteristics
C2 ³ 41 mF

(3) L1 Inductance
L1 227 mH
L1(actual) 230 mH


Excel Calculation Sheet (2/2)
(4) Input Capacitor
C1 ³ 0.35 F
C1(actual) 1 F

N1/N2 < 14
N1/N2(actual) 9.6

R9 3 M ; Input R9 and R10 values, then check the BOP and
R10 22 k the Linear MULT values
Codition:
BOP 0.875 > 0.75
Linear MULT 2.728 <3

Iq1(max.) 5.23 A
Visp 0.57 V
R7 0.11 

FET=ON, R8 > 13.0 k
FET=OFF, R8 > 13.9 k
R8 (actual) 68 k ; limiting the current to 1/5 of the rated current.
Remark
Input your design specification and your selected parameters. The numbers in the green font are auto-
calculated numbers. The numbers in the blue font are the design actual selected (used) number.


Simulation Index

Simulations Folder name

1. Application Circuit....................................................................... APPCKT
2. Application Circuit with Time Scaling (tscale =10)......................... APPCKT_tscale
3. Simulation of Step (1) and (2)..................................................... STEP1-2
4. Simulation of Step (3) and (4)..................................................... STEP3-4
5. Simulation of Step (5)................................................................. STEP5
6. Simulation of Step (6) at Vin, max.................................................. STEP6_INMAX
7. Simulation of Step (6) at Vin, min................................................... STEP6_INMIN
10. Switching Devices VPEAK and IPEAK at Steady State................... IVPEAK-SS
11. Switching Devices VPEAK and IPEAK at Start Up........................... IVPEAK-SU

Libraries :
1. ..parttb6819afgtb6819afg.lib
2. ..partparts.lib


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