![The acoff Utility
• The acoff utility reads a TI COFF file and displays its contents.
• It supports TI COFF versions 0, 1 and 2. Version detection is automatic.
• It can also be used to extract the binary executable raw data from a COFF file, for
use with a disassembler.
• It supports various options for formatting the extracted data.
• Usage:
acoff [-ablrs] [coff filename]
a: print all information.
b: print binary executable data.
l: print relocation entries.
r: print raw data from all sections.
s: print the symbol table entries.
Default: print headers only.](https://image.slidesharecdn.com/ee675slides-250711064702-fa22802d/85/Phase-Locked-Loop-PLL-Presentation-for-MTech-Level-35-320.jpg)
![Low Pass Filter by Heun’s Method
s τ
1
+
−
y
u
y0
(n + 1) = y(n) + c{u(n) − y(n)}
y(n + 1) = y(n) +
c
2
[{u(n) − y(n)}
+{u(n) − y0
(n + 1)}]
c =
∆T
τ
y(n + 1) = (1 − c + c2
2 )y(n) + (c − c2
2 )u(n)
• Unstable for
∆T 2τ
• Better accuracy and stability than Eu-
ler’s Explicit Method.
• Computationally more intensive.
0 0.02 0.04 0.06 0.08 0.1
0
0.5
1
1.5
Euler explicit
Heun
Actual
∆T = 5ms, τ = 0.016666s](https://image.slidesharecdn.com/ee675slides-250711064702-fa22802d/85/Phase-Locked-Loop-PLL-Presentation-for-MTech-Level-91-320.jpg)
![Trapezoidal Rule
• For the system of N first order ODEs:
ẏi = fi(t, y1, . . . , yN ), i = 1 . . . N
take the average of the derivatives at n and n + 1.
• One of the Newton-Cotes Formulas.
• Stable even for large time steps.
• Solving the implicit equations to calculate the derivatives can be difficult. Example:
ẏ1 = f1(y1, y2) ; ẏ2 = f2(y1, y2)
y1(n + 1) = y1(n) + ∆T
2 × [f1(y1(n), y2(n)) + f1(y1(n + 1), y2(n + 1))]
y2(n + 1) = y1(n) + ∆T
2 × [f2(y1(n), y2(n)) + f2(y1(n + 1), y2(n + 1))]
• If the system of ODEs is nonlinear, then it needs to be linearised at every time point.
• Roger Cotes (1682 – 1756): English mathematician, close collaborator of Isaac
Newton. Proofread Newton’s Principia Mathematica.](https://image.slidesharecdn.com/ee675slides-250711064702-fa22802d/85/Phase-Locked-Loop-PLL-Presentation-for-MTech-Level-95-320.jpg)
Phase Locked Loop (PLL) Presentation for MTech Level
- 1. EE 675: Microprocessor Applications in Power Electronics M.C. Chandorkar Department of Electrical Engineering Indian Institute of Technology – Bombay
- 2. Linear and Switching Power Conditioning Circuits V s vo Load − + + − vr − + • Vr: Voltage reserve • Continuous power loss in se- ries device • Suitable for low power applica- tions V s vo C − + L Load D PI reg V* + − − + + − • No need for voltage reserve • “No” loss in series device • Suitable for high power power applica- tions
- 3. Single Phase Inverter is S21 S22 S11 S12 mi a b Vs Vs −Vs Vab − + • Main function: Convert dc voltage to ac voltage of required frequency and amplitude. • Uses power semiconductor devices, typically Insulated Gate Bipolar Transistors) (IGBT). • IGBTs are rated in the range 100 V, 10 A to 3.3 kV, 600 A. • The devices are operated a switches. Inverters are switching power circuits.
- 4. Insulated Gate Bipolar Transistor (IGBT) Package Source: International Rectifier (www.irf.com)
- 5. Example: Induction Motor Drive g1 g3 g5 g4 g6 g2 + − + − g1 g4 g6 g3 g5 g2 + − ref_c ref_b ref_a 1 mΩ 5 s µ 5 s µ 5 s µ Delay Delay Delay vm np 340 V 50 Hz 0.25 mH v_dc i_as carrier a b c I.M. C i_am • Motor speed control. • Variable frequency, variable voltage induction motor controller. • Typical ratings: 415 V, 50 kW 415 V, 1 MW. • Applications: Fans, Blowers, Pumps, ...
- 6. Schematic Diagram: MV AC Motor Drive Source: ABB Medium Voltage Drives • Sinusoidal output voltage • Neutral Point Clamped Inverter • Retrofit applications
- 7. MV Drive Layout Source: ABB Medium Voltage Drives
- 8. High Performance Drive Control Motor Dynamic Model Parameter Estimate Speed Estimate Set Speed Speed Controller Gate Drives Inverter Control Feedback V, I T_est F_est F* T* (FOC) (DTC) Time Frames • 20 µs: – Motor model – Feedback • 100 µs: – Motor model – Protection – Speed estimate • 1 ms: – Flux reference – Speed controller – Parameter estimates – Ride through
- 9. Typical Timing Needs: Induction Motor Drive • 25 µs task: – Motor model (fast part) – Measurement and feedback • 100 µs task: – Motor model (slow part) – Speed estimation – DC over- and under-voltage prot. – Power failure ride-through • 1 ms task: – Speed controller – Torsional oscillation damping – Field weakening control • 10 ms task: – Parameter estimation – Communication • 100 ms task: – Operator inputs – Display updating – Drive state determination • 1 s task: – Motor thermal model – Motor temperature estimate • Background task: – Time usage estimates – Low priority I/O • A task should never fill all the time of its repetition rate ∆T. • PE tasks have hard deadlines. The penalty for exceeding deadlines is very high.
- 10. Induction Motor Control Block Diagram Source: ABB Review 6/1997
- 11. Advanced Static VAr Compensation A A A ASVC Load ap bp cp a1 b1 c1 rla rlb rlc n np as bs cs a b c −400 −200 0 200 400 V V_a 0.45 0.55 −600 −100 400 A I_Load I_real I_react I_Load_1 • ASVC: Advanced Static VAr Compensator • Provides all of the reactive cur- rent component • Provides harmonic currents upto the 17th • Good PLL design needed
- 12. Commercial Active Filter Source: ABB Jumet, Belgium • IGBT inverters • Low voltage product • Capacitor DC bus • Modular: – 1 or 2 inverter modules • DSP controller • 800x600x2150 mm (WxDxH) • 600 kg with two inverter modules
- 13. ABB Active Filter Features • 50 Hz, 415 V, three phase, three wire systems • Voltage tolerance: +/- 10% • RMS current rating: 225 A per module • Upto 20 harmonics can be filtered, upto the 50th harmonic • Programmable attenuation for individual harmonic • Operation between +/- 0.7 PF (programmable) • Response time: 40 ms • Active power consumption: 7 kW per module
- 14. Mitigating the Sag Problem: Dynamic Voltage Restorer (DVR) Protected System b c 3 Phase AC System • Dynamic Voltage Restorer (DVR): – Typical response time 10 ms. – Typical power rating: 4 MW for 100 ms. • Also known as the Dynamic Sag Corrector. • Lower cost than a comparably rated UPS system.
- 15. ABB Dynamic Voltage Restorer Installation Source: ABB High Voltage Systems Zürich
- 16. ABB Dynamic Voltage Restorer • Target industries: Semiconductor fabrication, printing, plastic, steel works, IT. • Power rating range: 3 MVA – 100 MVA • System voltage rating range: 3 kV – 230 kV • Upto 90% voltage sags compensated • Hot standby efficiency: 99% • Response time: 1 ms
- 17. Microcontrollers • Examples: Motorola 68HC16, Siemens SAB 88C166 • One operation per instruction • Single instruction per cycle, low clock speed • Several instructions to perform a given operation • Narrow instruction word (8-bit or 16-bit) • Multiple cycles for multiply • Rich in on-chip peripherals, good interrupt structure • Low cost
- 18. Microprocessors • Examples: Intel Pentium, Motorola Power PC • Typically, one operation per instruction • Multiple instructions per cycle • Several instructions to perform a given operation • Large program memory requirement • Very good high-level software support (C compilers etc.) • Expensive
- 19. Digital Signal Processors • Examples: TMS320F240, TMS320F2407, TMS320VC33, DSP56300, ADSP2100 • Often, multiple instructions per clock cycle • 24- and 32-bit processors have multiple instructions in one word • Single instruction may be sufficient to perform a given operation • CPU is designed for computation-intensive jobs (fixed / floating point) • Relatively small program memory requirement • On-chip bootloader; instruction cache • Relatively low to medium cost
- 20. DSP Microcontrollers • Examples: TMS320F240, TMS320F243, TMS320F2407, DSP56800 • Combination of DSP and Microcontroller • Often, multiple instructions per clock cycle • Typically, 16 bit data and instructions • CPU is designed for computation-intensive jobs • Rich set of on-chip peripherals (ADCs, I/O ports, Flash memory etc.) • 5 V as well as 3.3 V processors are on the market • Relatively low to medium cost • Reasonably good set of software development tools
- 21. TMS320F240 DSP Schematic Diagram
- 22. TMS320F240 DSP Microcontroller Summary • 16-bit fixed point DSP with 50 ns instruction cycle • Good for closed loop control applications • On-chip PLL for 20 MHz internal clock generation • 16 k x 16 internal Flash Memory Module • 2 x 8 analog input channels to 10 bit ADC • Three 16-bit general purpose timers • Very rich interrupt structure • PWM generation • 132 pin PQFP package
- 23. TMS320VC33 DSP Schematic Diagram SPRS087D – FEBRUARY 1999 – REVISED JULY 2002 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 functional block diagram 24 Boot Loader Cache (64 × 32) RAM Block 0 (1K × 32) RAM Block 1 (1K × 32) RDY HOLD HOLDA STRB R/W D31–D0 A23–A0 RESET CPU1 REG1 REG2 MUX 40 32 32 32 32 32 32 32 24 24 24 24 BK ARAU0 ARAU1 DISP0, IR0, IR1 Extended- Precision Registers (R7–R0) Auxiliary Registers (AR0–AR7) Other Registers (12) 40 40 40 40 Multiplier 32-Bit Barrel Shifter ALU DMA Controller Global-Control Register Source-Address Register Destination- Address Register Serial Port 0 Serial-Port-Control Register Receive/Transmit (R/X) Timer Register Data-Transmit Register Data-Receive Register FSX0 DX0 CLKX0 FSR0 DR0 CLKR0 Timer 0 Global-Control Register Timer-Period Register Timer-Counter Register TCLK0 Timer 1 Global-Control Register Timer-Period Register Timer-Counter Register TCLK1 Port Control STRB-Control Register Transfer- Counter Register PDATA Bus PADDR Bus DDATA Bus DADDR1 Bus DADDR2 Bus DMADATA Bus DMAADDR Bus 24 40 32 32 24 24 32 INT(3–0) IACK MCBL/MP XF(1,0) 32 24 24 24 24 32 32 32 CPU2 32 32 40 40 Peripheral Data Bus CPU1 REG1 REG2 RAM Block 2 (16K × 32) 24 32 RAM Block 3 (16K × 32) 24 32 MUX Peripheral Address Bus XOUT XIN H1 H3 PAGE0 PAGE1 PAGE2 PAGE3 Peripheral Data Bus TDI TDO TCK EMU0 EMU1 TMS TRST MUX EDGEMODE Controller PLL CLK JTAG Emulation IR PC RSV(0,1) SHZ CLKMD(0,1) EXTCLK
- 24. TMS320VC33 Floating Point DSP Summary • 32-bit floating point DSP with 13 ns instruction cycle • Good for computation intensive embedded control applications • On-chip PLL for 75 MHz internal clock generation • 34K x 32-bit on-chip RAM • On-chip program bootloader • 32-bit instruction word • 24-bit address space • Two 32-bit timers • Eight 40-bit extended precision registers • Parallel instructions
- 25. The Tasks of an Assembler • Convert assembly language code into machine binary code. Example: mpy #254 1100000011111110 • Handle symbolic information. Example: Start: mpy #254 bcnd Start, LT add #1 bcnd End, GT add #1 End: b Start • Handle expressions in operands. Example: b (Label + (0x10 * 1011b)) • Handle sections. Example: .sect ‘‘vectors’’
- 26. The Tasks of an Assembler - continued ... • Handle external references. Example: .ref ext1 ; ext1 is defined in another file . . . . . . add ext1 ; ext1 is used in this file, unknown value • Handle macro substitution. Example: S2E .macro qs,ds,cos,sin,qe,de lt qs mpy cos ltp ds mpy sin mpya cos sach qe ltp qs mpy sin spac sach de .endm
- 27. The Tasks of an Assembler - concluded • Handle relocation information. Example: b Label ; A relocation entry is created for this line. • Report errors. Example: add %!*#$@ ; Causes an error message • An assembler usually creates an object file (extension .obj), which contains unre- solved externals, and internal symbol information for other object modules. • An object file has relocation entries for each section. • Texas Instruments DSP software tools usually create object files in the Common Object File Format (COFF). • A linker connects all the object files by: – joining up sections from different files, – resolving all symbolic references, – performing relocations, – creating absolute code. • The final linked code file has no unresolved symbolic references, and no relocation information.
- 28. The Code Development Process Assembler Assembler To Target System Loader a1.asm aN.asm a1.obj aN.obj Linker a.out a.cmd • The entire application is usually spread among several source .asm files. • This facilitates teamwork and code maintenance. • The linker links all object files to make the final absolute executable file .out. • The .cmd file contains the memory map of the target system. • The .obj and the .out files often have the same file format. These include: – Common Object File Format (COFF), – Executable and Linking Format (ELF). • TI DSP software tools currently support COFF. Motorola supports ELF.
- 29. Sections • A section is the basic structural unit of assembly language code. • A section typically contains program or data code. Example: Start .text ; Program code section b Init DSP . . . .data ; Initialised data section .word 0x7fff, 08000h, 1011001b . . . • Usually there are three default sections: .text, .data and .bss. • Named sections can also be defined by users. Example: .sect ‘‘vect table’’ Int0 b INT0 Int1 b INT1 . . . • The linker combines section code across different files.
- 30. COFF File Structure • File headers • Section headers • Section raw data • Section relocation information • Section line numbers • File symbol table • String table to hold long symbol names • All TI COFF versions have the same for- mat but different structure sizes. • TI COFF comes in three versions: COFF0, COFF1 and COFF2. • COFF was used in the Unix System V. section 1 raw data section n raw data section 1 reloc info section n reloc info section 1 line nos. section n line nos. file header optional file header section 1 header section n header symbol table string table
- 31. File Header • COFF 0: 20 bytes long ; COFF 1 and COFF 2: 22 bytes long • Target DSP ID • Number of section headers • Time and date stamp of file creation • Symbol table file pointer • Number of entries in the symbol table • Flags – File executable or not (unresolved references?) – File has reloc information or not – Byte ordering: Little Endian - Object data LSB first Big Endian - Object data MSB first
- 32. Section Headers • COFF 0 and COFF 1: 40 bytes long ; COFF 2: 48 bytes long • Section name and its address in the system memory • File pointer to section raw data • File pointer to the section s relocation entries • Number of relocation entries in the section • By default, section headers are always created for the .text, .data and .bss sections • Section names for all user defined sections created with the .sect directive are sig- nificant to 8 characters
- 33. Section Relocation Entries • A relocation entry is created when the assembler encounters a symbol used as an argument of an assembly language instruction. Example: .global Label2 .text . . . b Label1 ; This will generate a reloc entry. . . . . . . Label1 nop and Data1 ; This will generate a reloc entry. b Label2 ; This will generate a reloc entry. .data Data1 .word 0123h • The reloc entry specifies the virtual address, the symbol table index, and the reloc type (7 LSBs of address, 9MSBs of address, 16 bit address, ...).
- 34. The COFF Symbol Table • The symbol table appears at the end of the COFF file, followed by the string table. • Each symbol table entry is 18 bytes long. • Each entry contains information on: – The symbol name. – The symbol value. – The section ID of the symbol. – The symbol type (integer, float, double, character, pointer, array, ...) – The symbol storage class (static, automatic, external, label, ...) • Symbol names can have any length. If a name is longer than eight characters, then the symbol name entry contains a pointer into the String Table, which contains the characters that make up the symbol name. • By default, all section names and global symbols are entered into the COFF symbol table. Local symbols are not entered.
- 35. The acoff Utility • The acoff utility reads a TI COFF file and displays its contents. • It supports TI COFF versions 0, 1 and 2. Version detection is automatic. • It can also be used to extract the binary executable raw data from a COFF file, for use with a disassembler. • It supports various options for formatting the extracted data. • Usage: acoff [-ablrs] [coff filename] a: print all information. b: print binary executable data. l: print relocation entries. r: print raw data from all sections. s: print the symbol table entries. Default: print headers only.
- 36. Assembler Passes • An assembler makes two passes. • In Pass 1, it creates an internal symbol table. – Symbols specified with a .global, .def or .ref directive are entered into this table. – All labels are also entered into the internal symbol table. The value given to each label is the value of the section program counter at that point. – It calculates the lengths of various sections. – It calculates the values of the file pointers. • In Pass 2, the assembler actually generates assembly code. – It recognises opcodes and operands. – It retrieves symbol values and evaluates expressions. – It forms the machine binary code and writes it to the output COFF file. – It writes the reloc entries, the symbol table and the string table to the COFF file.
- 37. Assembling Process: Example .text clrc INTM ; SPCt = 0 addc *, ar0 ; SPCt = 1 bcnd L2+(21), LT ; SPCt = 2 mac L2, 2 ; SPCt = 4 lacc L3, 9 ; SPCt = 6 .data x .word 0xa, 0eh ; SPCd = 0 .word 10100b ; SPCd = 2 .word x ; SPCd = 3 .text ; SPCt = 6 L2 neg ; SPCt = 7 L3: cmpl ; SPCt = 8 .data ; SPCd = 3 y .word 0x4 ; SPCd = 4 • Pass 1 fills up the internal symbol table, and checks the syntax of the program. • Pass 2 uses the symbol informa- tion, considers the program seman- tics. • At any time during assembly, there is one active section, and its pro- gram counter is active. • In this example, SPCt is the pro- gram counter for the .text sec- tion. • SPCd is the program counter for the .data section.
- 38. Schematic Layout of Digital Processor Control Hardware ADC Processor I/O Ports Memory Motor Drive
- 39. Number Representations on Fixed Point Processors • ADC outputs need to be represented properly in a processor • Control system variables need to be represented properly • Typically 16, 24 or 32 bit numbers • Need to represent positive and negative numbers • Signed integer and signed fraction representations are the most common
- 40. Sixteen-bit Signed Integers • The 2’s complement notation is used to represent signed integers • Positive numbers: Represent directly as binary numbers • Negative numbers: Take the simple complement and add 1 Example: +3 0000 0000 0000 0011 Example: -3 0000 0000 0000 0011 → 1111 1111 1111 1100 → 1111 1111 1111 1101 • Negative numbers start with an MSB of 1 • Positive numbers start with an MSB of 0 • Number range: – Most positive number is +215 − 1 = +32767 – Most negative number is −215 = −32768 – Number range: 65535
- 41. Operations with 16-bit 2’s Complement Numbers • Addition: Binary addition 0000 0000 0000 0011 + 0000 0000 0000 0011 = 0000 0000 0000 0110 • Subtraction: Binary addition with 2’s complement (The carry bit is discarded) 0000 0000 0000 0011 + 1111 1111 1111 1101 = 0000 0000 0000 0000 • Multiplication: The result is a 32-bit signed integer 0x0003 × 0xfffd = 0xfffffff7 • The results of multiplications cannot always be stored in the 16-bit number range 0x012c × 0x012c = 0x00015f90 (300 × 300 = 90000)
- 42. Signed Fraction Representation with 16-bit Numbers • Use the 16-bit range to represent signed fractions in the range -1 to 1 • An imaginary decimal point is placed between bit 15 and bit 14. The MSB indicates the sign and the remaining 15 bits represent the fraction • This is the Q-15 fractional format • Signed decimal fraction to Q-15 conversion: – Multiply the fraction with the scaling factor 215 = 32768 – Convert the resulting integer to hexadecimal – If the fraction is negative, take the 2’s complement of the hex number • Example: +0.25: +0.25 × 32768 = 08192 → 0x2000 -0.50: +0.50 × 32768 = 16384 → 0x4000 → 0xc000 • The resolution of the fractional numbers is 2−15 ≈ 0.00003051757 • To convert a Q-15 number to its fractional value, reverse the procedure given above
- 43. Operations with Q-15 Numbers • Addition: Hex addition 0x2000 + 0x2000 = 0x4000 (0.25 + 0.25 = 0.50) • Subtraction: Hex addition with 2’s complement 0x2000 + 0xc000 = 0xe000 (0.25 − 0.50 = −0.25) • Need to be careful of overflows and underflows 0x6000 + 0x6000 = 0xc000 (0.75 + 0.75 = −0.5 ???) • Many processors have an “overflow mode” which prevents the result of an addition or subtraction from going beyond 0x7fff and 0x8000 respectively • Overflows and underflows can be handled by software • But it is better to avoid them in the first place 0.1 × (0.5 + 0.7) = 0.05 + 0.07 and not 0.1 × 1.2
- 44. Operations with Q-15 Numbers – cont’d • Multiplication: The multiplication of two Q-15 numbers results in a Q-30 number. Consider two decimal fractions x and y. Their multiplication z0 is z0 = (x × 215) × (y × 215) = xy × 230, which is the Q-30 representation of the desired fractional result z = xy. To get the Q-15 representation of the result, it is necessary to multiply z0 as follows. z × 215 = z0 × 2−15 That is, z0 needs to be shifted right by 15 bits. Equivalently, we may shift z0 left by one bit, and take the most significant 16 bits of the resulting number to be the Q-15 representation of the result z; this is the preferred method. Formula: Multiply two Q-15 numbers, shift the 32-bit result left by one bit and take the most significant 16 bits to get the Q-15 result Example: 0x4000 × 0x6000 = 0x18000000 → 0x30000000 → 0x3000 (0.5 × 0.75 = 0.375)
- 45. Floating Point Number Representation s 23 0 22 24 31 exponent (e) fraction (f) e: 8-bit exponent field, contains signed 2’s complement integer s: Sign bit f: Fractional part of the mantissa x: Floating point number • If s = 0: x = 01.f × 2e • If s = 1: x = 10.f × 2e • Example: +1.7 × 101 +17 = 0.01f × 2e, s = 0 +17 = 01.0625 × 16 e = 4 and f = 00010000000000000000000 x = 0000 0100 0000 1000 0000 0000 0000 0000 = 0x04080000
- 46. 32-bit Floating Point Number Range • Most positive number: 0x7f7fffff = +3.4028234× 1038 • Least positive number: 0x81000000 = +5.8774717× 10−39 • Most negative number: 0x7f800000 = −3.4028236× 1038 • Least negative number: 0x81ffffff = −5.8774724× 10−39
- 47. TMS320VC33 Description • Memory map • Bootloader • Interrupts • Addressing modes
- 48. TMS320VC33 Interrupt Processing • Five interrupts from internal peripherals • Four external interrupts from pins Microcomputer mode: Name Address Priority Function INT0 0x809fc1 1 External on pin /INT0 INT1 0x809fc2 2 External on pin /INT1 INT2 0x809fc3 3 External on pin /INT2 INT3 0x809fc4 4 External on pin /INT3 XINT0 0x809fc5 5 Serial port XMT buffer empty RINT0 0x809fc6 6 Serial port RCV buffer full TINT0 0x809fc9 7 Timer0 interrupt TINT1 0x809fca 8 Timer1 interrupt DINT 0x809fcb 9 DMA controller interrupt
- 49. TMS320VC33 Interrupt Behaviour • Three CPU registers associated with interrupt processing. 1. Status register (ST) 2. Interrupt Enable register (IE) 3. Interrupt Flag Register (IF) • The Global Interrupt Enable (GIE) bit in the ST has to be set for interrupts to be enabled (upon CPU reset it is cleared) • The individual interrupt enable bit has to be set in the IE (interrupts are disabled upon CPU reset) • When an interrupt is recognised, the corresponding IF bit is set • The IF bits may be polled or written to by user programs
- 50. Interrupt Handling Upon recognising an interrupt the CPU does the following in sequence 1. Disable interrupts (0 → GIE) 2. Clear the proper IF bit 3. PC → *(++SP) 4. (Interrupt vector) → PC • The user program must re-enable interrupts • If the interrupt service routine (ISR) needs to be interruptible, interrupts may be re- enabled upon entry into the ISR
- 51. TMS320VC33 Addressing Modes • How are operands of instructions addressed? • Operand addresses are 24 bits long • There are five main addressing modes: 1. Register addressing: A CPU register contains the operand 2. Direct addressing: A part of the operand’s address is contained in the instruction 3. Indirect addressing: An auxiliary register contains the operand’s address 4. Immediate addressing: The operand is contained within the instruction 5. PC-relative addressing: The instruction contains a displacement to the program counter
- 52. Addressing Modes • Register addressing: A CPU register contains the operand – Example: absi R0 • Direct addressing: The Data Page Pointer (DP) contains A23 – A16 The instruction contains A15 – A0 The processor concatenates the DP and the instruction fields – Example: ldp @cos ldf @cos, R0
- 53. Addressing Modes • Indirect addressing: An auxiliary register contains the operand address • AR modification is possible in the same instruction – Example: stf R0, *+AR7(1) ; address = AR7 + 1 stf R0, *-AR7(1) ; address = AR7 - 1 stf R0, *++AR7(2) ; address = AR7 + 2, AR7 = AR7 + 2 stf R0, *--AR7(2) ; address = AR7 - 2, AR7 = AR7 - 2 stf R0, *AR7++(3) ; address = AR7, AR7 = AR7 + 3 stf R0, *AR7--(3) ; address = AR7, AR7 = AR7 - 3 • All of the above are also possible using a displacement contained in the Index Reg- isters IR0 and IR1 – Example: stf R0, *+AR7(IR0) ; address = AR7 + IR0 stf R0, *AR7--(IR1) ; address = AR7, AR7 = AR7 - IR1
- 54. Addressing Modes • Immediate addressing: The operand is contained in the instruction • May be a 16-bit (short immediate format) operand – Example: addi 1, R0 mpyf 2.4e-2, R0 • May be a 24-bit (long immediate format) operand – Example: call 0x80107 • PC-relative addressing: Used for branching. A signed 16-bit or 24-bit displacement is contained in the instruction. This is added to the PC. – Example: label: nop bz label1 ; 16-bit displacement br label1 ; 24-bit displacement
- 55. Non-sinusoidal Input Currents a b c Ias • The line current is non-sinusoidal. • The line-line voltage is notched. • Problems for other loads connected to a, b, c terminals. 0.18 0.19 0.2 0.21 0.22 −1000 −500 0 500 1000 Vab 0.18 0.19 0.2 0.21 0.22 −1000 −500 0 500 1000 Ias
- 56. The Harmonics Problem 0 0.005 0.01 0.015 0.02 −2 −1 0 1 2 h1 + h5/5 + h7/7 h1 h1 + h5/5 • Peak current is higher than fundamental. • (Only fundamental current transfers real power). • Voltage distortion at Point of Common Coupling (PCC). • Transformer losses. • Cable losses.
- 57. Mitigating the Harmonics Problem: Active Filtering Thyristor Converter b c a 3 Phase AC System i1 i1 + ih ih • The power electronic converter is operated to provide harmonic currents to the load. • The ac source pro- vides only the funda- mental component of the load current. • The same circuit can be used for reactive power compensation. • Real time digital sig- nal processing is used to extract the har- monic components ih from the load current.
- 58. Unbalanced Non-sinusoidal Currents • Input: Unbalanced three phase sig- nals. • The fundamental component as well as the harmonics are unbal- anced. • Example: Single phase traction supply derived from three phase distribution system. • Task: To extract the sequence com- ponents for the fundamental and the harmonics. • This task has to be done in real time on a DSP system. • One way to do this is to use refer- ence frame transformations. ia ib ic 1999/04/10 17:22:54 YOKOGAWA NORM: 200k S/s **** Filter SMOOTH OFF BW FULL **** Offset CH1 0.0V CH2 0.000 V CH3 0.000 V CH4 0.00V **** Record Len MAIN: 10K ZOOM: 10K **** Delay 0.000 00s **** Hold Off MIN **** Trigger AUTO EDGE CH4 5ms/div CH1 500V DC 100:1 1 CH3 5V DC 10:1 3 CH4 50V DC 10:1 4 Freq(1) 50.05Hz
- 59. Transformation to a Stationary Reference Frame fq fd f0 = 2 3 1 cos −2π 3 cos +2π 3 0 sin −2π 3 sin +2π 3 1 2 1 2 1 2 fa fb fc • fa, fb and fc are the instantaneous a, b and c phase quantities. • fq, fd and f0 are the transformed quantities. • We consider cases in which fa + fb + fc = 0. In this case, fq = fa fd = (fc − fb)/ √ 3 • Vector representation: F̄ = (fq, fd) • Complex number representation: F̄ = fq − jfd a q Re F d Im c b
- 60. Transformation Example Measured: θ = ωt fa = cos (θ) fb = cos (θ − 2π/3) fc = cos (θ + 2π/3) Transformed: fq = + cos θ fd = − sin θ Complex number: F̄ = cos θ + j sin θ F̄ = ejθ The vector F̄ rotates anti-clockwise with an angular velocity of ω. F q Re d Im ω Transformation from abc to dq0
- 61. Transformation to a Rotating Reference Frame Transformation: ¯ Fe = F̄e−jθe θe = ωet Example: F̄ = cos θ + j sin θ F̄ = ejθ Transformed: ¯ Fe = ej(θ−θe) If θ = θe for all time, then ¯ Fe = 1 + j0 In the rotating reference frame, ¯ Fe is a con- stant vector. Transformation back to the stationary refer- ence frame is achieved by F̄ = ¯ Fee+jθe qe F ωe de q Re d Im ω Transformation equations: fe q = fq cos ωet − fd sin ωet fe d = fq sin ωet + fd cos ωet
- 62. Summary of Transformation Equations • a-b-c to stationary q-d: fq = fa fd = (fc − fb)/ √ 3 • TMS320VC33 macro code: isqrt3 .float 0.5773502 ABC2S .macro a,b,c,qs,ds ldf a,r0 stf r0,qs ldf c,r0 subf b,r0 mpyf @isqrt3,r0 stf r0,ds .endm • Stationary q-d to a-b-c: fa = fq fb = −1 2fq − √ 3 2 fd fc = −1 2fq + √ 3 2 fd • Assumptions: fa + fb + fc = 0 ; θe = R ωedt • Stationary q-d to rotating qe-de: fe q = fq cos θe − fd sin θe fe d = fq sin θe + fd cos θe • TMS320VC33 macro code: S2EP .macro qs,ds,cos,sin,qe,de ldf qs,r0 ;r0=qs ldf ds,r1 ;r1=ds ldf cos,r2 ;r2=cos ldf sin,r3 ;r3=sin mpyf3 r2,r0,r4 ;r4=cos*qs mpyf3 r3,r1,r5 ;r5=sin*ds subf r5,r4 ;r4=cos*qs-sin*ds stf r4,qe ;store qe mpyf3 r3,r0,r4 ;r4=sin*qs mpyf3 r2,r1,r5 ;r5=cos*ds addf r5,r4 ;r4=sin*qs+cos*ds stf r4,de ;store de .endm • Rotating qe-de to stationary q-d: fq = +fe q cos θe + fe d sin θe fd = −fe q sin θe + fe d cos θe
- 63. Example: Balanced Currents with Fifth Harmonic • Input: ia = a1 cos ωt + a5 cos 5ωt ib = a1 cos (ωt − 2π/3) + a5 cos 5(ωt − 2π/3) ic = a1 cos (ωt + 2π/3) + a5 cos 5(ωt + 2π/3) • Stationary ref. frame transformation: iq = +a1 cos ωt + a5 cos 5ωt id = −a1 sin ωt + a5 sin 5ωt ¯ I = iq − jid = a1ejωt + a5e−j5ωt • The fundamental vector rotates anit- clockwise. The 5th harmonic vector rotates clockwise. • The total current vector is the sum of the fun- damental and 5th harmonic vectors. −1.5 −0.5 0.5 1.5 −1.5 −0.5 0.5 1.5 5ω ω q d The figure shows the vector loci for a1 = 1 and a5 = 1/5. The vectors are shown at ωt = π/4.
- 64. Example: Unbalanced Currents Measured currents: ia = α cos (ωt) ib = cos (ωt − 2π/3) ic = −(ia + ib) Transform to stationary reference frame: iq = α cos (ωt) id = (1−α) √ 3 cos (ωt) − sin (ωt) ¯ I = iq − jid Vector representation: ¯ I = ¯ I+e+jωt + ¯ I−e−jωt ¯ I+ = (1+α) 2 − j (1−α) 2 √ 3 ¯ I− = −(1−α) 2 − j (1−α) 2 √ 3 The current vector ¯ I is composed of two components, ¯ I+ rotating anti-clockwise and ¯ I− rotating clockwise, with the angular veloc- ity ω. ω ω −1.1 0 1.1 −1.1 0 1.1 The figure shows the vector loci for α = 0.5. The vectors are shown at t = 0.
- 65. Extraction of Fundamental and Harmonic Components • Example input: ia = a1 cos ωt + a5 cos 5ωt ib = a1 cos (ωt − 2π/3) + a5 cos 5(ωt − 2π/3) ic = a1 cos (ωt + 2π/3) + a5 cos 5(ωt + 2π/3) • We want to extract the value of a1. • Stationary ref. frame transformation: iq = +a1 cos ωt + a5 cos 5ωt id = −a1 sin ωt + a5 sin 5ωt ¯ I = iq − jid = a1ejωt + a5e−j5ωt • Transformation to +ω ref. frame: ¯ Ie +1 = ¯ Ie−jωt = a1 + a5e−j6ωt ie q = a1 + a5 cos (6ωt) ie d = a5 sin (6ωt) • Low pass filter: e q1 i = a1 i q e i e d e i = 0 d1 • Rotating +ω to stationary ref. frame: iq1 = +a1 cos (ωt) id1 = −a1 sin (ωt) • Stationary ref. frame to abc: ia1 = a1 cos (ωt) ib1 = a1 cos (ωt − 2π/3) ic1 = a1 cos (ωt + 2π/3) • The 5th harmonic component is extracted similarly by transforming and filtering in the −5ω rotating reference frame.
- 66. Extraction of Unbalance Components • Example input: ia = α cos (ωt) ib = cos (ωt − 2π/3) ic = −(ia + ib) • Transform to stationary reference frame: iq = α cos (ωt) id = (1−α) √ 3 cos (ωt) − sin (ωt) ¯ I = iq − jid • Vector representation: ¯ I = ¯ I+e+jωt + ¯ I−e−jωt = ¯ Ip + ¯ In ¯ I+ = (1+α) 2 − j (1−α) 2 √ 3 ¯ I− = −(1−α) 2 − j (1−α) 2 √ 3 • Transform to +ω and −ω ref. frames: ¯ Ie +1 = ¯ Ie−jωt = ¯ I+ + ¯ I−e−j2ωt ¯ Ie −1 = ¯ Ie+jωt = ¯ I+e+j2ωt + ¯ I− • Low pass filtering of ¯ Ie +1 yields ¯ I+. • Low pass filtering of ¯ Ie −1 yields ¯ I−. • Transform ¯ I+ from +ω frame to station- ary frame yields the positive sequence vector ¯ Ip. ¯ Ip = ¯ I+e+jωt • Transform ¯ I− from −ω frame to station- ary frame yields the negative sequence vector ¯ In. ¯ In = ¯ I−e−jωt • Transforming ¯ Ip to the a-b-c reference frame yields the positive sequence cur- rent components. • Transforming ¯ In to the a-b-c reference frame yields the negative sequence cur- rent components.
- 67. Summary of Component Extraction Method • Measure currents ia, ib and ic. • Transform them to the stationary d-q reference frame to get the stationary frame current vector. • Transform the current vector to all appropriate rotating reference frames. • Pass the transformed vectors through low pass filters. • Transform the filtered quantities back to the stationary reference frame. • Calculate the positive and negative sequence components. Question: How to obtain the values of cos mωt and sin mωt needed for transformations to the rotating reference frames? Answer: Implement a harmonic oscillator on a DSP.
- 68. Harmonic Oscillator Implementation • Oscillator equations: ẋ = +ωy x(0) = 0 ẏ = −ωx y(0) = 1 • This gives: x = sin ωt y = cos ωt • Discrete time system: xn+1 = xn + ω∆T × yn x0 = 0 yn+1 = yn − ω∆T × xn+1 y0 = 1 • ∆T is the time step with which these dis- crete time equations are solved. • ω, the desired angular frequency, is the input to the oscillator. • ω need not be constant. • TMS320VC33 assembly code: ldf @sin,r0 mpyf @wdt,r0 negf r0,r0 addf @cos,r0 stf r0,@cos mpyf @wdt,r0 addf @sin,r0 stf r0,@sin • This code is executed every ∆T sec- onds. • The input to the code is ω∆T. • The asymmetry in the discrete time equations is for reasons of stability. • Higher (harmonic) frequency oscilla- tions are obtained by multiplying ω∆T with the harmonic number m.
- 69. Sine and Cosine Wave Generation • The frequency ω is ramped up at a constant rate. • The time step ∆T = 20µs. • The result is a sine wave and a cosine wave of continuously increasing frequency. • In DSP implementation, ω∆T can be the output of a PLL syn- chronised with the line voltage. • Initialisation: Write 1.0 in the memory location for cos, and 0.0 in the memory location for sin. 0 0.02 0.04 0.06 0.08 0.1 −2 −1 0 1 2
- 70. Oscillator Synchronisation • Due to quantisation error, the oscillators for the har- monic frequencies tend to drift relative to the funda- mental frequency oscillator. • For higher order harmonics, the drift is higher. • All oscillators are synchronised at the zero crossings of the fundamental sine wave. • This involves re-initialising all sine values to zero, and all cosine values either to -1 or +1. 0 0.005 0.01 0.015 0.02 −2 −1 0 1 2 Fundamental, 3rd and 5th sine and cosine waves • TMS320VC33 code: ldf @sin 1,r0 absf r0 cmpf 0.008,r0 bp over reset subf r0,r0 stf r0,@sin 3 stf r0,@sin 5 stf r0,@sin 7 stf r0,@sin 9 ldf @cos 3,r0 ldfp 1.0,r0 ldfn -1.0,r0 stf r0,@cos 3 stf r0,@cos 5 stf r0,@cos 7 stf r0,@cos 9 over reset:
- 71. First Order Low Pass Filter s τ 1 + − y u • Transfer function: y(s) u(s) = 1/(1 + sτ) • Discrete time implementation: yn+1 = yn + ∆T τ (un − yn) • TMS320VC33 code: ldf @u,r0 subf @y,r0 mpyf @k,r0 addf @y,r0 stf r0,@y 0 0.02 0.04 0.06 0.08 0.1 0 100 200 300 400 500 u y ∆T = 20µs, τ = 10ms, k = ∆T/τ = 0.002
- 72. Oscillograms from DSP Implementation 1999/04/10 17:59:11 YOKOGAWA 10ms/div CH1 500V DC 100:1 1 CH3 5V DC 10:1 3 Freq(1) 50.00Hz Freq(3) 50.00Hz • Oscillogram shows input phase current ia, and its reconstruction from its components. • The original three phase current set has unbalanced fundamental and also unbalanced harmonics. • The positive and negative sequence sets for the fundamental and harmonics upto the 9th are extracted. • All components are added to make the reconstruction. 1999/04/10 17:43:45 YOKOGAWA 5ms/div CH1 200V DC 100:1 1 CH2 2V DC 10:1 2 CH3 2V DC 10:1 3 CH4 20V DC 10:1 4 Freq(1) 50.19Hz Freq(2) 419.3Hz Freq(3) 49.99Hz Freq(4) 250.6Hz • Oscillogram shows input phase current ic, and its extracted components. • The fundamental component is superimposed on the actual current. The fundamental is reconstructed by adding its extracted positive and negative sequence components. • The lower traces show the 5th and 9th harmonic components, reconstructed by adding their respective positive and negative sequence components.
- 73. Basic Phase Locked Loop Phase Detector Input− Controlled Oscillator u Filter y ε x N • Aim: To obtain the output y which has the same frequency as the input u, and has a constant phase relative to u. • The signal x is obtained by filtering the phase error . • The value of x determines the frequency of y. • The signal x represents the frequency of u. • Feature: if the frequency of y is divided by N before feeding to the phase detector, then this will be N times the frequency of u.
- 74. PLL Implementation with XOR Gate XOR VCO y u x ε u y ε x • The phase detector is an exclusive OR (XOR) gate. • The filter is an RC circuit. • The oscillator is a voltage controlled oscillator (VCO). • The input u and output y have the same frequency. • The output y lags u by π/2. • We want sinusoidal inputs and outputs.
- 75. PLL Implementation with a Harmonic Oscillator XOR Harmonic oscillator ZCD ZCD ω cos t ω sin t u y ε ω 0 0.5 1 1.5 2 0 100 200 300 400 500 ω 1.802 1.812 1.822 1.832 1.842 −2 −1 0 1 2 u y u and y • All components of the PLL can be implemented on a DSP system. • The output sin ωt of the harmonic oscillator lags the input u by π/2.
- 76. Three Phase PLL • Three phase PLL usage examples: – Frequency measurements. – Three phase static VAr compensators. – Voltage sag compensators. – Unbalance measurements. – Harmonic extraction. – Active filters. • The PLL should use information from all three phases. • It should operate in the presence of unbalances and harmonics. • It should preferably not operate on the basis of zero crossings. • It should have a specified dynamic response. • We make use of reference frame transformations to implement a PLL.
- 77. Example: PLL for Balanced Sinusoidal Voltages • Measured: fa = cos ωt fb = cos (ωt − 2π/3) fc = cos (ωt + 2π/3) • Transformations: fq = + cos ωt fd = − sin ωt F̄ = cos ωt + j sin ωt = ejωt F̄e = ej(ω−ωe)t 0 0.02 0.04 0.06 0.08 0.1 −2 −1 0 1 2 fqe in 50 Hz ref. frame fde in 50 Hz ref. frame fqe in 45 Hz ref. frame fde in 45 Hz ref. frame qe F ωe de q Re d Im ω • Aim of the PLL: Find that rotating reference frame in which fe d = 0 and fe q is a constant. • Find the angular frequency ωe un- der closed loop control.
- 78. Three Phase PLL Implementation abc to qd qe−de to qd PI Reg. ω e ator Oscill− ε d ω e t sin ω e cos t q d qe 0 + c b a de − ce se ωe 0 0.1 0.2 0.3 0.4 0.5 0 100 200 300 400 εd 0 0.1 0.2 0.3 0.4 0.5 0 0.1 0.2 0.3 0.4 0.5 Simulator code for PLL (∆T = 20µs): /* Input Transformation */ s = integ(s, ws*c); c = integ(c, -ws*s); q = c; d = -s; /* Rotating frame */ se = integ(se, we*ce); ce = integ(ce, -we*se); qe = (q * ce) - (d * se); de = (q * se) + (d * ce); /* omega e controller */ err d = -de; we p = kp * err d; we i = integ(we i, ki*err d); we = we p + we i;
- 79. Three Phase PLL Dynamic Equations • The PLL can be modeled as follows. ṡe = +ωece ċe = −ωese ω̇e = {kp(−q̇ + ωed) − kiq}se − {kp( ˙ d + ωeq) + kid}ce • kp and ki are the P-I controller proportional and integral gains. • This is a nonlinear system of equations. • It can be modelled in the discrete time system simulator.
- 80. Three Phase PLL with Arbitrary Phase Angle abc to qd qe−de to qd PI Reg. ω e ator Oscill− ε d ω e t sin ω e cos t q d qe + c b a de − ce se F • Calculate set point F: F = −( p q2 + d2) × sin δ • This involves evaluating a square root and a sine function. • This is computationally intensive. How- ever, these functions can be evaluated on modern DSPs. • It is desirable to make δ = 0 if possible. F de ωe qe δ q Re d Im ω F
- 81. PLL Operation with Unbalanced Inputs abc to qd qe−de to qd ω e t sin ω e cos t ε d PI Reg. ator Oscill− ce se ω e ω ef + − ω ef q d c b a qe de 0 • Inputs: a = α cos (ωt) b = cos (ωt − 2π/3) c = −(a + b) • Aim: To lock the PLL with the positive sequence component of the fundamen- tal component of the input. • A strong second harmonic component is present in fe d due to the fundamental negative sequence component. • Pass fe d through a low pass filter to re- move the second harmonic component. ω ω −1.1 0 1.1 −1.1 0 1.1 The figure shows the vector loci for α = 0.5. The vectors are shown at t = 0.
- 82. Simulation: PLL Operation with Unbalanced Inputs abc to qd qe−de to qd ω e t sin ω e cos t ε d PI Reg. ator Oscill− ce se ω e ω ef + − ω ef q d c b a qe de 0 0 0.1 0.2 0.3 0.4 0.5 −100 0 100 200 300 400 α = 0.5 α = 1 PLL frequency ωef , for α = 1.0 and α = 0.5. The input frequency is ω = 314.15 rs−1. Simulator code for PLL (∆T = 20µs): q = fa; d = (fc - fb)/sqrt(3); qe = (q * ce) - (d * se); de = (q * se) + (d * ce); de f = integ(de f, k f*(de-de f)); err d = -de f; we p = kp * err d; we i = integ(we i, ki*err d); we = we p + we i; se = integ(se, we*ce); ce = integ(ce, -we*se); we f = integ(we f, k w*(we - we f));
- 83. Example: Unbalanced Fundamental and Harmonics 0.15 0.16 0.17 0.18 0.19 0.2 −2 −1 0 1 2 fa fb fc 0.4 0.42 0.44 0.46 0.48 0.5 −2 −1 0 1 2 fa cos sin ωef 0 0.1 0.2 0.3 0.4 0.5 −100 0 100 200 300 400 • The harmonics as well as the fundamental are unbalanced. • The PLL locks to the positive sequence com- ponent of the fundamental component. • The signals sin and cos can be used to ef- fect rotation transformations that are syn- chronised with the fundamental positive se- quence component.
- 84. Integration Instances • PI regulators. • Discrete time implementations of continuous time filters. • Integration of discretised dynamic plant models in sensorless control. • Real time simulation on DSP platforms. • The basic question: If the state vector of a system, and the vector of derivatives of the states, is known at the discrete time point t(n), what will the state of the system be at the discrete time point t(n + 1) = t(n) + ∆T? • In most power electronics applications, the interval ∆T is constant. • In multirate systems, there are several (constant) time intervals.
- 85. Example: First Order Low Pass Filter s τ 1 + − y u y(s) u(s) = 1/(1 + sτ) • Known at time point t(n): Input u(n). Output y(n). Derivative (u(n) − y(n))/τ. • Calculate at time point t(n + 1): Output y(n + 1). One method to calculate the output is Euler’s explicit integration method.
- 86. Euler’s Explicit Method yi T ∆ t(1) t t(4) t(3) t(2) • System of N first order ODEs: ẏi = fi(t, y1, . . . , yN ), i = 1 . . . N yi(n + 1) = yi(n) + hfi(t(n), y1(n), . . . , yN (n)) • h = ∆T is the (constant) time step. • The derivatives are calculated only at the start of the interval. • Since all yi(n) are known at time point t(n), the derivatives fi can be calculated explicitly. • The method has first order accuracy. The error is proportional to ∆T. • Not suitable for stiff systems unless ∆T is much smaller than the fastest tran- sient.
- 87. Low Pass Filter by Euler’s Explicit Method s τ 1 + − y u • TMS320F24X code: (All variables in Q15) (Executed every ∆T s) lacc y,16 neg ;acch=-y add u,16 ;acch=u-y sach tmp ;temp. storage lt tmp ;T=u-y mpy k ;P=k*(u-y) pac ;acch=k*(u-y) add y,16 ;acch=y+k*(u-y) sach y ;store y y(n + 1) = y(n) + ∆T τ {u(n) − y(n)} y(n + 1) = 1 − ∆T τ y(n) + ∆T τ u(n) • Unstable for ∆T 2τ. 0 0.1 0.2 0.3 0.4 0.5 0 0.5 1 1.5 u y ∆T = 20µs, τ = 0.016666s. 0 0.1 0.2 0.3 0.4 0.5 −1 0 1 2 3 u y ∆T = 0.033333s, τ = 0.016666s.
- 88. Euler’s Implicit Method • For the system of N first order ODEs: ẏi = fi(t, y1, . . . , yN ), i = 1 . . . N evaluate the derivatives at the new location yi(n + 1) instead of at yi(n). • Also known as the Backward Euler method. • Better suited for stiff systems than the Explicit (or Forward) Euler method. • Stable even for large time steps. • Solving the implicit equations to calculate the derivatives can be difficult. Example: ẏ1 = f1(y1, y2) ; ẏ2 = f2(y1, y2) y1(n + 1) = y1(n) + ∆T × f1(y1(n + 1), y2(n + 1)) y2(n + 1) = y2(n) + ∆T × f2(y1(n + 1), y2(n + 1)) • If the system of ODEs is nonlinear, then it needs to be linearised at every time point.
- 89. Low Pass Filter by Euler’s Implicit Method s τ 1 + − y u y(n + 1) = y(n) + ∆T τ {u(n) − y(n + 1)} y(n + 1) = 1 1+cy(n) + c 1+cu(n) c = ∆T τ • Stable for any time step. • Easy to implement for a single ODE. • Difficult to implement on a DSP in real time for a system of ODEs, as it in- volves the simultaneous solution of a system of algebraic equations. 0 0.1 0.2 0.3 0.4 0.5 0 0.5 1 1.5 u y ∆T = 20µs, τ = 0.016666s. 0 0.1 0.2 0.3 0.4 0.5 0 0.5 1 1.5 y u ∆T = 0.033333s, τ = 0.016666s.
- 90. Heun’s Method • For the system of N first order ODEs: ẏi = fi(t, y1, . . . , yN ), i = 1 . . . N evaluate the values of yi(n + 1) in two steps. y0 i(n + 1) = yi(n) + ∆Tfi(t(n), y1(n), . . . , yN (n)) yi(n + 1) = yi(n) + ∆T 2 {fi(t(n), y1(n), . . . , yN (n)) + fi(t(n + 1), y0 1(n + 1), . . . , y0 N (n + 1))} • Also known as Modified Euler’s Method. • Has second order accuracy. The error is proportional to (∆T)2. • Computationally more intensive than Euler’s Explicit Method. • However, it permits the use of larger time steps than Euler’s Explicit Method.
- 91. Low Pass Filter by Heun’s Method s τ 1 + − y u y0 (n + 1) = y(n) + c{u(n) − y(n)} y(n + 1) = y(n) + c 2 [{u(n) − y(n)} +{u(n) − y0 (n + 1)}] c = ∆T τ y(n + 1) = (1 − c + c2 2 )y(n) + (c − c2 2 )u(n) • Unstable for ∆T 2τ • Better accuracy and stability than Eu- ler’s Explicit Method. • Computationally more intensive. 0 0.02 0.04 0.06 0.08 0.1 0 0.5 1 1.5 Euler explicit Heun Actual ∆T = 5ms, τ = 0.016666s
- 92. Harmonic Oscillator by Euler’s Explicit Method • Continuous time: ẋ = +ωy ẏ = −ωx • Discrete time: x(n + 1) y(n + 1) = 1 h −h 1 x(n) y(n) x(0) = 0 ; y(0) = 1 h = ω∆T • Eigenvalues: z = 1 ± jω∆T • System is unstable. 0 0.05 0.1 0.15 0.2 −2 −1 0 1 2
- 93. Harmonic Oscillator by Euler’s Implicit Method • Solve these simultaneous equa- tions: x(n + 1) = x(n) + hy(n + 1) y(n + 1) = y(n) − hx(n + 1) • Conditions: x(0) = 0 ; y(0) = 1 h = ω∆T x(n + 1) y(n + 1) = 1/(1 + h2) h/(1 + h2) −h/(1 + h2) 1/(1 + h2) x(n) y(n) • Eigenvalues: z = (1 ± jh)/(1 + h2) • System is stable. 0 0.05 0.1 0.15 0.2 −2 −1 0 1 2
- 94. Harmonic Oscillator: Practical Implementation Discrete system: x(n + 1) = x(n) + hy(n) y(n + 1) = y(n) − hx(n + 1) x(0) = 0; y(0) = 1 h = ω∆T x(n + 1) y(n + 1) = 1 h −h 1 − h2 x(n) y(n) Eigenvalues: z = 1 − h2 2 ± jh q 1 − h2 4 0 0.05 0.1 0.15 0.2 −2 −1 0 1 2 TMS320F24X code: lt sin mpy wdt pac add cos,16 sach cos lt cos mpy wdt pac neg add sin,16 sach sin System is critically stable.
- 95. Trapezoidal Rule • For the system of N first order ODEs: ẏi = fi(t, y1, . . . , yN ), i = 1 . . . N take the average of the derivatives at n and n + 1. • One of the Newton-Cotes Formulas. • Stable even for large time steps. • Solving the implicit equations to calculate the derivatives can be difficult. Example: ẏ1 = f1(y1, y2) ; ẏ2 = f2(y1, y2) y1(n + 1) = y1(n) + ∆T 2 × [f1(y1(n), y2(n)) + f1(y1(n + 1), y2(n + 1))] y2(n + 1) = y1(n) + ∆T 2 × [f2(y1(n), y2(n)) + f2(y1(n + 1), y2(n + 1))] • If the system of ODEs is nonlinear, then it needs to be linearised at every time point. • Roger Cotes (1682 – 1756): English mathematician, close collaborator of Isaac Newton. Proofread Newton’s Principia Mathematica.
- 96. M.C. Chandorkar Associate Professor Electrical Engineering Department Indian Institute of Technology - Bombay Mumbai 400076 mukul@ee.iitb.ac.in