Pipelining & All Hazards Solution
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The document discusses pipeline hazards including structural, data, and control hazards. It provides details on how each hazard can occur in a 5-stage pipeline and techniques to resolve them, including forwarding, stalling, and compiler scheduling. Data hazards are classified as RAW, WAW, and WAR. Control hazards from branches are reduced by computing the branch target and outcome earlier in the ID phase to minimize stalls.
![Control Hazards
Reducing the stall from branch hazards by moving the zero test and branch calculation into ID
phase of pipeline. It uses a separate adder to compute the branch target address during ID.
Because the branch target addition happens during ID, it will happen for all instructions. The
branch condition (Regs[IF/ID.IR6…10] op 0) will also be done for all instructions. The selection
of the sequential PC or the branch target PC will still occur during IF, but now it uses values
from ID phase, rather than from EX/MEM register. In this case, the branch instruction is done by
the end of ID phase, so EX, MEM and WB stages are not used for branch instructions anymore.](https://image.slidesharecdn.com/cmpar-181217064457/85/Pipelining-All-Hazards-Solution-29-320.jpg)
Pipelining & All Hazards Solution
- 3. Presentation Presentation Topic: Pipelining & All Hazards Solution
- 4. Content Introduction to pipeline hazard Structural Hazard Data Hazard Control Hazard
- 5. Pipelining What is Pipelining? It is an implementation technique where multiple tasks are performed in overlapped manner. When Pipelining Can be Implemented? It can be implemented when a task Is divided into two or subtasks, which can be performed independently. Classic 5-stage pipeline: 1) Instruction Fetch (Ifetch), 2) Register Read (Reg), 3) Execute (ALU), 4) Data Memory Access (Dmem), 5) Register Write (Reg)
- 7. Pipeline Hazards • Hazard: Condition or suitaution which does not allow the pipeline to operate normally. • Hazards reduce the performance from the ideal speedup gained by pipelining • Hazards in pipeline can make the pipeline to stall • Eliminating a hazard often requires that some instructions in the pipeline to be allowed to proceed while others are delayed – When an instruction is stalled, instructions issued latter than the stalled instruction are stopped, while the ones issued earlier must continue
- 8. Pipeline Hazards • No new instructions are fetched during the stall • Three types of hazards – Structural hazards – Data hazards – Control hazards
- 9. Structural Hazards A structural hazard occurs when a part of the processor's hardware is needed by two or more instructions at the same time. HW cannot support the combination of instructions Structural hazards can be avoided by stalling, duplicating the resource, or pipelining the resource.
- 10. Structural Hazards • Consider a Von Neumann architecture (same memory for instructions and data)
- 11. Structural Hazards • Stall cycle added (commonly called pipeline bubble)
- 14. Data Hazards • Data hazards occur when the pipeline changes the order of read/write accesses to operands so that the order differs from the order seen by sequentially executing instructions on an un-pipelined machine • Consider the execution of following instructions, on our pipelined example processor: – ADD R1, R2, R3 – SUB R4, R1, R5 – AND R6, R1, R7 – OR R8, R1, R9 – XOR R10, R1, R11
- 15. Data Hazards • The use of results from ADD instruction causes hazard since the register is not written until after those instructions read it.
- 16. Data Hazards • Eliminate the stalls for the hazard involving SUB and AND instructions using a technique called forwarding
- 17. Data Hazards • Store requires an operand during MEM and forwarding is shown here. – The result of the load is forwarded from the output in MEM/WB to the memory input to be stored – In addition the ALUOutput is forwarded to ALU input for address calculation for both Load and Store
- 18. Data Hazards Classification • Depending on the order of read and write access in the instructions, data hazards could be classified as three types. • Consider two instructions i and j, with i occurring before j. Possible data hazards: – RAW (Read After Write) • j tries to read a source before i writes to it , so j incorrectly gets the old value; • most common type of hazard, that is what we tried to explain so far. – WAW (Write After Write) • j tries to write an operand before is written by i. The write ends up being performed in wrong order, having i overwrite the operand written by j, the destination containing the operand written by i rather than the one written by j • Present in pipelines that write in more than one pipe stage – WAR (Write After Read) • j tries to write a destination before it is read by i, so the instruction i incorrectly gets the new value • This doesn’t happen in our example, since all reads are early and writes late
- 19. Data Hazards Requiring Stalls • Unfortunately not all data hazards can be handled by forwarding. Consider the following sequence: – LW R1, 0(R2) – SUB R4, R1, R5 – AND R6, R1, R7 – OR R8, R1, R9 • The problem with this sequence is that the Load operation will not have data until the end of MEM stage.
- 20. Data Hazards Requiring Stalls • The load instruction can forward the results to AND and OR instruction, but not to the SUB instruction since that would mean forwarding results in “negative” time
- 21. Data Hazards Requiring Stalls • The load interlock causes a stall to be inserted at clock cycle 4, delaying the SUB instruction and those that follow by one cycle. – This delay allows the value to be successfully forwarded onto the next clock cycle
- 22. Data Hazards Requiring Stalls • Before stall insertion LW R1, 0(R2) IF ID EX MEM WB SUB R4, R1, R5 IF ID EX MEM WB AND R6, R1, R7 IF ID EX MEM WB OR R8, R1, R9 IF ID EX MEM WB LW R1, 0(R2) IF ID EX MEM WB SUB R4, R1, R5 IF ID stall EX MEM WB AND R6, R1, R7 IF stall ID EX MEM WB OR R8, R1, R9 stall IF ID EX MEM WB • After stall insertion
- 23. Compiler Scheduling for Data Hazards • Consider a typical code, such as A = B+C LW R1, B IF ID EX MEM WB LW R2, C IF ID EX MEM WB ADD R3, R1, R2 IF ID stall EX MEM WB SW A, R3 IF stall ID EX MEM WB • The ADD instruction must be stalled to allow the load of C to complete • The SW needs not be delayed because the forwarding hardware passes the result from MEM/WB directly to the data memory input for storing
- 24. Compiler Scheduling for Data Hazards • Rather than just allow the pipeline to stall, the compiler could try to schedule the pipeline to avoid the stalls, by rearranging the code – The compiler could try to avoid the generating the code with a load followed by an immediate use of the load destination register – This technique is called pipeline scheduling or instruction scheduling and it is a very used technique in modern compilers
- 26. Control Hazards • Can cause a greater performance loss than the data hazards • When a branch is executed it may or it may not change the PC (to other value than its value + 4) – If a branch is changing the PC to its target address, than it is a taken branch – If a branch doesn’t change the PC to its target address, than it is a not taken branch • If instruction i is a taken branch, than the value of PC will not change until the end MEM stage of the instruction execution in the pipeline – A simple method to deal with branches is to stall the pipe as soon as we detect a branch until we know the result of the branch
- 27. Control Hazards • A branch causes three cycle stall in our example processor pipeline – One cycle is a repeated IF – necessary if the branch would be taken. If the branch is not taken, this IF is redundant – Two idle cycles Branch Instruction IF ID EX MEM WB Branch Successor IF stall stall IF ID EX MEM WB Branch Successor +1 IF ID EX MEM WB Branch Successor +2 IF ID EX MEM
- 28. Control Hazards • The three clock cycles lost for every branch is a significant loss – With a 30% branch frequency, the machine with branch stalls achieves only about half of the speedup from pipelining – Reducing the branch penalty becomes critical • The number of clock cycles in a branch stall can be reduced by two steps: – Find out if the branch is taken or not in early stage in the pipeline – Compute the taken PC (address of the branch target) earlier
- 29. Control Hazards Reducing the stall from branch hazards by moving the zero test and branch calculation into ID phase of pipeline. It uses a separate adder to compute the branch target address during ID. Because the branch target addition happens during ID, it will happen for all instructions. The branch condition (Regs[IF/ID.IR6…10] op 0) will also be done for all instructions. The selection of the sequential PC or the branch target PC will still occur during IF, but now it uses values from ID phase, rather than from EX/MEM register. In this case, the branch instruction is done by the end of ID phase, so EX, MEM and WB stages are not used for branch instructions anymore.
- 30. .. • END
Editor's Notes
- #8: pipeline stall is a delay in execution of an instruction in an instruction pipeline in order to resolve a hazard
- #9: pipeline stall is a delay in execution of an instruction in an instruction pipeline in order to resolve a hazard
- #11: As a result, when an instruction will perform a data reference, will conflict with an instruction fetch. In this example, the load instruction wants to access the memory to load data at the same time when instruction 3 wants to fetch an instruction from memory.
- #12: To solve the problem, a stall cycle is added. The effect of the pipeline bubble is actually to occupy the resources for that instruction slot as it travels through the pipeline. Performance wise, instruction 3 will not complete during clock cycle 8, but during clock cycle 9. We are going to resolve the structural hazard by using stall cyle. This ins 3 will wait until the hw unit memory becomes free then entering in the pipeline by entering first stage if we do that we see that one cycle is waisted due to the stall.
- #15: All the instructions after ADD use the result from ADD.
- #16: The ADD instruction writes the result in register R1 only at the WB stage, but SUB instruction reads the value during its ID stage. This is what is called a data hazard. Unless precautions are taken, the SUB instruction will read the wrong value and will use it… The AND instruction is also affected by this hazard. As we can see from the figure, the write of R1 doesn’t complete until the end of clock cycle 5. Thus, the AND instruction that reads the registers in clock cycle 4 will receive the wrong results. XOR instruction operates correctly, it reads its inputs (in clock cycle 6) after the ADD has written its result (in clock cycle 5). OR instruction can also be made to work without incurring an hazard, using a simple implementation technique. The technique is to perform the register file reads in the second half of the clock cycle and the writes in the first half.
- #17: The data hazard, in certain circumstances can be solved using an implementation technique called forwarding. The idea behind the forwarding is that the result produced by ADD is not really needed by the SUB instruction until it is actually produced. If the result can be moved from where the ADD instruction produces it , the EX/MEM register, to where the SUB needs it, the ALU input latches, then the need for a stall can be avoided. Forwarding works as follow: The ALU result from EX/MEM register is always fed back to the ALU input latches If the forwarding hardware detects that the previous ALU operation has written the register corresponding to a source for the current ALU operation, control logic selects the forwarded result as the ALU input, rather than the value read from the register file. We need to forward results not only from immediately previous instruction, but possible from instructions that started two or three cycles earlier.
- #29: To optimize the branch behavior, both of the steps should be taken.
- #30: It uses a separate adder to compute the branch target address during ID. Because the branch target addition happens during ID, it will happen for all instructions. The branch condition (Regs[IF/ID.IR6…10] op 0) will also be done for all instructions. The selection of the sequential PC or the branch target PC will still occur during IF, but now it uses values from ID phase, rather than from EX/MEM register. In this case, the branch instruction is done by the end of ID phase, so EX, MEM and WB stages are not used for branch instructions anymore.