Connecting electrical appliances to a Home Network using low-cost Power-Line Communication

Connecting electrical appliances to a Home Network
using low-cost Power-Line Communication
Andrea Ricci∗ , Valerio Aisa† , Valerio Cascio† , Guido Matrella∗ and Paolo Ciampolini∗
∗ Dipartimentodi Ingegneria dell’Informazione, Universit` degli Studi di Parma
a
Parma 43100, Italy. Email: andrea.ricci@nemo.unipr.it, {guido.matrella,paolo.ciampolini}@unipr.it
† Wrap s.p.a., Fabriano (AN), Italy. Email: Valerio.Aisa@merloni.com, valerio.cascio@wraphome.com

Abstract— This paper discusses a novel “proxy” approach, Home Communication Node Micro-
aimed at connecting digital appliances to a home network and Network (PLC, Wi-Fi, Zig-bee) controller
based on ultra low cost, narrow band power-line transmission Power
(ULP). Bidirectional point-to-point communication is carried out Micro- Meter
AFE ULP digital
on power-supply wire between the appliance itself and the outlet. controller Triac circuitry
Here a dedicated device embeds both network management
functions and ULP communication, acting as a proxy between
the appliance and the home network. Through this approach,
Ultra Low-cost Power-line Communication
white goods and any other electrical household appliance can be Smart
connected to the home network at extremely low communication Adapter Digital Appliance
cost and without issues related to standard protocol selection. In
this summary, after a brief introduction, the network structure
Fig. 1. Network structure
is presented. Next, physical layer of ULP protocol is discussed
and a prototypal HW implementation is presented. Finally,
experimental ULP performances are discussed and conclusions
are drawn. communication node (located, for instance, at the outlet).
Index Terms— power line, networks, home appliance, pro- By this approach, a number of definite advantages can be
grammable device.
attained: communication costs on the appliance side are kept
at a minimum; appliance hardware and software are virtually
I. I NTRODUCTION independent of the actual home networking protocol and
medium; general-purpose adapters can be designed, sharing
Nowadays, most of modern household appliances incor-
design and manufacturing costs on larger production volumes;
porate digital controllers: as electronics costs decrease and
moreover, the same communication node embedded in the
functionality increases, more and more sophisticated tasks can
adapter can actually serve multiple appliances, thus further
be accomplished by embedded digital circuitry: among most
lowering connection costs.
interesting perspectives, network connectivity is expected to
In the following, basic operating principles and a prototypal
become a standard feature in the next future. This will allow
implementation of the ULP technology are described.
for implementing remote control, for smart power management
and, mostly important, it will enable remote maintenance or
II. N ETWORK STRUCTURE
servicing from manufacturers or service-centers, preventive
maintenance, SW upgrades and early fault diagnostics. This, Figure 1 describes the network structure. Each appliance
in turn, will improve functionality, safety, reliability and is connected to his outlet. Bidirectional, point-to-point data
performance of appliances. In principle, a wide variety of transfer is carried out on the power cord: however, instead
network devices and protocols can be exploited to this purpose of using more conventional PLC communications, which
(e.g., LON [1], Konnex [2], Ethernet [3], etc.); however, would require relatively complicated (i.e., expensive) mod-
no agreement on a universally recognized home-networking ulation/demodulation circuitry, a much simpler solution is
“standard” has been reached yet. On the other hand, bandwith obtained by directly modulating the base-frequency power
requirements for the applications recalled above could be exchange between the outlet and the appliance.
significantly lower than those granted by full-featured home A small device, called “Smart Adapter”, connects the appli-
networks. This, associated to the extremely tight economic ance power-supply plug and the outlet, acting as a bridge
constraints typical of this market, prevents most solutions towards the home network. At one end, the smart adapter
from being effectively exploited for low-cost “white goods” manages “power modulation” communications with the ap-
networking. To overcome this problem, a solution has been pliance, while, at the opposite end, it embeds specific network
proposed in [4], based on a “proxy” approach: an ultra low cost controllers, interfacing to wired (e.g. broadband PLC, ethernet,
power-line narrow band technology (called ULP), is adopted, etc.) as well as wireless (e.g. Wi-Fi, ZigBee, etc.) networks.
enabling a bidirectional communication on power supply wire At the appliance front-end, simple digital signal processing
between the appliance itself and a stand-alone, general-purpose (either performed by the appliance controller itself or by

Smart Adapter IDA Digital Appliance
SWL an inexpensive resistive load (ZULP ). The appliance current,
exemplified in Fig. 3a, is therefore:
Power ZULP ULP
VS logic m (t) VS (t)
meter
TULP m(t)
circuitry
IDA = =
ZU LP
(a) VM 2π
= sin t dk pT (t − kT ) , (4)
ZU LP T
k
zc1
m ZULP Z1 At the Smart Adapter, data coming from the electrical
Z2 zc2
appliance are decoded by measuring the mean power absorbed
by the appliance during each k-th cycle of the supply voltage.
(b) If N samples of the instantaneous power P (t) are acquired
Lj Lj+1 k
per cycle, the mean power PT reads:
Fig. 2. ULP Transmission: (a) Digital Appliance to Smart Adapter, (b) Smart
Adapter to Digital Appliance (k+1)T
N −1
1 1 T T
k
PT = P dt ∼
= P kT + +i . (5)
T N i=0
2N N
additional logic circuitry) can be used to analyze the input kT

power-supply waveform; just a few discrete components (in The resulting scheme is very robust and reliable and can be
the following referred to as the Analog Front-End, AFE) are implemented at practically no additional costs.
needed to couple the digital domain and the power analog Smart Adapter sends data to the digital appliance by gener-
section. Actual voltage, phase and frequency can be extracted,
suitable, for instance, for early detection of power fails or VS (a)
misfunctioning. In the approach discussed here, slight, inten-
tional perturbations of the power supply waveform are also m(t)
1 0 0 1
used to carry additional information from the outside world to I DA
the appliance (“upstream” data flow): information can thus be Lj L j+1
decoded by exploiting already available resources. Similarly, VS
m
(b)
“downstream” communication (from the appliance to the smart
adapter) comes almost for free: information is encoded by ZC 1

modulating the instantaneous power consumption; to this ZC 2
purpose, the digital unit may simply control the switching of a
small additional load. As shown in Fig. 1, the Smart Adapter Fig. 3. ULP transmission signals: (a) Downstream communication, (b)
includes a microcontroller used as system supervisor and to Upstream communication
implements ULP logic functions. A power meter (receiver) and
a triac (transmitter) interface the controller to the powerline. ating short and precise interruptions of the appliance power
supply. In this case, the j th packet of M bit
III. ULP COMMUNICATION : PHYSICAL LAYER
Downstream communication is based on the modulation Dj = {dM j , dM j+1 , ..., dM j+M −1 } , (6)
of instantaneous power consumption: to this purpose, let’s is transmitted at a time. Data are encoded by modulating the
assume a set of binary data dk is to be transmitted, and interruption duration Lj as follows:
2π g (Dj )
VS (t) = VM sin t , (1) Lj = L0 + LV j = L0 + LV max , (7)
T 2M
is the supply voltage (T being the AC period). If a single where g is the Gray encoding function, L0 is an offset, constant
bit per period is transmitted (i.e., a throughput of 50/60 bit/s, lenght and LV max is the maximum allowed length of inter-
depending on the powerline frequency), a mask function can ruption variable term. Interruptions are controlled by a triac
be straightforwardly introduced: driven by the smart adapter logic, and synchronized with zero-
crossing of supply voltage, as shown in Fig. 3b. Experiments
m (t) = dk pT (t − kT ) , (2)
demonstrate the possibility to send at least one nibble (M = 4)
k
at a time, without affecting the proper functionality of the
where the port function pT (t) is defined as appliance. In this case, for instance, parameters can be set as
follows: L0 = 4 ms, LV max = 2 ms, with the AC supply
1 0<t<T
pT (t) = u (t) − u (t − T ) = (3) voltage period T set at 20 ms. Again, the main concern here
0 otherwise
is to keep the digital control at the appliance side as simple
Data can be easily encoded in the supply current by letting as possible: the AFE just includes two Schmitt triggers having
m(t) activate a small triac (TULP ) which, in turn, drives different thresholds (0 and 90 V), and provides ULP logic with

a couple of square waves, zc1 and zc2 . Extracting the rising- initial “calibrating” phase, and the actual operational mode.
edge delay between zc1 and zc2 is almost trivial: if such an Calibration is necessary to deal with tolerance of the low-
interval is larger than L0 , a message coming from the Smart cost AFE components: to this purpose, the receiver is first
Adapter message is recognized and decoded by measuring Lj , trained by means a fixed sequence of known data, from which
which just requires elementary binary counters. ¯
the actual mean value of the offset L0 is extracted. In the
operational phase, interruptions lenght are measured through
IV. FPGA IMPLEMENTATION OF ULP PHYSICAL LAYER binary counters; data are decoded according to (7), accounting
¯
for the calibrated value L0 . Decoded nibbles are used by the
As already stressed above, transceiver tasks at the appliance
side are kept as simple as possible, in order to lower the RRC (Receiver Register Control) block to build data bytes, to
overhead induced by communication. Software implementa- be stored into data register. Contemporarily, receiver state flags
tion of these tasks on the appliance native microcontroller are set in the status register. The receiver block also detects
is therefore relatively inexpensive; nevertheless, it would be power supply failures, by testing if voltage interruptions length
largely preferrable to delegate them to a hardware, peripheral, exceedes the AC period value. If this occurs, a proper interrupt
so that interference with appliance software applications and flag is raised.
resources could be almost zeroed. Increase of the hardware The transmitter section generates the mask signal m(t) (which
cost would be negligible as well, if such a peripheral could controls power modulation triac TULP ), by means of a shift
be integrated into the microcontroller device itself: to explore register, triggered by the zero-crossing signal zc1 and loaded,
the practicality of such an approach, we have developed a eight bit at a time, from data register.
prototypal implementation of a “power modulation” macrocell, The last block monitors the power supply. It computes ampli-
by means of a low-cost FPGA device. tude and frequency of supply voltage (i.e.: 50 or 60 Hz), by
As shown in Fig. 4, the ULP interface can be divided into using the same time interval estimation techniques exploited
five functional blocks: a register interface, a module for signal by the receiver section. The hardware design of ULP physical
conditioning, transmitter, receiver and line info block. FPGA layer has been tested using an evaluation board (Digilab
operations are performed using 1 MHz system clock, provided 2SB) based on a Xilinx Spartan-II 200E chip [5]; a portable
by the appliance microcontroller. VHDL code has been developed, the implementation of which
Communication between FPGA logic and microcontroller is requires about 1.500 equivalent logic gates. Functionality of
performed using a register interface. The register set in- the circuit has been fully validated, and experimental estimate
cludes five 8-bit registers (control register PMCR, status of the Bit Error Rate associated to the ULP protocol indicates
register PMSR, data register PMDR, voltage measure register a BER figure lower than 10−6 . More accurate assessment of
PMVMR and clock generation register PMCGR), all sharing the BER inferior limit is currently under way.
the same interface with microcontroller, based on address and V. C ONCLUSIONS
data buses, read/write signals and a set of five interrupt flags.
In this paper a low bit-rate, ultra low-cost powerline com-
The macrocell takes care of signal conditioning: square waves
munication (ULP) protocol is discussed. Its main goal is
zc1 and zc2 are routed through noise suppressors before being
that of allowing for networking digital household appliances,
latched internally. Their edges are used to generate trigger
without adding significant costs and staying independent of the
signals for subsequent processing blocks.
actual home-networking protocol by tranferring higher-level
The receiver module operates in two distinct modes: an
communication tasks to an external “Smart Adapter” device.
Formal basics of the “power modulation” approach, un-
derlaid by the ULP protocol, have been illustrated, and a
prototypal hardware implementation of a ULP controller has
been discussed. Experimental validation has been carried
out, obtaining fully satisfactory results, both in terms of
performance and chip-area requirements. This suggest that
incorporating an inexpensive ULP peripheral into a standard
microcontroller would effectively allow for narrow-band, low-
cost networking of digital appliances.
R EFERENCES
[1] Echelon Corporation, LonTalk Protocol Specification, version 3.0. 1994.
[2] Konnex Association, KNX Standard. 2001.
[3] Institute of Electrical and Electronics Engineers, Inc., IEEE Std 802.3.
IEEE Computer Society, 2002.
[4] V. Aisa, P. Falcioni and P. Pracchi, Connecting white goods to a home
network at a very low cost. International Appliance Manufacturing,
2004.
Fig. 4. Architecture of ULP physical interface implemented with pro- [5] Xilinx, Spartan-IIE 1.8V FPGA Family: Complete Datasheet. 2004.
grammable logice device

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