Practical difficulties and how to avoid emc hazards in instrumentation

Practical Difficulties &
How to avoid EMC
Hazards in
Instrumentation Design

EMC Hazards
EMC Hazards are classified in to two classes
EMI Hazards –
Conducted Emission Hazards
Radiated Emission Hazards
Voltage Dips & Interruption
Voltage Flicker & Fluctuations

EMC Hazards
EMS Hazards
Conducted Susceptibility Hazards
Radiated Susceptibility Hazards
Immunity Hazards
ESD Hazards
EFT Hazards
Surge Hazards
PFMF Hazards
Voltage Dips & Interruption Hazards

EMI Hazards
Conducted Emission Hazards
Due to Cables
Due to Ferrite
Due to improper Capacitor, Inductor & Diode

EMI Hazards
Radiated Emission
Due to Ferrite
Due to Enclosure and Air gaps
Due to ventilation and ventilation fans
Due to Environment

EMC Hazard Design – Immunity
ESD – Electro Static Discharge
Due to Enclosure Martials & Environment Humidity
Surge Immunity
Due to Selection of MOV and place of Installation
PFMF –Power Frequency Magnetic Field
Due to Field of Installation & Environment of
Installation
Voltage Dips & Short Interruption
Due to Input supply to the “EUT”

EFT – Design Hazard
Embedded controllers are designed to generate and act on signals such as high-speed serial
communication clocks that have timing specifications comparable to that of transient-
induced noise. Therefore, transient-induced noise is likely to interfere with these signals. In
a broad classification, the following blocks, pins, and signals are most influenced by
transient-induced noise:
 Power and ground signals
 Reset circuits
 Clock/oscillator signals
 Edge-sensitive triggers
 High-frequency digital signals
 Analog signals
 Communication blocks such as I2C, SPI, UART
 CPU
 Flash/RAM
transient-induced noise affects one or more of these blocks, the following types of system
failures can occur:
 Reset
 Latch-Up

The Design Process
Concept the idea
Target specifications the details (include functional and regulatory
- EMC)
System architecture the structure and details - EMC
Design rules the circuit and layout constraints- EMC
Initial design build it
Functional evaluation does it work? If not, modify.
Regulatory evaluation is it legal? If not modify - EMC
Release it meets the (modified) specs.

The Design Process
Target specifications the details (include
functional and regulatory - EMC)
- Are all the jurisdictions
specified?
- Have the requirements
changed?
- Is the environment correct?

The Design Process
System architecture the structure and details – EMC
-How many layers in PCBs?
-Are reactive circuits located away from I/O ports?
-Are I/O ports isolated/shielded?
-Are IC families appropriate for speeds needed?
-Will housing provide shielding?

Design for compliance
Initial Design must consider the following:
design goals
Components
PCB architecture
PCB layout and I/O
Cables
enclosures and shielding
software/firmware

Design rules the circuit and layout constraints –EMC
- Are RF signal traces short and/ or embedded?
- Are bypass caps located and sized optimally?
- Are ground planes low-Z, and earth bypass provided?
- Have sensitive designs been modeled?
-Consider use of Signal Integrity and Quiet expert, EMC
Flo simulation tools

Design for robustness:
- checkpoint routines and watchdog timers.
- checksums, error detection/correction codes.
- “sanity checks” of measured values.
- poll status of ports, sensors, actuators.
- read/write to digital ports to validate.

To increase the EMC success rate, the design process must have following
checks:
- Be sure the regulatory specifications are correct and current.
- Take into account the impact of equipment architecture
on EMC. Assure that purchased modules also comply.
- Consider EMC design rules, manual and/or automatic.
- Include places for EMC compliance modifications.
- Perform pre-compliance testing where possible.

Regulatory evaluation is it legal? If not modify – EMC
- Were places provided for optional
filtering/bypassing?
- Are ferrites cost-effective?
- Can spring fingers be added to the enclosure?
- Will a shielded cable help?
- Board re-spin?

EMI increases with power consumption
EMI increases with slew rate/clock
speed
EMI increases with ground bounce
EMI increases with output loading
Differential drive can reduce EMI
(LVDS)

Design for compliance: PCB architecture
Adjacent ground and power planes act as very
good decoupling capacitors.
ground and power planes can shield high-speed
or low-level signal traces between.
separate ground and chassis planes can reduce
noise.
16-planes (layers) design is common for back
planes

Pre-compliance tools
To pre-test for RF immunity:
use licensed transmitters for radiated fields.
use coupling networks and transformers for
conducted disturbances.
To mitigate RF immunity problems:
try ferrites and spring fingers above 50 MHz
try filters below 50 MHz, bypassing anywhere.

Pre-compliance EMI sites
1 m site
minimizes factory ambient.
good for small EUT, frequencies > 100 MHz.
Screened room
inexpensive, OK for regulatory conducted emissions
and conducted immunity tests.
Can be used for radiated emissions, with precautions.

My Profile
• Dr.R .Lenin Raja M.E., Ph.D (RF & Antenna)
• Director- Technical – ISRL
• Editor -Member:
• Carthage Science Publishing – RF & Microwave Engineering (The
Netherlands)
• Electronics & Antenna Engineering – World Academy of Science &
Technology –USA
• Contact : +91-8870082081
• leninaucbe@gmail.com; lenin.research@gmail.com

Practical difficulties and how to avoid emc hazards in instrumentation

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