![Different CPU architectures specify different instructions
Two classes of ISAs
• Reduced Instruction Set Computers (RISC)
IBM Power PC, Sun Sparc, MIPS, Alpha
• Complex Instruction Set Computers (CISC)
Intel x86, PDP-11, VAX
Another ISA classification: Load/Store Architecture
• Data must be in registers to be operated on
For example: array[x] = array[y] + array[z]
1 add ? OR 2 loads, an add, and a store ?
• Keeps HW simple many RISC ISAs are load/store
Instruction Set Architecture (ISA)
3](https://image.slidesharecdn.com/riscv-241017041949-96b3b22e/85/RISCV_processor_design_embedded_systems-pptx-3-320.jpg)
RISCV_processor_design_embedded_systems.pptx
- 1. RISC V Processor Design •Nithin Kumar N.R • Assistant Professor • Department of ECE • New Horizon College of Engineering
- 2. High Level Language • C, Java, Python, ADA, … • Loops, control flow, variables Levels of Interpretation: Instructions 2 for (i = 0; i < 10; i++) printf(“go cucs”); main: addi x2, x0, 10 addi x1, x0, 0 loop: slt x3, x1, x2 ... Assembly Language • No symbols (except labels) • One operation per statement • “human readable machine language” Machine Language • Binary-encoded assembly • Labels become addresses • The language of the CPU ALU, Control, Register File, … Machine Implementation (Microarchitecture) Instruction Set Architecture 00000000101000010000000000010011 00100000000000010000000000010000 00000000001000100001100000101010 10 x2 x0 op=addi
- 3. Different CPU architectures specify different instructions Two classes of ISAs • Reduced Instruction Set Computers (RISC) IBM Power PC, Sun Sparc, MIPS, Alpha • Complex Instruction Set Computers (CISC) Intel x86, PDP-11, VAX Another ISA classification: Load/Store Architecture • Data must be in registers to be operated on For example: array[x] = array[y] + array[z] 1 add ? OR 2 loads, an add, and a store ? • Keeps HW simple many RISC ISAs are load/store Instruction Set Architecture (ISA) 3
- 4. A RISC-V CPU with a (modified) Harvard architecture • Modified: instructions & data in common address space, separate instr/data caches can be accessed in parallel Putting it all together: Basic Processor 4 Registers data, address, control ALU Control 0010000000 1 0010000001 0 0001000010 0 ... 1010001000 0 1011000001 1 0010001010 1 ...
- 5. Low Power/High performance approaches
- 6. ARM v4 • The ARM is a 32-bit architecture. • When used in relation to the ARM: • Byte means 8 bits • Halfword means 16 bits (two bytes) • Word means 32 bits (four bytes) • Most ARM’s implement two instruction sets • 32-bit ARM Instruction Set • 16-bit Thumb Instruction Set
- 7. Operating Modes • The ARM has seven basic operating modes: • User : unprivileged mode under which most tasks run • FIQ : entered when a high priority (fast) interrupt is raised • IRQ : entered when a low priority (normal) interrupt is raised • Supervisor : entered on reset and when a Software Interrupt instruction is executed • Abort : used to handle memory access violations • Undef : used to handle undefined instructions • System : privileged mode using the same registers as user mode
- 8. The ARM Register Set SVC Mode r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r15 (pc) cpsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r8 r9 r10 r11 r12 r13 (sp) r14 (lr) spsr Current Visible Registers Banked out Registers User FIQ IRQ Undef Abort r13 (sp) r14 (lr)
- 9. ARM Instruction Set • Consist of : • Arithmetic: ADD ADC SUB SBC RSB RSC • Logical:AND ORR EOR BIC • Comparisons: CMP CMN TST TEQ • Data movement: MOV MVN • These instructions only work on registers, NOT memory. • Syntax: <Operation>{<cond>}{S} Rd, Rn, Operand2 • Comparisons set flags only- they do not specify Rd • Data movement does not specify Rn • Second operand is sent to the ALU via barrel shifter. Not equal Unsigned higher or same Unsigned lower Minus Equal Overflow No overflow Unsigned higher Unsigned lower or same Positive or Zero Less than Greater than Less than or equal Always Greater or equal EQ NE CS/HS CC/LO PL VS HI LS GE LT GT LE AL MI VC Suffix Description Z=0 C=1 C=0 Z=1 Flags tested N=1 N=0 V=1 V=0 C=1 & Z=0 C=0 or Z=1 N=V N!=V Z=0 & N=V Z=1 or N=!V Conditional Execution
- 10. Pipeline changes for ARM TDMI Instruction Fetch Shift + ALU Memory Access Reg Write Reg Read Reg Decode FETCH DECODE EXECUTE MEMORY WRITE ARM9TDMI ARM or Thumb Inst Decode Reg Select Reg Read Shift ALU Reg Write Thumb®ARM decompress ARM decode Instruction Fetch FETCH DECODE EXECUTE ARM7TDMI Shift + ALU Memory Access Reg Write FETCH DECODE EXECUTE MEMORY WRITE Reg Read Multiply Branch Prediction Instruction Fetch ISSUE ARM or Thumb Instruction Decode Multiply Add ARM10
- 11. Five Stages of RISC-V Datapath 11 5 ALU 5 5 control Reg. File PC Prog. Mem inst +4 Data Mem Fetch Decode Execute Memory WB A single cycle processor – this diagram is not 100% spatial
- 12. RISC-V MIPS Microprocessor Datapath 12
- 13. Five Stages of RISC-V Datapath 13
- 14. Five Stages of RISC-V Datapath 14
- 15. Five Stages of RISC-V Datapath 15
- 16. • The β is a general-purpose 32-bit architecture • All integer manipulation is between registers, with up to two source operands (one may be a sign-extended 16-bit literal), and one destination register. • Memory is referenced through load and store instructions that perform no other computation. • Conditional branch instructions are separated from comparison instructions: branch instructions test the value of a register that can be the result of a previous compare instruction. 6.004 Computation Structures
- 17. 6.004 Computation Structures - Instructions
- 18. • Traps • Faults • Interrupts • Register -27 is dedicated as Base of frame Pointer (BP) • Register -28 is dedicated as Link Pointer Pointer (LP) • Register -29 is dedicated as Stack Pointer (SP) • Register -30 is dedicated as Exception Pointer (XP) • Register -31 will be zero always, is dedicated as Supervisor Mode. 6.004 Computation Structures- Exceptions
- 19. Programming Model RISC V
- 20. Programming Model RISC V 32I
- 21. • https://github.com/ash-olakangal/RISC-V-Processor/tree/main • Low Power Design Methodologies by Jan M. Rabaey • Advanced Computer Architecture, NPTEL, IIT Guwahati • https://developer.arm.com/documentation • THE DEFINITIVE GUIDE TO ARM CORTEX-M3 AND CORTEX-M4 PROCESSORS BY YIU, JOSEPH • HTTPS://GITHUB.COM/ULTRAEMBEDDED/RISCV • 6.004 Computation Structures ,β Documentation, DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE, M A S S A C H U S ETTS I N S TI TU TE O F TEC H N O LO G Y • HTTPS://RISCV.ORG References
- 22. 32 bit RISC architecture 45 nm technology Number of cores -1 In order - 5 stage of pipelining With Superscalar unit Processor modes – machine, SVC, user, FIQ MMU – low power banked memory L1 I cache and L1D cache Single precision FPU Bus interface AHB/AXI4 Specifications
- 23. • https://shakti.org.in/processors.html • https://vegaprocessors.in/ • https://bar.eecs.berkeley.edu/projects/riscv.html • PES Website -course curriculum • satyagupta09@gmail.com • chitrahariharan2009@gmail.com References
- 24. THANK YOU
Editor's Notes
- #4: The Harvard architecture is a computer architecture with physically separate storage and signal pathways for instructions and data. --- http://en.wikipedia.org/wiki/Harvard_architecture Under pure von Neumann architecture the CPU can be either reading an instruction or reading/writing data from/to the memory. Both cannot occur at the same time since the instructions and data use the same bus system. In a computer using the Harvard architecture, the CPU can both read an instruction and perform a data memory access at the same time, even without a cache. A Harvard architecture computer can thus be faster for a given circuit complexity because instruction fetches and data access do not contend for a single memory pathway . Also, a Harvard architecture machine has distinct code and data address spaces: instruction address zero is not the same as data address zero. Instruction address zero might identify a twenty-four bit value, while data address zero might indicate an eight bit byte that isn't part of that twenty-four bit value. A modified Harvard architecture machine is very much like a Harvard architecture machine, but it relaxes the strict separation between instruction and data while still letting the CPU concurrently access two (or more) memory buses. The most common modification includes separate instruction and data caches backed by a common address space. While the CPU executes from cache, it acts as a pure Harvard machine. When accessing backing memory, it acts like a von Neumann machine (where code can be moved around like data, a powerful technique). This modification is widespread in modern processors such as the ARM architecture and X86 processors. It is sometimes loosely called a Harvard architecture, overlooking the fact that it is actually "modified".
- #10: Pipeline Comparison The point of this foil is to show that with the ARM7TDMI a lot of work was carried out in the execute stage of the pipeline. Now with ARM9TDMI the execute stage has been split out into three stages to allow greater throughput. This then means the CPI is about 1.5 compared against 1.9 for ARM7TDMI, and the operating frequency is approximately double for ARM9TDMI over ARM7TDMI on the same fabrication process. Therefore, at least double the processing power is available. It is possible for the pipeline to interlock. Forwarding paths have been provided to minimise this as much as possible, but they can still occur. By using a bit of consideration when writing code they can almost be eliminated.