Sequential circuits in Digital Electronics

Created by,
Vinoth Loganathan
RTL Design Engineer

DIGITAL DESIGN
 Digital designing of circuits is done Using logic gates
 Types of Digital Design are
 Combinational Circuit design
 Does not require clock
 No memory element (no feedback)
 E.g.: Adders, Coders, Mux, Etc.
 Sequential Circuit design
 Requires clock (For state transition)
 Has memory element (feedback)
 E.g.: Flip Flops, Counters, Etc.
2Created by Vinoth Loganathan in interest of VLSI Guidance

LATCH
 A latch has a feedback path, so information can
be retained by the device.
 Latches is Level sensitive and it have a control
signal.
 It is a level triggered , it mean that the output of
present state and input of the next state depends
on the level that is binary input 1 or 0.
 Latch is a device which continuously checks all
its input and correspondingly changes its output,
independent of the time determined by clocking
signal.
 Types:
SR-Latch (Set-Reset Latch)
D-Latch(Delay Latch)
JK-Latch(Jack Kilby Latch)
T-Latch(Toggle Latch) 3Created by Vinoth Loganathan in interest of VLSI Guidance

• The elementary sequential logic circuit is known as Flip-Flop.
• Flip flops are edge triggered which makes it easy to carry out timing analysis.
• Flip-flop has two stable states of complementary output values (0 and 1).
• They can transfer data only at the single instant and data cannot be changed until next
signal change.
• A flip-flop continuously checks its inputs and correspondingly changes its output only at
times determined by clocking signal.
• Types:
 SR Flip Flop
 D Flip Flop
 JK Flip Flop
 T Flip Flop
 A flip-flop circuit can be constructed from NAND gates and/or NOR gates.
 Each flip-flop has two outputs, Q and Q', and two inputs, set and reset.

 This type of flip-flop is referred to as an SR
flip-flop. It has two useful states set and reset.
 When Q=1 and Q'=0, it is in the set state (or 1-
state). When Q=0 and Q'=1, it is in the clear
state (or 0-state). The outputs Q and Q' are
complements of each other and are referred
to as the normal and complement outputs,
respectively. The binary state of the flip-flop
is taken to be the value of the normal output.
 When a 1 is applied to both the set and reset
inputs of the flip-flop, both Q and Q' outputs
go to 0. This condition violates the fact that
both outputs are complements of each other.
In normal operation this condition must be
avoided by making sure that 1's are not
applied to both inputs simultaneously.
 S=1, R=1 is also called as the memory state.
5
State(NAND) S R Q’ Q Description
Set
1 0 0 1 Set Q » 1
1 1 0 1 no change
Reset
0 1 1 0 Reset Q » 0
1 1 1 0 no change
Invalid 0 0 1 1 Invalid Condition
Created by Vinoth Loganathan in interest of VLSI Guidance

6
Present state Next state 1
Q n Qn+1 S R
0 0 0 X
0 1 1 0
1 0 0 1
1 1 X 0
Characteristics Equation
Excitation Table

 As long as the clock input is low, changes at the
D input make no difference to the outputs. The
truth table shows this as a ‘don’t care’ state (X).
The basic D Type flip-flop is called a level
triggered D Type flip-flop because whether the
D input is active or not depends on the logic
level of the clock input.
 Provided that the CK input is high (at logic 1),
then whichever logic state is at D will appear at
output Q and (unlike the SR flip-
flops) Q’ is always the inverse of Q).
 In Figure, if D = 1, then S must be 1 and R must
be 0, therefore Q is SET to 1.
 A possible problem with the level triggered D
type flip-flop; if there are changes in the data
during period when the clock pulse is at its
high level, the logic state at Q changes in
sympathy with D, and only ‘remembers’ the last
input state that occurred during the clock pulse.
This effect is called ‘Ripple Through’, and
although this allows the level triggered D Type
flip-flop to be used as a data switch, only
allowing data through from D to Q as long as CK
is held at logic 1, this may not be a desirable
property in many types of circuit.
7
Clk D Q Q Description
↓ » 0 X Q Q
Memory
no change
↑ » 1 0 0 1 Reset Q » 0
↑ » 1 1 1 0 Set Q » 1

8
Present state
of Q o/p
Next state of
Q o/p
Dn Input
0 0 0
0 1 1
1 0 0
1 1 1
Excitation Table
Q=D

 A JK flip-flop is a refinement of the SR flip-flop in that the
indeterminate state of the SR type is defined in the JK
type. Inputs J and K behave like inputs S and R to set and
clear the flip-flop (note that in a JK flip-flop, the letter J is
for set and the letter K is for clear).
 When logic 1 inputs are applied to both J and K
simultaneously, the flip-flop switches to its complement
state, i.e.., if Q=1, it switches to Q=0 and vice versa.
 A clocked JK flip-flop is shown in the figure. Output Q is
ANDed with K and CP inputs so that the flip-flop is
cleared during a clock pulse only if Q was previously 1.
Similarly, output Q' is ANDed with J and CP inputs so that
the flip-flop is set with a clock pulse only if Q' was
previously 1.
 Note that because of the feedback connection in the JK
flip-flop, a CP signal which remains a 1 (while J=K=1)
after the outputs have been complemented once will
cause repeated and continuous transitions of the outputs.
To avoid this, the clock pulses must have a time duration
less than the propagation delay through the flip-flop.
 The restriction on the pulse width can be eliminated with
a master-slave or edge-triggered construction. The same
reasoning also applies to the T flip-flop presented next.
9
same as
for the
SR Flip
Flop
Input Output
Description
J K Q Q
0 0 0 0
Memory
no change
0 0 0 1
0 1 1 0
Reset Q » 0
0 1 0 1
1 0 0 1
Set Q » 1
1 0 1 0
toggle
action 1 1 0 1 Toggle

10
Characteristics Equation Excitation Table
Present state
of Q o/p
Next state of
Q o/p
Jn Input Kn input
0 0 0 ×
0 1 1 ×
1 0 × 1
1 1 × 0
Q= JQ’+K’Q

 The T flip-flop is a single input version
of the JK flip-flop. As shown in the
figure, the T flip-flop is obtained from
the JK type if both inputs are tied
together.
 The output of the T flip-flop "toggles"
with each clock pulse.
11
Present state
of Q o/p
Next state of
Q o/p
Tn Input
0 0 0
0 1 1
1 0 1
1 1 0
Excitation Table
Q=TQ’+T’Q

 The Master-Slave Flip-Flop is basically two
gated flip-flops connected together in a series
configuration with the slave having an inverted
clock pulse. The outputs from Q and Q from the
“Slave” flip-flop are fed back to the inputs of the
“Master” with the outputs of the “Master” flip
flop being connected to the two inputs of the
“Slave” flip flop. This feedback configuration
from the slave’s output to the master’s input gives
the characteristic toggle of the JK flip flop as
shown below. 12
Clk j k Qn Qn
0 0 No change
0 1 0 1
1 0 1 0
1 1 Qn Qn

13
Timing diagram for master-slave JK flip-flop

 Sequential circuits are dependant on clock pulses applies to their inputs.
 The result of flip-flop responding to a clock input is called clock pulse triggering, of which
there are four types. Each type responds to a clock pulse in one of four ways:
1. High level triggering
2. Low level triggering
3. Positive edge triggering
4. Negative edge triggering
14
A clock is a special device that whose output continuously alternates between 0 and 1.
The time it takes the clock to change from 1 to 0 and back to 1 is called the clock period, or
clock cycle time.
The clock frequency is the inverse of the clock period.The unit of measurement for frequency
is the hertz.
Clocks are often used to synchronize circuits.
clock period

 Parallel Data Storage.
 Shift registers
 Frequency division
 Counters

 Serial adder: bits are added a pair at a time
(in one clock cycle)
 A=an-1an-2…a0, B=bn-1bn-2…b0
 The state machine is described as,
 G: state that the carry-in is 0
 H: state that the carry-in is1
23
Equations
Y = ab + ay + by
s = a ⊕b ⊕c

 The serial binary subtracter operates the same as the serial binary adder, except
the subtracted number is converted to its two's complement before being added.
Alternatively, the number to be subtracted is converted to its ones' complement, by
inverting its bits, and the carry flip-flop is initialized to a 1 instead of to 0 as in
addition.The ones' complement plus the 1 is the two's complement.

 A counter is a device which stores (and sometimes displays) the number of times a
particular event or process has occurred, often in relationship to a clock signal.
Types of counters
Counters are classified according to the way they are clocked:
 Asynchronous Counter (Ripple Counter):
The first flip-flop is clocked by the external clock pulse and then each successive
flip-flop is clocked by the output of the preceding f/f.
 Synchronous Counter :
Common clock is connected to all of the f/f’s and thus they are clocked simultaneously.

 Asynchronous Counter : flip-flop doesn’t change condition simultaneously because
it doesn’t use single clock signal
 Each FF output drives the CLK input of the next FF.
 FFs do not change states in exact synchronism with the applied clock pulses.
 There is delay between the responses of successive FFS.
 It is also often referred to as a ripple counter due to the way the FFs respond one
after another in a kind of rippling effect.

Asynchronous Down Counter
 The previous example is up asynchronous counter
 Down asynchronous counter count from large to zero and repeat
 Example: 3-bit binary down counter

32
 Up-down Counter is a combination of up and down counter.
 It can count upwards as well as downwards.
 It is also called multimode counter.
 It uses logic gates to allow either the inverted or non-inverted output
of one flip-flop to the clock input of the next flip-flop, depending
upon the status of control inputs.
 If the control inputs are both 1 or 0, then the counter does not count
upwards or downwards, because the clock inputs of all the flip-flops
except, the LSB will be held constant at either 0 or 1.This condition is
avoided.

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 In ripple counter, the settling time becomes large due to presence of propagation
delay (tpd) of each flip-flop.
 The propagation delay of the first and second flip-flops is tpd and 2 tpd respectively.
 The maximum frequency used in asynchronous counter is 1/fmax ≥ n tpd
or fmax ≥ 1/n tpd.

 The following techniques use an n-bit binary counter with asynchronous or synchronous
clear and/or parallel load:
 Detect a terminal count of N in a Modulo-N count sequence to asynchronously Clear the count to 0 or
asynchronously Load in value 0 (These lead to counts which are present for only a very short time
and can fail to work for some timing conditions!)
 Detect a terminal count of N - 1 in a Modulo-N count sequence to Clear the count synchronously to 0
 Detect a terminal count of N - 1 in a Modulo-N count sequence to synchronously Load in value 0
 Detect a terminal count and use Load to preset a count of the terminal count value minus (N - 1)
 Alternatively, custom design a modulo N counter as done for BCD
MODULO N COUNTER

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 The counter in Figure has 16 distinct states, thus, it is a MOD-16 ripple counter.
 The MOD number can be increased simply by adding more FFs to the counter.That
is
 MOD number = 2N
 Example
 A counter is needed that will count the number of items passing on a conveyor belt. A
photocell and light source combination is used to generate a single pulse each time an
item crosses its path.The counter must be able to count as many as one thousand items.
How many FFs are required?

 A synchronous 4-bit binary counter with an
asynchronous Clear is used to make a Modulo
7 counter.
 Use the Clear feature to detect the count 7 and
clear the count to 0. This gives a count of 0, 1,
2, 3, 4, 5, 6, 7(short)0, 1, 2, 3, 4, 5, 6, 7(short)0,
etc.
 DON’T DO THIS! Referred to as a “suicide”
counter! (Count “7” is “killed,” but the
designer’s job may be dead as well!)
COUNTING MODULO 7: DETECT 7 AND ASYNCHRONOUSLY
CLEAR
Clock
0
D3 Q3
D2 Q2
D1 Q1
D0 Q0
CLEAR
CP
LOAD

 A synchronous 4-bit binary counter with a synchronous
load and an asynchronous clear is used to make a
Modulo 7 counter
 Use the Load feature to detect the count "6" and load in
"zero". This gives a count of 0, 1, 2, 3, 4, 5, 6,
0, 1, 2, 3, 4, 5, 6, 0, ...
 Using don’t cares for states above 0110, detection of 6
can be done with Load = Q4 Q2
COUNTING MODULO 7: SYNCHRONOUSLY LOAD ON
TERMINAL COUNT OF 6
D3 Q3
D2 Q2
D1 Q1
D0 Q0
CLEAR
CP
LOAD
Clock
0
0
0
0
Reset

 A synchronous, 4-bit binary counter
with a synchronous Load is to be
used to make a Modulo 6 counter.
 Use the Load feature to preset the
count to 9 on Reset and detection of
count 14.
 This gives a count of 9, 10, 11, 12, 13,
14, 9, 10, 11, 12, 13, 14, 9, …
 If the terminal count is 15 detection
is usually built in as Carry Out (CO)
Clock
D3 Q3
D2 Q2
D1 Q1
D0 Q0
CLEAR
CP
LOAD
0
0
1
1
COUNTING MODULO 6: SYNCHRONOUSLY PRESET 9 ON RESET AND LOAD 9 ON TERMINAL
COUNT 14
Reset
1

39
 Synchronous counter: flip-flop with the same synchronous clock signal
 We can build synchronous counter using process to design sequential
circuit
 Example: 2-bit synchronous binary counter (using T flip-flop or JK)

 Up/Down Synchronous Counter: two way counter which able to count up
or down
 Up/Down control input line which determine the counter
 Up/Down = 1 (count up)
 Up/Down = 0 (count down)

44
A synchronous count down binary counter goes through the binary states in the reverse order
from 1111 down to 0000 and back to 1111
The least significant bit is always complemented. Each bit is complemented if all the lower bits
are equal to 0
The two operations can be combined in one circuit to form a counter capable of counting either
up or down
When up and down inputs are 0, the circuit does not change state and when there are both 1, the
circuit counts up
When the up input control is 1, the circuit counts up,
since the T inputs are determined from the previous
values of the normal outputs in Q.
When the down input control is 1, the circuit counts
down, since the complement outputs Q’ determine
the states of the T inputs.
When both the up and down signal are 0’s, the
register does not change state but remains in the
same countCreated by Vinoth Loganathan in interest of VLSI Guidance

The modulus is the number of unique states through which the
counter will sequence. The maximum possible number of states of
a counter is 2n where n is the number of flip-flops.
Counters can be designed to have a number of states in their
sequence that is less than the maximum of 2n

 Digital Clock
 Frequency Counter

48
 The counter that starts counting from any state is called pre-settable counter.
 It accepts the starting state using the PRESET and CLEAR inputs.
 Example of pre-settable counter is MOD-8 ripple UP counter.

 In sequential circuit design, we turn some description into a working circuit
 We first make a state table or diagram to express the computation
 Then we can turn that table or diagram into a sequential circuit
Step 1:
Make a state table based on the problem statement. The table should show the present states, inputs,
next states and outputs. (It may be easier to find a state diagram first, and then convert that to a table)
Step 2:
Assign binary codes to the states in the state table, if you haven’t already. If you have n states, your
binary codes will have at least log2 n digits, and your circuit will have at least log2 n flip-flops
Step 3:
For each flip-flop and each row of your state table, find the flip-flop input values that are needed to
generate the next state from the present state.You can use flip-flop excitation tables here.
Step 4:
Find simplified equations for the flip-flop inputs and the outputs.
Step 5:
Build the circuit!

net-list
FSM (FINITE STATE MACHINE) OPTIMIZATION
State tables
State minimization
State assignment
Combinational logic optimization
identify and remove
equivalent states
assign unique binary
code to each state
use unassigned state-codes
as don’t care

51
Sequential circuit components:
•Flip-flop(s)
•Clock
•Logic gates
•Input
•Output
State diagram:
Circle => state
Arrow => transition input/output
State table:
Left column => current state
Top row => input combination
Table entry => next state, output

A xy 00 01 11 10
0 0 1 0 1
1 1 0 1 0
52
A(next) = A(xy)’+A’(x’y)+A(xy)+A’(xy’)
A B C

 A reduction in the number of states may
result in a reduction in the number of flip-
flops.
Equivalent states
 Two states are said to be equivalent
 For each member of the set of inputs, they
give exactly the same output and send the
circuit to the same state or to an equivalent
state. One of the state can be removed.
53
Reducing the state
table
● e = g (remove g);
● d = f (remove f);

 To minimize the cost of the combinational circuits.
 Three possible binary state assignments. (m states need n-bits, where 2n > m)

 Any binary number assignment is satisfactory as long as each state is
assigned a unique number.
 Use binary assignment 1.

 Sequential machines are typically classified as either a Mealy machine or a Moore
machine implementation.
 Moore machine: The outputs of the circuit depend only upon the current state of
the circuit.
 Mealy machine: The outputs of the circuit depend upon both the current state of
the circuit and the inputs.

 In Moore's circuit output depends on the
present state alone.
 Moore's output will be minimize glitches.
 Moore's output stable ‘1’ clock cycle.
 This is reliable circuit .
 It consume more Area.
 Application:Traffic light controller.
Moore Design Mealy Design
• In Mealy circuit output depends on the
present state and current input.
• Mealy output can possible to produce
glitches.
• Mealy output need not stable for ‘1’ clock
cycle.
• This is Controller circuit .
• It consume Low Area.
• Application: Chip design.

58
MOORE STATE DIAGRAM & TABLE
A/0 B/0 C/0 D/0
1 0 0
0
0
1
1
E/1
1
0
1
Present
State Input
Next
State Output
A 0 A 0
A 1 B 0
B 0 C 0
B 1 B 0
C 0 D 0
C 1 B 0
D 0 A 0
D 1 E 0
E 0 C 1
E 1 B 1
Z Q2 Q1
00 01 11 10
Q0
0
1 1
A: 000 D: 100
B: 001 E: 101
C: 010
Z= Q2 Q1’Q0Created by Vinoth Loganathan in interest of VLSI Guidance

MEALY STATE DIAGRAM & TABLE
59
A B C D
1/0 0/0 0/0
1/1
0/0
0/0
1/0
1/0
Present
State Input
Next
State Output
A 0 A 0
A 1 B 0
B 0 C 0
B 1 B 0
C 0 D 0
C 1 B 0
D 0 A 0
D 1 B 1

 Tabular representation of X and Qat the FFs and of Y as per FQ for the combination circuit at the
output stages.
 Gives present states and the inputs given at the memory section.
 Gives the memory-section outputs that follow the excitations
Excitation Table Rows
 Number of rows in each column equals 2 m where m is the number of flip-flops because each flip-
flop has one Q output and m flip-flops will have 2m different combinations of the states at the Qs.
 For example, if (Q1, Q2) are the Qs of two FFs, then (Q1, Q2) = (0, 0), (0, 1), (1, 0) and (1, 1) are the
four combinations possible for the four different states of the memory section present outputs
Excitation Table Columns
 First column—present state (Q1, Q2) in its each row
 The number of columns for the excitation inputs Q’ equals the number of possible combinations
of external inputs in the set X. It equals 2i if there are i distinct literal to represent the inputs when
there are i inputs X0, X1, … Xi–1. If i = 1, then columns 2 and 3 will be for X = 0 and X =1, as there are
two possible values of X.

SR flip-flop:-
Excitation table:-
Clk S R Qn Qn
0 0 No change
0 1 0 1
1 0 1 0
1 1 Race Race
Present state of Q
o/p
Next state of Q o/p Sn Input Rn input
0 0 0 ×
0 1 1 0
1 0 0 1
1 1 × 0

JK flip-flop:-
Excitation table:-
Present state of Q
o/p
Next state of Q o/p Jn Input Kn input
0 0 0 ×
0 1 1 ×
1 0 × 1
1 1 × 0
Clk J k Qn Qn
0 0 No change
0 1 0 1
1 0 1 0
1 1 Qn Qn

D flip-flop:-
Excitation table:-
Present state of Q
o/p
Next state of Q
o/p
Dn Input
0 0 0
0 1 1
1 0 0
1 1 1
Clk D Q
0 0
1 1

T flip-flop:-
Excitation table:-
Present state of Q
o/p
Next state of Q
o/p
Tn Input
0 0 0
0 1 1
1 0 1
1 1 0
Clk T Q
0 No change
1 toggle

 Shift registers are a type of sequential logic circuit, mainly for storage of digital data.
They are a group of flip-flops connected in a chain so that the output from one flip-flop
becomes the input of the next flip-flop.
 Most of the registers possess no characteristic internal sequence of states. All the flip-
flops are driven by a common clock, and all are set or reset simultaneously.
 The data in a shift register can be shifted in two possible ways: (a) serial shifting and (b)
parallel shifting.
 The serial shifting method shifts one bit at a time for each clock pulse in a serial manner,
beginning with either LSB or MSB.
 On the other hand, in parallel shifting operation, all the data (input or output) gets
shifted simultaneously during a single clock pulse.
 Hence, we may say that parallel shifting operation is much faster than serial shifting
operation.

 There are two ways to shift data into a register (serial or parallel) and similarly two ways
to shift the data out of the register.
 All of the four configurations are commercially available as TTL MSI/LSI circuits.They
are:
1. Serial in/Serial out (SISO) –74L91, 8 bits
2. Serial in/Parallel out (SIPO) – 74164, 8 bits
3. Parallel in/Serial out (PISO) – 74265, 8 bits
4. Parallel in/Parallel out (PIPO) – 74198, 8 bits.

 The input data is then applied sequentially to the D input of the first flip-flop on the left (FF0). During
each clock pulse, one bit is transmitted from left to right. Assume a data word to be 1001.The least
significant bit of the data has to be shifted through the register from FF0 to FF3.

 For this kind of register, data bits are entered serially in the same manner as discussed
in the SISO.
 Once the data are stored, each bit appears on its respective output line, and all bits are
available simultaneously

 The circuit uses D flip-flops and AND gates for entering data (i.e. writing)to the
register.

 For parallel in - parallel out shift registers, all data bits appear on the parallel
outputs immediately following the simultaneous entry of the data bits.

 Each right shift operation has the effect of successively dividing the binary number
by two. If the operation is reversed (left shift), this has the effect of multiplying the
number by two.
 With suitable gating arrangement a serial shift register can perform both
operations.

 Two of the most common types of shift register counters are introduced here:
 The Ring counter .
 The Johnson counter.
 They are basically shift registers with the serial outputs connected back to the
serial inputs in order to produce particular sequences.
 These registers are classified as counters because they exhibit a specified
sequence of states.

 A ring counter is basically a circulating shift register in which the output of the most
significant stage is fed back to the input of the least significant stage. If the CLEAR
signal is high, all the flip-flops except the first one FF0 are reset to 0. FF0 is preset to 1
instead.
74
Since the count sequence has 4 distinct states,
the counter can be considered as a mod-4
counter

 Johnson counters are a variation of standard ring counters, with the inverted output
of the last stage fed back to the input of the first stage.
 They are also known as twisted ring counters. An n-stage Johnson counter yields a
count sequence of length 2n, so it may be considered to be a mod-2n counter.The
circuit above shows a 4-bit Johnson counter.

 To Produce Time Delay
 To Simplify Combinational Logic
 To Convert Serial Data to Parallel Data
 To Convert Parallel Data to Serial Data
 A Shift Register Counter

77
It is an arrangement of several types of
counters where the output of last flip-
flop is fed as input to the first flip-flop.
On the basis of feedback, shift register
counters are of two types:
Ring counter: In this, only one flip-flop is
set at any particular time while others are
cleared. The information can shift from left
to right or right to left and back around.
Shift counter: It is a counter where an
inverted output of last flip-flop acts as an
input to the first flip-flop

78
 It generates the desired sequence of bits in synchronization with a clock.
 It is constructed using shift register and next state decoder where the output of next state decoder is connected
to serial input of shift register.
 It can be used as random bit generator, code generator and prescribed period generator.
 It is designed using two circuits:
 Multiplexer: Using this, an n-bit sequence can be generated with n-inputs and modulo-n counter.
 Counter: Using this, an N-bit sequence can be generated where the number of flip-flops (n) is given by N < = 2n - 1.

Created by Vinoth Loganathan in interest of VLSI Guidance 79

Sequential circuits in Digital Electronics

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