Session five

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Session 5

Prepared by
Alaa Salah Shehata
Mahmoud A. M. Abd El Latif
Mohamed Mohamed Tala’t
Mohamed Salah Mahmoud

Version 02 – October 2011
Copyright 2006 – Biz/ed


5
-Data Types

Contents -Scalar
-Composite
-User defined

-LABs
-Memory units

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Data Types

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Data Types
-Type declaration is made inside architecture declaration, entity declaration,
process declaration

-VHDL is a strongly typed language, meaning that data objects of different types
cannot be assigned to one another without the use of a type conversion function.

Data Types can be classified into:
1–Scalar types
Refers to all types whose objects have a single value at any time instant.

2–Composite types
Refers to types that have a regular structure consisting of elements of the same type
such as array or elements of different types such as record.

3–User defined types
Types that are defined by default and to be defined by the user before using.
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Data Types 1-Scalar Types
-Refers to all types whose objects have a single value at any time instant.

Scalar Types

1-Enumerated types
a–Bit
b–Boolean
c–Character
d-String
2–Integer
3–Floating Point
4–Physical types

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Data Types 1-1 Enumerated Types
-Specifies list of possible values

a-Bit
Type bit defines two standard logical values (‘0’ , ‘1’)
bit ( „0‟ , „1‟ ) ;

b-Boolean
Type Boolean is used in the conditional operations
boolean ( false , true ) ;

Logical functions such as equality (=) and comparison (<) functions
return a BOOLEAN value.
Example: Evaluate the following relational expression:
”1011” < ”110”. Comment!
The expression evaluates to true.

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Data Types 1-1 Enumerated Types

c-Character
covers all characters
character ( „@‟,‟#‟, …. „A‟ , „B‟, ...) ; The CHARACTER data
type enumerates the ASCII character set.

D- string
if we need to write string of characters we use this key word

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Enumerated Types

Example
22

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Example 1-1 Enumerated Types

entity ex_enum is
Port ( inp1 : in STD_LOGIC;
inp2 : in STD_LOGIC;
outp1 : out Boolean;
outp2 : out Character;
outp3 : out string(1 to 5)

);
end ex_enum;

architecture Behavioral of ex_enum is
begin
outp1 <= true when inp1 < inp2 else false ;
outp2 <= „t‟ when inp1 < inp2 else „f‟ ;
outp3 <= “equal” when inp1=inp2 else “notEQ”;
end Behavioral;

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Data Types 1-2 Integer Type

integer range -2147483648 to 2147483648 ;

Example
Signal counter : integer range 0 to 15 ;

Note

The implementation of the type integer in the synthesis and depends on the range
specified by the user.

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Integer Type

Example
23

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integer Types

PROCESS (X)
variable a: integer;
variable b: integer range 0 to 15;

type int is range -10 to 10;
variable d: int;

BEGIN
a := 1;
b := -1; d := -12;
a := 1.0;
a := -1; b := 10;
d := a;
END PROCESS;

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Data Types 1-3 Floating Point Type

It has no meaning in synthesis so it is only used for simulation.

Named as floating or real type -1.0E308 to 1.0E308

They must converted to bits at synthesize time.

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Floating Point Type

Example
24

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Floating Point Type

entity ex_enum is
Port ( inp1 : in STD_LOGIC;
inp2 : in STD_LOGIC;
outp : out real
);
end ex_enum;

architecture Behavioral of ex_enum is
begin
outp<= 1.5 when inp1 < inp2 else 2.5;
end Behavioral;

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Data Types 1-4 Physical Type

Physical types represent measurements of some quantity
Allows to define measurements of some physical quantities such as time, length,
resistance…

Syntax
type <type_name> is range <range>
units
<primary_unit>;
<secondary_unit> =
<integer> <primary_unit>;
…
end units;

<primary_unit> an identifier for the primary unit of measurement for that type
<secondary_unit> an integer multiple of the primary unit

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Data Types 1-4 Physical Types

Predefined physical types
time type
Time is the only predefined physical type

Example
type time is range -2147483647 to 2147483647
units
fs;
ps = 1000 fs;
ns = 1000 ps;
us = 1000 ns;
ms = 1000 us;
sec = 1000 ms;
min = 60 sec;
hr = 60 min;
end units;
Note
physical types are not synthesizable
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Data Types 2-Composite Types

Composite Types
1–Array
Multiple elements of the same type

2-Record

Multiple elements of different types

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Data Types 2-1 Array
•Group elements of the same type

Syntax
7 21 0
Type <type_name> is array <range> of <data_type>; 0
Example . 1
.
1D array .
type data is array (7 downto 0) of bit ;
signal D_bus : data ; 15
D_bus <= “10101010”

2 D array
type memory is array (0 to 15) of std_logic_vector(7 downto 0);
signal word : memory ;
word (5) <= “10010110” ;
word (15,4) <= „1‟ ;

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Data Types 2-1 Array

type word is array (0 to 31) of std_logic;
type byte is array (7 downto 0) of std_logic;
type memory is array (0 to 15) of std_logic_vector(7 downto 0);

signal D_bus : word;
signal mem1 : memory;
variable x : byte;
variable y : std_logic;

mem1 (5) <= "10010110" ;
mem1 (15,4) <= '1' ;
y := x(5);

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Data Types 2-2 Record
Group elements of possibly different types
Elements are indexed via field names

Syntax
type <type_name> is record
identifier: type;
identifier: type;
…
end record;

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Data Types 2-2 Record

Example Data Packet

type packet is record
ID : integer range 0 to 15 ;
C : std_logic ;
SOF : std_logic_vector(7 downto 0) ;
PAYLOAD : std_logic_vector( 127 downto 0) ;
CRC : std_logic_vector(3 downto 0) ;
EOF : std_logic_vector(7 downto 0);
end record ;

signal tx_packet : packet;
tx_packet.ID <= 3 ;
tx_packet.PAYLOAD <= “1000………………..10101”;

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Data Types 3-User Defined Types

Types that are defined by default and to be defined by
the user before using, such as encoding FSM next and
present states.
Syntax:
Type <type_name> is (value1, value2, …)

Most often used in the encoding of FSM states.
When encoding the states of the FSM of the control unit
in a microprocessor, one can define it as follows.

Type states is (reset, fetch, decode, excute, store)
Signal P_state : states;

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Data Types 3-User Defined Types

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Data Types -Data Conversion

VHDL is a strongly typed language, meaning that data objects of different types cannot be
assigned to one another without the use of a type conversion function.

If A and B are both integer variables, the assignment

a := b + ‘1’ ; is illegal because ‘1’ is of type bit.

For Example

SIGNAL a,b : IN integer;
SIGNAL y : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
...
y <= CONV_STD_LOGIC_VECTOR ((a+b), 8); to change from integer to std_logic

or a<=conv_integer(y); to change from std_logic to integer

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Memories

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Data Types -How to make RAM
first you have to think about entity (I/p &o/P)

1-clock for synchronization

2-write enable to control writing the data on memory , RAM<= data_in.

3-read enable to control read date from memory ,data_out <= Ram.

4 address to control which data you want to read or write .

5- input data and output data

the question is do we have to but reset as input ???

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• RAM

with separate read and write ports

lab
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• RAM

with internal address control

lab
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• ROM

Make Synchronous 16 X 8 ROM

lab
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Session 2


Mini Project-2

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Why Scrambler

1) One purpose of scrambling is to
reduce the length of strings of zeros or
ones in a transmitted signal, since a
long string of 0s or 1s may cause
transmission synchronization problems,
i.e. cause the clock regeneration at the
receiver more difficult.

2) Also for making the transmitted signal
more secured.

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Scrambler

A(i) Scrambler B(i)

B(i)=[A(i)+c(i)]mod2

A(i) is the input to the scrambler.
B(i) is the scrambled code word (the output of the scrambler)
c(i) is the output of the Pseudo-random sequence generation

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Scrambler

Pseudo-random sequence generation

As we said before, C(i) will be Xored with the input of the
scrambler b(i) generating the scrambled output B(i).
B(i)=[b(i)+c(i)]mod2
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Questions
Session-5

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Take Your Notes
Print the slides and take your notes here

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See You Next Session

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