Slide Development Of A Laser Driver Chip Test Set‑Up For Slhc Experiments
- 1. S. Meroli(a,b), A. Cazzorla(a,b), B. Checcucci(a), G. Mazza(c), A. Moschitta(a,b), L. Servoli(a) (a) Istituto Nazionale di Fisica Nucleare Sezione di Perugia – Italy (b) Università degli Studi di Perugia - Italy (c) Istituto Nazionale di Fisica Nucleare Sezione di Torino – Italy
- 2. OUTLINE • Optical Links for LHC Upgrade • Test Setup description • Test Results • Conclusions 2
- 3. Optical Link at LHC • Optical links heavily used in LHC experiments: – Minimize power dissipation and material budget – Allow high data-rates - Immune to electrical interference • example: CMS tracker readout: - used 50000 optical fibres - 40 MS/s transfer rate - total length of the link approximately 100m - bit error rates less than 10-12 3
- 4. Optical Link Upgrade for LHC • Future LHC upgrade: luminosity increased by an order of magnitude. Higher radiation doses. More data to be transmitted • Further requirements: low power dissipation, reduced mass. • Possible solution: increase the bandwidth of each individual link. - Run at multi‐Gbps speeds; - Have better radiation tolerance; - Operate at low temperatures (~ -10°) and in strong magnetic field (4T); - Be easy to install and operate. 4
- 5. GBT Project • The GBT project aims to design a fast and radiation tolerant optical transceiver for HEP experiments. • The GBT project is a collaboration between: Cern, CPPM Marseille, SMU Dallas and several INFN units (Perugia, Torino, Bologna, Bari). • The GBT will provide a bi-directional connection between the front-end electronics and the DAQ/TTC/SC systems: - working at 4.8 Gbit/s - radiation tolerant (total dose and SEU effects) Development of a full custom ASIC is needed (fabricated in a commercial CMOS 130 nm technology). 5
- 6. GBT Architecture The GBT includes: - GBTIA Transimpedance optical receiver - GBTx Data and Timing Transceiver - GBT-SCA Slow control ASIC • Possibility to drive both edge - GBLD Laser driver (DUT) emitting lasers and VCSELs • Differential and single ended driving • Independently programmable rising and falling edge pre/deemphasis • I2C digital control with SEU protection 6
- 7. GBLD Diagram Block • I2C Interface • Internal Registers • Input Stage • PreDriver • Output Stages 7
- 8. GBLD Specification Electrical Specification Proposal for 5 Gbps Operation # Specifications Min Max Unit Note 1 Rise Time 60 Ps 20%-80% 2 Fall Time 60 Ps 20%-80% 3 Total 50 Ps @BER= Jitter 1E-12 4 Deterministic 30 Ps Jitter 5 Modulation 2 24 mA current 6 Bias current 2 43 mA 7 Pre/De-emphasis 0 12 mA current 8 Power 460 mW consumption Eye Diagram: overlap of the waveform in a single UI. 8
- 9. GBLD Testboard • Critical for the Testboard is the design of: - Footprint: • transition between the chip pad and the PCB • insufficient thermal sink. • soldering problems due to high density package. - Separated Power Distribution System for critical areas - Bias network capable to work in a 4T magnetic environment Schematic Testboard Assembled Testboard 9
- 10. GBLD Testboard • To ensure signal integrity at 5 Gb/s, an accurate simulation work for the microstrip design has been carried out. Electric Field Tool to determine the size, the length Tool to study the electric field and the geometry of the microstrip line propagation and the coupling between the microstrip lines 10
- 11. GBLD Testboard • To ensure signal integrity at 5 Gb/s, an accurate simulation work, for the microstrip design, has been carried out. This analysis allowed us to reach the main goal: microstrip lines impedance closes to 50Ω (± 5%) avoiding mismatch and reflections (~51Ω) Microstrip impedance measurement, made out with a TDR module 11
- 12. Laser Driver Test Setup • PC to control in real-time: - GBLD setting (through I2C line) - Signal Data-Rate generated from PPG - Signal Measurements from SDA Scope 12
- 13. Test results: Eye Diagrams Eye Diagram@2.5 Gb/s Eye Diagram@5 Gb/s • @2.5 Gb/s: • @5 Gb/s: - eye open - rise/fall times not sufficiently fast - jitter quite low - significant jitter present 13
- 14. Test results: Rise Time Rise Time@2.5 Gb/s Rise Time@5 Gb/s • Rise time significantly higher than 120 ps • Rise time far from specification (60 ps) and critical for 5 Gb/s operation 14
- 15. Test results: Fall Time Fall Time@2.5 Gb/s Fall Time@5 Gb/s • Fall time significantly higher than 100 ps • Far from specification (60 ps) PreDriver fails to switch the current quickly (bandwidth limitation) Increasing the preDrvBias Current: GBLD performance improvement 15
- 16. Test results: Output Jitter Rj@5 Gb/s Dj@5 Gb/s 5 Gb/s jitter results very similar at 2.5 Gb/s jitter results • Rj remains into the specifications • Dj is the dominant part • The dominant Dj component is the Inter-Symbolic Interference (ISI) related to the bandwidth limitation. Tj@5 Gb/s 16
- 17. Test results: SNR SNR@2.5 Gb/s SNR@5 Gb/s • SNR@5 Gb/s worsens than SNR@2.5 Gb/s • SNR improves increasing the preDrvBias current High rise/fall time and Deterministic Jitter make impossible the operation @5Gb/s 17
- 18. Test results: Pre-Emphasis Current Pre-emphasis is an addictional current provided during the rise and fall time. Need to improve the rise and fall time. Waveform without pre-emphasis Waveform with max pre-emphasis @5 Gb/s @5 Gb/s Rise Fall Positive Negative Rise Fall Positive Negative Time Time overshoot overshoot Time Time overshoot overshoot 137.9 ps 135.6 ps 5.1 % 2% 82 ps 78.5 ps 20.9 % 23.3 % 18
- 19. Test results: Pre-Emphasis Current Pre Emphasis MAX Rise Time Pre Emphasis MIN With maximum pre-emphasis the rise/fall time decreases significantly (close to the proposal specifications). Eye Diagrams wider 19
- 20. Conclusion • A full automatic test setup has been realized • A 5 Gb/s laser driver in CMOS 0.13 μm technology has been designed and tested. • Prototype is functional but bandwidth is a bit below specs • Possible reasons: GBLD parasitic capacitance and layout symmetry need optimization. • A new version of GBLD chip and a new testboard have been realized (May 2010) and will be put under test soon. 20
- 21. Backup
- 22. GBLD Modulation Diagram Block 22
- 23. Input Range Output pk-pk Voltage vs Input Voltage 23
- 24. Test results: Eye Height Eye Height @2.5 Gb/s Eye Height @5 Gb/s • Eye Height @5 Gb/s closer than Eye Height @2.5 Gb/s 24
- 25. Tests with pre-emphasis current Ipeak is the additional current that adds to/subtracts from Imod during the period Tpeak over which the Pre-Emphasis/De-Emphasis takes place. 25
- 26. Tests with VCSEL Eye Diagram obtained with a VCSEL 26