![ Softcore processors
Case studies:
Xilinx Microblaze
Xilinx Picoblaze
DUGONG (a simplified
‘sort of’ interface
control processor)
[Optional:
Altera/Intel NIOS2]](https://image.slidesharecdn.com/softcoreprocessor-240222143001-b0414198/85/Softcore-processor-pptxSoftcore-processor-pptxSoftcore-processor-pptx-2-320.jpg)
![Direct mode
INPUT s5, 2a
ADD sa, sf
PORT[2a] s5
sa + sf sa
Indirect mode
INPUT s9, (s2)
STORE s3, (sa)
PORT[RAM[s2]]s9
s3 RAM[RAM[sa]]
s2+08+C s2
s7–7 s7
Immediate mode
ADDCY s2,08
SUB s7, 7
PicoBlaze Addressing Modes
Instruction example Explanation](https://image.slidesharecdn.com/softcoreprocessor-240222143001-b0414198/85/Softcore-processor-pptxSoftcore-processor-pptxSoftcore-processor-pptx-34-320.jpg)
![WRITE #0, [0xFF000000] // write 0 to address
READA [0xFF100000] // read from addr into A
WAIT #4 // wait for 4 clock cycles
WRITEA [0xFF200000] // write A to addr
BRANCH // send data in A to controller
NOP
NOP …](https://image.slidesharecdn.com/softcoreprocessor-240222143001-b0414198/85/Softcore-processor-pptxSoftcore-processor-pptxSoftcore-processor-pptx-47-320.jpg)
Softcore processor.pptxSoftcore processor.pptxSoftcore processor.pptx
- 1. Lecture 23 Softcore Processors Lecturer: Simon Winberg Attribution-ShareAlike 4.0 International (CC BY-SA 4.0)
- 2. Softcore processors Case studies: Xilinx Microblaze Xilinx Picoblaze DUGONG (a simplified ‘sort of’ interface control processor) [Optional: Altera/Intel NIOS2]
- 4. What is a ‘soft core’? A soft microprocessor is a microprocessor core that can be wholly implemented using logic synthesis. It is essentially an item of ‘Intellectual Property’ (IP) that contains the design of a processor. A soft core processors can be incorporated into a design and then the design synthesized, place & routed to generate an executable. Examples of these: Altera NIOS II Xilinx Microblaze & Xilinx Picoblaze A variety of ARM processors How do these compare to hard cores? … see later!
- 5. How a Soft core typically fits in to a design Soft Core Processor FPGA • Avalon bus for NIOS, • OPB (Onchip Peripheral Bus) or PLB (Processor Local Bus) for Microblaze
- 6. Address Bus for the Processor •FFT Engine •Timer •GPIO •Eth MAC •VGA •… etc …
- 7. Could implement it all as gates, but that can be rather inefficient and wasteful On-chip resources that soft core processors typically use: RAM blocks - various configurations Full adders DSP cores (e.g. integer multipliers, etc.) State machines
- 8. Hard core vs. Soft core ?!
- 9. Not implemented as gateware programmed into the FPGA logic Implemented in silicon/ASIC; unchangeable Benefits: Usually much higher performance Manufacturer typically provides optimized compiler for their chips
- 10. Reading (supplementary, not examined) “A Dual-Issue Embedded Processor for Low Power Devices” by H Lozano, M Ito The authors propose “an energy efficient dual-issue embedded processor that can deliver up to 60% improvement in IPC (instruction-per-cycle)…” Paper L21 - 07157822 - Dual-Issue Embedded Processor for Low Power Devices.pdf http://dx.doi.org/10.4108/icst.iniscom.2015.258414
- 11. MicroBlaze 32-bit processor, RISC instructions. Thirty-two 32-bit general purpose registers Generate, configure and program with Xilinx SDK Picoblaze 8 bit, simple RISC instructions Free for use on Xilinx DUGONG (a scenario showing example developed by a UCT student, a state machine with instructions) Planning to be control module Open-source NIOS II Altera’s soft core processor, 32 bit, configurable Commercial NIOS II Gen2 improved, more options Alternate soft cores: MP32 / MIPS32, ARM Simpler, closer to simple FSM More powerful, closer to full CPU NIOS is recommended additional reading (it is an Altera/Intel product)
- 12. A major purpose is: Make it easier to communicate / transfer & packetize data Test designs (e.g. like reading/adjusting setting while running) Set up the initial conditions of your design / HDL block configuration Highly configurable processor structure – e.g. add a custom instruction to baseline processor Of course also e.g. testing novel processor designs Should consider the soft core processor is More an aid to control the system facilitate comms, advantages of software running in system, e.g. O/S The soft core processor shouldn’t Be provide the main solution to you digital accelerator, unless there is good reason such as experimenting with performance of a cluster of processors on FPGA First two points are most common use
- 13. NIOS II Altera’s soft core processor, 32 bit, configurable Commercial NIOS II Gen2 improved, more options Alternate soft cores: MP32 / MIPS32, ARM More powerful, closer to full CPU NIOS is recommended additional reading, see last slides It is an Altera/Intel product
- 14. Soft Core Case Studies PicoBlaze Xilinx MicroBlaze DUGONG (Open source)
- 15. MicroBlaze was developed by Xilinx It is a soft microprocessor core designed and optimized for use on Xilinx FPGAs MicroBlaze is a Reduced Instruction Set Computer (RISC) Generated, configured and programmed using Xilinx EDK (Embedded Development Kit)
- 16. You can’t run it on any FPGA!! It works on only supported those Xilinx FPGAs. These include the FPGAs families: Spartan-3/3A/3AN/3A DSP/3E FPGA Spartan-6 Virtex-4 FX (also supports PowerPC 405 processors) and LX/SX FPGA Virtex-5 FXT (alost PowerPC 440 processor) LX/LXT FPGA (MicroBlaze) Virtex-6 (MicroBlaze processor)
- 17. Microblaze and its surrounding components Supports two bus Standards: • PLB (Processor Local Bus) (ver. V46) for high speed & high bandwidth peripherals. Supports 128 bits of data, 36 bit address • XILINX Local Memory Bus (LMB) to interface local PLBs
- 18. Cache By default MicroBlaze has no cache. Can enable cache in EDK (which will use BRAM)
- 20. Highly configurable soft processor Can select a specific set of features needed Fixed features of the processor are: Thirty-two 32-bit general purpose registers 32-bit instruction word with three operands and two addressing modes 32-bit address bus Single issue pipeline The MicroBlaze can be parameterized to enable inclusion of additional functionality.
- 21. The MicroBlaze has a versatile interconnect system to support a variety of embedded applications. MicroBlaze instruction set is similar to that of the RISC- based DLX architecture. Most vendor-supplied and third-party IP modules interface to PLB directly (or through an PLB to OPB bus bridge.) For access to local-memory (BRAM in the FPGA), the MicroBlaze uses a dedicated LMB bus that reduces loading on the other buses (e.g. OPB). User-defined coprocessors are supported through a dedicated FIFO-style connection called FSL (Fast Simplex Link). The coprocessor(s) interface can accelerate computationally intensive algorithms by offloading parts or the entirety of the computation to a user-designed hardware module.
- 22. High performance soft processor Most of instructions completed with 1 cycles Short pipelines, higher working frequency FPGA optimized implementation Fast carry chain MUX, hardware multiplier RLOC placement constraints Easy (relatively) to use with Xilinx EDK Linux/GCC support
- 23. No MMU support No protection among processes Implies it cannot support full version of Linux No double precision floating point No atomic instructions hard to implement lock non-blocking FIFO instruction problem No cache coherent support
- 24. A smaller, but powerful MicroBalze: The MicroBlaze MicroController System (MCS) MCS offers an even smaller package MCS consists of MicroBlaze in a fixed 3-stage pipeline configuration for the smallest footprint, and is surrounded by a system of common embedded design peripherals*. * MCS can run from IDS Logic Edition without the need for a full embedded design license
- 25. Xilinx MicroBlaze Wiki http://www.wiki.xilinx.com/MicroBlaze Wikipedia https://en.wikipedia.org/wiki/MicroBlaze Building an embedded system using a Microblaze on an Nexys3 http://islab.soe.uoguelph.ca/sareibi/TEACHING _dr/XILINX_TUTORIALS_dr/EDK_dr/EDK- NEXYS3-Elhossini2012.pdf Some of the information regarding MicroBlaze based on slides by K. Siddhapathak
- 26. Soft Core Case Studies PicoBlaze Xilinx MicroBlaze DUGONG (Open source)
- 27. Size: Takes on 96 slices !! (slice = group of PLBs) Big advantage considering low cost FPGAs have a few 100 slices; and 1000s slices for medium range Not coded as behavioral VHDL It is manually pre-compiled (IP block) Built by instantiation of Xilinx raw primitives Can still be simulated using Modelsim Info available from: www.xilinx.com/picoblaze
- 28. Main Uses Control / configuration of parameters Some data processing (add / integer operations) Comms / UI facilities (i.e. ‘talk’ to control PC, especially UART, USB connection) Testing & debugging your design on hardware
- 29. Can be very helpful to speed-up & simplify development Changing the instructions running on the softcore PicoBlaze is likely faster than changing the HDL code (especially with rebuilding time) Has a simple and easy to learn instruction set, also offers opportunities for reuse of the PicoBlaze code in other systems.
- 30. ECE 448 – FPGA and ASIC Design with VHDL PicoBlaze Architecture
- 31. Overview of the PicoBlaze
- 32. Interfacing to the PicoBlaze clock PicoBlaze KCPSM = constant (K) Coded Programmable State Machine
- 33. PicoBlaze Interface Name Direction Size Function clk input 1 System clock signal in reset input 1 Reset signal address output 10 Address of instruction mem. Specifies address of the instruction to be retrieved. Instruction input 18 Fetched instruction. port_id output 8 Address of the input or output port. in_port input 8 Input data from I/O peripherals. read_strobe output 1 Strobe associated with the input operation. out_port output 8 Output data to I/O peripherals. write_strobe output 1 Strobe associated with the output operation. interrupt input 1 Interrupt request from I/O peripherals. interrupt_ack output 1 Interrupt acknowledgment to I/O peripherals
- 34. Direct mode INPUT s5, 2a ADD sa, sf PORT[2a] s5 sa + sf sa Indirect mode INPUT s9, (s2) STORE s3, (sa) PORT[RAM[s2]]s9 s3 RAM[RAM[sa]] s2+08+C s2 s7–7 s7 Immediate mode ADDCY s2,08 SUB s7, 7 PicoBlaze Addressing Modes Instruction example Explanation
- 35. Example Program ; DEMONSTRATION PROGRAM ; EXERCISE THE 7 SEGMENT DISPLAYS cold_start: LOAD s3, 11 ; clear all time values OUTPUT s3, 04 LOAD s4, 00 OUTPUT s4, 05 main_loop: OUTPUT s5,04 ; Update 4 digit 7 seg display OUTPUT s3,06 JUMP main_loop
- 36. Soft Core Case Studies Nios II PicoBlaze Xilinx DUGONG (Open source)
- 37. Why look at this one This provides a case study of a custom-designed processor which provides a variety of useful facilities that are useful especially in configuring other modules in an FPGA, or being used as a junction for moving data around within the FPGA or steering the data to e.g. an output port or for doing debug inspections (kind of like a boot monitor for an FPGA; you can send it various commands – in machine language – and it can carry them out to do inspections on the modules running in the system)
- 38. Developed by Matthew Bridges (SDRG student), part of a larger research project Designed from scratch (a solution to a need) Design around compatibility with Wishbone interface Designed with a focus on simplicity with scalability But what is it??? Available at: https://github.com/matthewbridges/dugong
- 39. ‘DUGONG’ name? A dugong is actually a type of underwater mammal, colloquially called ‘sea cow’ that is found in the Indian Ocean (similarities to ‘manatees’) The DUGONG controller was given this name as it’s a ‘underwater’ hidden feature, and no one else is likely to choose the name… and it is a kind of grazer like a RHINO
- 40. Essentially it is a glorified state machine But has limited number of states and transition types (i.e. predefined list of triggers, operations, transitions, etc.)
- 41. Essentially it is a glorified state machine Works as follows: A list of timing and transfer operations are loaded into it, and it runs through these sequentially OP1 OP2 OP3 Data in OP1 OP2 OP3 Send config Redirect mode Config mode MODES: Various other modes, some simultaneous.
- 42. DUGONG Structure WISHBONE Has one register, the accumulator, through which data is transferred. To control processor interface (GPMC bus on RHINO)
- 43. Serves as the Master on the wishbone bus Wishbone bus: Open source hardware interconnect bus structure for connecting computational blocks within ICs / reconfigurable computers. This bus structure is commonly used by designs provided by OpenCores. Wishbone interfaces for Master and Slave modules
- 44. How DUGONG fits in to a Wishbone-based design Controls the wishbone clock lines, etc.
- 45. Designed around simplicity & scalability (connect up and configure small to big designs) Has no function unit (FU) – with good reason Can I use it for processing? Comparisons? Sorry, no can do: that is someone else's problem (or rather use a CPU e.g. Nios II) OpenCores.org: http://opencores.org/ Open Hardware Repository: http://www.ohwr.org/ There are lots of other opensource soft cores available, see e.g.:
- 46. DUGONG1: 4 bit Instruction Set Structure: <CODE:4 bits> <DATA:28 bits> Code Instruction Description 0000 NOP No operation 0001 WRITE Write data to addr 0010 READA Read from addr to acc 0011 WRITEA Write from acc to addr 0100 BRANCH write data to pc / controller 1000 WAIT Wait for a number of clock cycles equal to data field
- 47. WRITE #0, [0xFF000000] // write 0 to address READA [0xFF100000] // read from addr into A WAIT #4 // wait for 4 clock cycles WRITEA [0xFF200000] // write A to addr BRANCH // send data in A to controller NOP NOP …
- 49. Soft Core Case Studies Nios II PicoBlaze Xilinx DUGONG (Open source)
- 50. A 32-bit soft core processor from Altera Three standard cores versions: Fast, Standard, Light The cores have tradeoffs in: FPGA LEs needed power speed RISC architecture: Simple instructions Harvard Architecture: Separated data and instruction memories (a likely safer approach to the Von Neumann arch. style) 32 interrupt levels Avalon Bus interface C/C++ compilers; can also use plain assembly
- 51. NIOS II Architecture Image source: www.altera.com Let’s have a closer look at the core
- 52. NIOS II Core
- 53. How do you get a NIOS II soft core processor and set it up?
- 54. Altera Qsys: In later versions of Quartus II 1. Select Tools 2. Select Qsys
- 55. 1. Select Tools 2. Select SOPC Builder
- 56. Altera QSys
- 57. Image sources: man working on laptop – flickr scroll, video reel, big question mark – Pixabay http://pixabay.com/ (public domain) some diagrammatic elements are from Xilinx ISE screenshots https://commons.wikimedia.org/wiki/Category:Images (creative commons) Disclaimers and copyright/licensing details I have tried to follow the correct practices concerning copyright and licensing of material, particularly image sources that have been used in this presentation. I have put much effort into trying to make this material open access so that it can be of benefit to others in their teaching and learning practice. Any mistakes or omissions with regards to these issues I will correct when notified. To the best of my understanding the material in these slides can be shared according to the Creative Commons “Attribution-ShareAlike 4.0 International (CC BY-SA 4.0)” license, and that is why I selected that license to apply to this presentation (it’s not because I particularly want my slides referenced but more to acknowledge the sources and generosity of others who have provided free material such as the images I have used).