solution of question no.6inputPresent stateNext stateoutput.pdf
- 1. solution of question no.6 input Present state Next state output 0 S0 S0 0 1 S0 S1 0 0 S1 S2 0 1 S1 S1 0 0 S2 S3 0 1 S2 S1 0 0 S3 S0 0 1 S3
- 2. S4 0 0 S4 S2 1 1 S4 S1 1 library ieee; use IEEE.std_logic_1164.all; entity moore is port (clk : in std_logic; reset : in std_logic; input : in std_logic; output : out std_logic ); end moore; architecture behavioral of moore is type state_type is (s0,s1,s2,s3,s4); --type of state machine. signal current_s,next_s: state_type; --current and next state declaration. begin process (clk,reset) begin if (reset='1') then current_s <= s0; --default state on reset. elsif (rising_edge(clk)) then current_s <= next_s; --state change. end if; end process;
- 3. --state machine process. process (current_s,input) begin case current_s is when s0 => --when current state is "s0" if(input ='0') then output <= '0'; next_s <= s0; else output <= '0'; next_s <= s1; end if; when s1 =>; --when current state is "s1" if(input ='0') then output <= '0'; next_s <= s2; else output <= '0'; next_s <= s1; end if; when s2 => --when current state is "s2" if(input ='0') then output <= '0'; next_s <= s3; else output <= '0'; next_s <= s1; end if; when s3 => --when current state is "s3" if(input ='0') then output <= '1';
- 4. next_s <= s0; else output <= '0'; next_s <= s4; end if; when s4 => --when current state is "s4" if(input ='0') then output <= '1'; next_s <= s2; else output <= '1'; next_s <= s1; end if; end case; end process; end behavioral; solution of question no.7 input Present state Next state output 0 S0 S1 0 1 S0 S0 0 0 S1 S1 0 1
- 5. S1 S2 0 0 S2 S3 0 1 S2 S0 0 0 S3 S1 0 1 S3 S2 1 library ieee; use IEEE.std_logic_1164.all; entity mealy is port (clk : in std_logic; reset : in std_logic; input : in std_logic; output : out std_logic ); end mealy; architecture behavioral of moore is type state_type is (s0,s1,s2,s3); --type of state machine. signal current_s,next_s: state_type; --current and next state declaration. begin
- 6. process (clk,reset) begin if (reset='1') then current_s <= s0; --default state on reset. elsif (rising_edge(clk)) then current_s <= next_s; --state change. end if; end process; --state machine process. process (current_s,input) begin case current_s is when s0 => --when current state is "s0" if(input ='0') then output <= '0'; next_s <= s1; else output <= '0'; next_s <= s0; end if; when s1 =>; --when current state is "s1" if(input ='0') then output <= '0'; next_s <= s1; else output <= '0'; next_s <= s2; end if; when s2 => --when current state is "s2" if(input ='0') then output <= '0'; next_s <= s3;
- 7. else output <= '0'; next_s <= s1; end if; when s3 => --when current state is "s3" if(input ='0') then output <= '0'; next_s <= s1; else output <= '1'; next_s <= s2; end if; end case; end process; end behavioral; input Present state Next state output 0 S0 S0 0 1 S0 S1 0 0 S1 S2 0
- 8. 1 S1 S1 0 0 S2 S3 0 1 S2 S1 0 0 S3 S0 0 1 S3 S4 0 0 S4 S2 1 1 S4 S1 1 Solution solution of question no.6 input Present state Next state output
- 10. 1 S4 S1 1 library ieee; use IEEE.std_logic_1164.all; entity moore is port (clk : in std_logic; reset : in std_logic; input : in std_logic; output : out std_logic ); end moore; architecture behavioral of moore is type state_type is (s0,s1,s2,s3,s4); --type of state machine. signal current_s,next_s: state_type; --current and next state declaration. begin process (clk,reset) begin if (reset='1') then current_s <= s0; --default state on reset. elsif (rising_edge(clk)) then current_s <= next_s; --state change. end if; end process; --state machine process. process (current_s,input) begin case current_s is when s0 => --when current state is "s0"
- 11. if(input ='0') then output <= '0'; next_s <= s0; else output <= '0'; next_s <= s1; end if; when s1 =>; --when current state is "s1" if(input ='0') then output <= '0'; next_s <= s2; else output <= '0'; next_s <= s1; end if; when s2 => --when current state is "s2" if(input ='0') then output <= '0'; next_s <= s3; else output <= '0'; next_s <= s1; end if; when s3 => --when current state is "s3" if(input ='0') then output <= '1'; next_s <= s0; else output <= '0'; next_s <= s4; end if; when s4 => --when current state is "s4"
- 12. if(input ='0') then output <= '1'; next_s <= s2; else output <= '1'; next_s <= s1; end if; end case; end process; end behavioral; solution of question no.7 input Present state Next state output 0 S0 S1 0 1 S0 S0 0 0 S1 S1 0 1 S1 S2 0 0 S2 S3
- 13. 0 1 S2 S0 0 0 S3 S1 0 1 S3 S2 1 library ieee; use IEEE.std_logic_1164.all; entity mealy is port (clk : in std_logic; reset : in std_logic; input : in std_logic; output : out std_logic ); end mealy; architecture behavioral of moore is type state_type is (s0,s1,s2,s3); --type of state machine. signal current_s,next_s: state_type; --current and next state declaration. begin process (clk,reset) begin if (reset='1') then current_s <= s0; --default state on reset. elsif (rising_edge(clk)) then
- 14. current_s <= next_s; --state change. end if; end process; --state machine process. process (current_s,input) begin case current_s is when s0 => --when current state is "s0" if(input ='0') then output <= '0'; next_s <= s1; else output <= '0'; next_s <= s0; end if; when s1 =>; --when current state is "s1" if(input ='0') then output <= '0'; next_s <= s1; else output <= '0'; next_s <= s2; end if; when s2 => --when current state is "s2" if(input ='0') then output <= '0'; next_s <= s3; else output <= '0'; next_s <= s1; end if;
- 15. when s3 => --when current state is "s3" if(input ='0') then output <= '0'; next_s <= s1; else output <= '1'; next_s <= s2; end if; end case; end process; end behavioral; input Present state Next state output 0 S0 S0 0 1 S0 S1 0 0 S1 S2 0 1 S1 S1 0 0 S2