Speeding Up Resting State Networks Recognition via a Hardware Accelerator
0 likes37 views
The document presents a hardware acceleration solution for the analysis of resting state networks (RSNs) using a FastICA algorithm, aimed at improving the identification of neurodegenerative diseases. The hardware implementation achieved a significant speedup of 5x compared to standard software methods, reducing execution time from 38.116 seconds to 7.278 seconds. Future work will focus on further optimizing the design and implementing additional filtering techniques for real-time analysis.
![Resting State Networks (RSNs)
3
Resting-State Networks (RSNs): synchronous
fluctuations between regions spatially distinct, occurring in the
absence of a task or stimulus.[1]
[1] [Bharat Biswal, F. Zerrin Yetkin, Victor M. Haughton, James S. Hyde, "Functional connectivity in the motor cortex using Echo-Planar MRI", Magn Reson Med, n.41 (1995), 34:537](https://image.slidesharecdn.com/fastbrain-190516145311/85/Speeding-Up-Resting-State-Networks-Recognition-via-a-Hardware-Accelerator-3-320.jpg)
![In FastICA algorithm we used mainly two ILP techniques:
● Pipeline
● Unrolling: We have used in on loops handling smaller vectors, to enhance
performance with replicated hardware that performs so in parallel multiple loop
iterations.
int sum = 0;
for (int i = 0; i < 10; i++) {
sum += a[i];
}
with loop unrolling
int sum = 0;
for (int i = 0; i < 10; i += 2) {
sum += a[i];
sum += a[i +1];
}
12
Hardware Accelerations](https://image.slidesharecdn.com/fastbrain-190516145311/85/Speeding-Up-Resting-State-Networks-Recognition-via-a-Hardware-Accelerator-12-320.jpg)
![Results: execution time
Implementations Execution time [s]
Our HW implementation 7.278
GIFT SW 38.116
Speed up of
5x
14](https://image.slidesharecdn.com/fastbrain-190516145311/85/Speeding-Up-Resting-State-Networks-Recognition-via-a-Hardware-Accelerator-14-320.jpg)
Speeding Up Resting State Networks Recognition via a Hardware Accelerator
- 1. Speeding Up Resting State Networks Recognition via a Hardware Accelerator Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano Filippo Carloni filippo.carloni@mail.polimi.it Giada Casagrande Valentina Corbetta Andrea Agostinelli Luca Cerina Emanuele Del Sozzo Marco D. Santambrogio NGCX, San Francisco – May 17-31, 2019
- 2. Context Definition 2 Long-term analysis of alterations in brain functional connectivity Identification of neurodegenerative diseases and attention deficit disorders
- 3. Resting State Networks (RSNs) 3 Resting-State Networks (RSNs): synchronous fluctuations between regions spatially distinct, occurring in the absence of a task or stimulus.[1] [1] [Bharat Biswal, F. Zerrin Yetkin, Victor M. Haughton, James S. Hyde, "Functional connectivity in the motor cortex using Echo-Planar MRI", Magn Reson Med, n.41 (1995), 34:537
- 4. Independent Component Analysis (ICA) 4 fMRI analysis using ICA requires a large amount of matrix multiplications on big data ICA method Resting-State NetworksBrain Signals
- 6. Technical Challenges 6 power consumptionexecution time A standard software implementation on CPU would not be capable to converge to a solution in a short amount of time and would need high power consumption
- 7. Proposed Solution 7 Send to the remote service Retrieve results ElaborationPatient Images
- 8. Data Processing Images loading Pre- processing FastICA Post- processing Images reconstructio n and saving 8
- 9. Temporal Profile 9 Temporal Profile relative to the previous phases
- 10. Why FPGAs 10
- 11. Hardware Accelerations In FastICA algorithm we used mainly two ILP techniques: ● Pipeline: We used pipeline on loops handling big vectors, since in FastICA the iterations do not depend on the previous ones, so it’s very efficient to perform loops iterations with partially overlapping. 11
- 12. In FastICA algorithm we used mainly two ILP techniques: ● Pipeline ● Unrolling: We have used in on loops handling smaller vectors, to enhance performance with replicated hardware that performs so in parallel multiple loop iterations. int sum = 0; for (int i = 0; i < 10; i++) { sum += a[i]; } with loop unrolling int sum = 0; for (int i = 0; i < 10; i += 2) { sum += a[i]; sum += a[i +1]; } 12 Hardware Accelerations
- 13. Results: significant components Image from: Storti, Silvia Francesca, et al. "Automatic selection of resting-state networks with functional magnetic resonance imaging." Frontiers in neuroscience 7 (2013): 72. 13
- 14. Results: execution time Implementations Execution time [s] Our HW implementation 7.278 GIFT SW 38.116 Speed up of 5x 14
- 15. Conclusions and future works ● The main purpose of our work was to obtain a significant speed up with respects to the state of the art, which has been reached (5x) ● As future works we aim to improve the design optimization ● We would also like to implement other filters to reduce movement artifacts and noise ● We would like to implement in hardware also the other steps of our code to reach a real-time analysis 15
- 16. Thank you for your attention 16 Filippo Carloni filippo.carloni@mail.polimi.it Giada Casagrande Valentina Corbetta Andrea Agostinelli Luca Cerina Emanuele Del Sozzo Marco D. Santambrogio