St16c550v430 uart with 16-byte fifo’s
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The document describes the ST16C550 UART chip, which features a 16-byte transmit FIFO, 16-byte receive FIFO, and full duplex operation. It is pin-compatible with the NS16C550 UART and operates at speeds from 2.97V to 5.5V with a programmable baud rate generator from 50 bps to 1.5 Mbps. The chip provides status registers for error conditions and transfer status as well as interrupt capabilities. It is available in 40-pin PDIP, 44-pin PLCC, and 48-pin TQFP packages.
![ST16C550
T = [(programmed word length = 7) + (stop bit = 1) + For internal clock oscillator operation, an industry
(start bit = 1) = 9]. 40 (bit times divided by 9) = 4.4 standard microprocessor crystal (parallel resonant/ 22
characters. pF load) is connected externally between the XTAL1
and XTAL2 pins, with an external 1 MΩ resistor across
Example -B: If the user programs the word length = 7, it. Alternatively, an external clock can be connected to
with parity and one stop bit, the time out will be: the XTAL1 pin to clock the internal baud rate generator
T = 4 X 7(programmed word length) + 12 = 40 bit times. for standard or custom rates. See figure 3 for crystal
Character time = 40 / 10 [ (programmed word length oscillator connection.
= 7) + (parity = 1) + (stop bit = 1) + (start bit = 1) = 4
characters. The generator divides the input 16X clock by any
divisor from 1 to 216 -1. The ST16C550 divides the
Programmable Baud Rate Generator basic crystal or external clock by 16. The frequency of
the -BAUDOUT output pin is exactly 16X (16 times) of
The ST16C550 supports high speed modem tech- the selected baud rate (-BAUDOUT =16 x Baud Rate).
nologies that have increased input data rates by Customized Baud Rates can be achieved by selecting
employing data compression schemes. For example the proper divisor values for the MSB and LSB sec-
a 33.6Kbps modem that employs data compression tions of baud rate generator.
may require a 115.2Kbps input data rate. A 128.0Kbps
ISDN modem that supports data compression may Programming the Baud Rate Generator Registers
need an input data rate of 460.8Kbps. The ST16C550 DLM (MSB) and DLL (LSB) provides a user capability
can support a standard data rate of 921.6Kbps. for selecting the desired final baud rate. The example
in Table 3 below shows selectable baud rates when
The programmable Baud Rate Generator is capable using a 1.8432 MHz crystal.
of accepting an input clock up to 24 MHz, as required
for supporting a 1.5Mbps data rate. The ST16C550 can For custom baud rates, the divisor value can be calcu-
be configured for internal or external clock operation. lated using the following equation:
Divisor (in decimal) = (XTAL1 clock frequency) / (serial data rate x 16)
Table 3, BAUD RATE GENERATOR PROGRAMMING TABLE (1.8432 MHz CLOCK):
Output User User DLM DLL
Baud Rate 16 x Clock 16 x Clock Program Program
Divisor Divisor Value Value
(Decimal) (HEX) (HEX) (HEX)
50 2304 900 09 00
75 1536 600 06 00
150 768 300 03 00
300 384 180 01 80
600 192 C0 00 C0
1200 96 60 00 60
2400 48 30 00 30
4800 24 18 00 18
7200 16 10 00 10
9600 12 0C 00 0C
19.2k 6 06 00 06
38.4k 3 03 00 03
57.6k 2 02 00 02
115.2k 1 01 00 01
Rev. 4.30
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![ST16C550
REGISTER FUNCTIONAL DESCRIPTIONS
The following table delineates the assigned bit functions for the twelve ST16C550 internal registers. The assigned
bit functions are more fully defined in the following paragraphs.
Table 4, ST16C550 INTERNAL REGISTERS
A2 A1 A0 Register BIT-7 BIT-6 BIT-5 BIT-4 BIT-3 BIT-2 BIT-1 BIT-0
[Default]
Note *2
General Register Set
0 0 0 RHR [XX] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0
0 0 0 THR [XX] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0
0 0 1 IER [00] 0 0 0 0 modem receive transmit receive
status line holding holding
interrupt status register register
interrupt
0 1 0 FCR [00] RCVR RCVR 0 0 DMA XMIT RCVR FIFO
trigger trigger mode FIFO FIFO enable
(MSB) (LSB) select reset reset
0 1 0 ISR [01] FIFO’s FIFO’s 0 0 INT INT INT INT
enabled enabled priority priority priority status
bit-2 bit-1 bit-0
0 1 1 LCR [00] divisor set set even parity stop word word
latch break parity parity enable bits length length
enable bit-1 bit-0
1 0 0 MCR [00] 0 0 0 loopback -OP2 -OP1 -RTS -DTR
enable
1 0 1 LSR [60] FIFO trans. trans. break framing parity overrun receive
data empty holding interrupt error error error data
error empty ready
1 1 0 MSR [X0] CD RI DSR CTS delta delta delta delta
-CD -RI -DSR -CTS
1 1 1 SPR [FF] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0
Baud Rate Generator Divisor Registers. Accessible when LCR bit-7 is set to logic 1. Note 1*
0 0 0 DLL [XX] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0
0 0 1 DLM [XX] bit-15 bit-14 bit-13 bit-12 bit-11 bit-10 bit-9 bit-8
Note *1: The BRG registers are accessible only when LCR bit-7 is set to a logic 1.
Note *2: The value represents the register’s initialized HEX value. An “X” signifies a 4-bit un-initialized nibble.
Rev. 4.30
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![ST16C550
Interrupt Status Register (ISR)
The ST16C550 provides four levels of prioritized inter-
rupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with six
interrupt status bits. Performing a read cycle on the ISR
will provide the user with the highest pending interrupt
level to be serviced. No other interrupts are acknowl-
edged until the pending interrupt is serviced. Whenever
the interrupt status register is read, the interrupt status
is cleared. However it should be noted that only the
current pending interrupt is cleared by the read. A lower
level interrupt may be seen after rereading the interrupt
status bits. The Interrupt Source Table 5 (below) shows
the data values (bit 0-3) for the four prioritized interrupt
levels and the interrupt sources associated with each of
these interrupt levels:
Table 5, INTERRUPT SOURCE TABLE
Priority [ISR]
Level Bit-3 Bit-2 Bit-1 Bit-0 Source of the interrupt
X 0 0 0 1 No interrupt pending
1 0 1 1 0 LSR (Receiver Line Status Register)
2 0 1 0 0 RXRDY (Received Data Ready)
2 1 1 0 0 RXRDY (Receive Data time out)
3 0 0 1 0 TXRDY ( Transmitter Holding Register Empty)
4 0 0 0 0 MSR (Modem Status Register)
Rev. 4.30
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St16c550v430 uart with 16-byte fifo’s
- 1. ST16C550 UART WITH 16-BYTE FIFO’s September 2003 GENERAL DESCRIPTION PLCC Package The ST16C550 (550) is a universal asynchronous re- ceiver and transmitter with 16 byte transmit and receive FIFO. It operates at 2.97 to 5.5 volts. A programmable -DSR -CTS VCC N.C. -CD -RI D4 D3 D2 D1 D0 baud rate generator can select transmit and receive 44 43 42 41 40 6 5 4 3 2 1 clock rates from 50 bps to 1.5 Mbps. The ST16C550 is an improved version of the NS16C550 D5 7 39 RESET UART with higher operating speed and lower access D6 8 38 -OP1 time. The ST16C550 on board status registers provides D7 9 37 -DTR the error conditions, type and status of the transfer RCLK 10 36 -RTS operation being performed. Included is complete MO- RX 11 35 -OP2 DEM control capability, and a processor interrupt N.C. 12 ST16C550CJ44 34 N.C. TX 13 33 INT system that may be software tailored to the user’s CS0 14 32 -RXRDY requirements. The ST16C550 provides internal loop- CS1 15 31 A0 back capability for on board diagnostic testing. -CS2 16 30 A1 The ST16C550 is available in 40 pin PDIP, 44 pin PLCC, -BAUDOUT 17 29 A2 and 48 pin TQFP packages. It is fabricated in an 18 19 20 21 22 23 24 25 26 27 28 advanced CMOS process to achieve low drain power and high speed requirements. -IOW XTAL1 XTAL2 -IOR -DDIS -TXRDY -AS IOW N.C. GND IOR FEATURES • Pin to pin and functionally compatible to the Industry Standard 16C550 • 2.97 to 5.5 volt operation • 24MHz clock operation at 5V • 16MHz clock operation at 3.3V • 16 byte transmit FIFO • 16 byte receive FIFO with error flags • Full duplex operation • Transmit and receive control • Four selectable receive FIFO interrupt trigger levels • Standard modem interface • Compatible with ST16C450 • Low operating current ( 1.2mA typ.) ORDERING INFORMATION Part number Package Operating temperature Device Status ST16C550CP40 40-Lead PDIP 0° C to + 70° C Active. See the ST16C550CQ48 for new designs. ST16C550CJ44 44-Lead PLCC 0° C to + 70° C Active ST16C550CQ48 48-Lead TQFP 0° C to + 70° C Active ST16C550IP40 40-Lead PDIP -40° C to + 85° C Active. See the ST16C550IQ48 for new designs. ST16C550IJ44 44-Lead PLCC -40° C to + 85° C Active ST16C550IQ48 48-Lead TQFP -40° C to + 85° C Active Rev. 4.30 EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 • (510) 668-7000 • FAX (510) 668-7017
- 2. ST16C550 Figure 1, PACKAGE DESCRIPTION, ST16C550 48 Pin TQFP Package 40 Pin DIP Package -DSR -CTS VCC N.C. N.C. -CD -RI D0 1 40 VCC D4 D3 D2 D1 D0 D1 2 39 -RI 48 47 46 45 44 43 42 41 40 39 38 37 D2 3 38 -CD N.C. 1 36 N.C. D3 4 37 -DSR D5 2 35 RESET D4 5 36 -CTS D6 3 34 -OP1 D5 6 35 RESET D7 4 33 -DTR D6 7 34 -OP1 RCLK 5 32 -RTS ST16C550CP40 N.C. 6 31 -OP2 D7 8 33 -DTR ST16C550CQ48 RX 7 30 INT RCLK 9 32 -RTS TX 8 29 -RXRDY RX 10 31 -OP2 CS0 9 28 A0 TX 11 30 INT CS1 10 27 A1 CS0 12 29 -RXRDY -CS2 11 26 A2 CS1 13 28 A0 -BAUDOUT 12 25 N.C. -CS2 14 27 A1 13 14 15 16 17 18 19 20 21 22 23 24 -BAUDOUT 15 26 A2 -AS GND N.C. -IOW N.C. XTAL1 XTAL2 -DDIS -TXRDY IOW -IOR IOR XTAL1 16 25 -AS XTAL2 17 24 -TXRDY -IOW 18 23 -DDIS IOW 19 22 IOR GND 20 21 -IOR Rev. 4.30 2
- 3. ST16C550 Figure 2, BLOCK DIAGRAM Transmit Transmit FIFO Shift TX Control Logic D0-D7 Registers Register Data bus -IOR,IOR & -IOW,IOW RESET Receive Receive Inter Connect Bus Lines FIFO Shift RX Control signals Registers Register & A0-A2 Register Select Logic -AS CS0,CS1 -CS2 -DDIS -DTR,-RTS -OP1,-OP2 Modem -CTS Clock Control Interrupt -RI Control INT Logic & Logic -RXRDY -CD Baud Rate -DSR -TXRDY Generator XTAL1 XTAL2 RCLK -BAUDOUT Rev. 4.30 3
- 4. ST16C550 SYMBOL DESCRIPTION Symbol Pin Signal Pin Description 40 44 48 type A0 28 31 28 I Address-0 Select Bit Internal registers address selection. A1 27 30 27 I Address-1 Select Bit Internal registers address selection. A2 26 29 26 I Address-2 Select Bit Internal registers address selection. IOR 22 25 20 I Read data strobe. Its function is the same as -IOR (see - IOR), except it is active high. Either an active -IOR or IOR is required to transfer data from 16C550 to CPU during a read operation. Connect to logic 0 when using -IOR. CS0 12 14 9 I Chip Select-0. Logical 1 on this pin provides the chip select- 0 function. Connect CS0 to logic 1 if using CS1 or -CS2. CS1 13 15 10 I Chip Select-1. Logical 1 on this pin provides the chip select- 1 function. Connect CS1 to logic 1 if using CS0 or -CS2. -CS2 14 16 11 I Chip Select -2. Logical 0 on this pin provides the chip select- 2 function. Connect to logic 0 if using CS0 or CS1. IOW 19 21 17 I Write data strobe. Its function is the same as -IOW (see - IOW), but it acts as an active high input signal. Either -IOW or IOW is required to transfer data from the CPU to ST16C550 during a write operation. Connect to logic 0 when using -IOW. -AS 25 28 24 I Address Strobe. A logic 1 transition on -AS latches the state of the chip selects and the register select bits, A0-A2. This input is used when address and chip selects are not stable for the duration of a read or write operation, i.e., a micropro- cessor that needs to de-multiplex the address and data bits. If not required, the -AS input can be permanently tied to a logic 0. D0-D7 1-8 2-9 43-47 2-4 I/O Data Bus (Bi-directional) - These pins are the eight bit, tri- state data bus for transferring information to or from the controlling CPU. D0 is the least significant bit and the first data bit in a transmit or receive serial data stream. GND 20 22 18 Pwr Signal and Power Ground. Rev. 4.30 4
- 5. ST16C550 SYMBOL DESCRIPTION Symbol Pin Signal Pin Description 40 44 48 type -IOR 21 24 19 I Read data strobe (active low strobe). A logic 0 on this pin transfers the contents of the ST16C550 data bus to the CPU. Connect to logic 1 when using IOR. -IOW 18 20 16 I Write data strobe (active low strobe). A logic 0 on this pin transfers the contents of the CPU data bus to the addressed internal register. Connect to logic 1 when using IOW. INT 30 33 30 O Interrupt Request (active high). Interrupts are enabled in the interrupt enable register (IER), and when an interrupt con- dition exists. Interrupt conditions include: receiver errors, available receiver buffer data, transmit buffer empty, or when a modem status flag is detected. -RXRDY 29 32 29 O Receive Ready. When operating in the FIFO mode, one of two types of DMA signaling can be selected using the FIFO control register bit-3. When operating in the ST16C450 mode, only DMA mode “0” is allowed. Mode “0” supports single transfer DMA in which a transfer is made between CPU bus cycles. Mode “1” supports multi-transfer DMA in which multiple transfers are made continuously until the receiver FIFO has been emptied. In DMA mode “0” -RXRDY is low, when there is at least one character in the receiver FIFO or receive holding register. In DMA mode “1”, -RXRDY is low, when the trigger level or the time-out has been reached. -TXRDY 24 27 23 O Transmit Ready. When operating in the FIFO mode, one of two types of DMA signaling can be selected using the FIFO control register bit-3. When operating in the ST16C450 mode, only DMA mode “0” is allowed. Mode “0” supports single transfer DMA in which a transfer is made between CPU bus cycles. Mode “1” supports multi-transfer DMA in which multiple transfers are made continuously until the transmit FIFO has been filled. -BAUDOUT 15 17 12 O Baud Rate Generator Output. This pin provides the 16X clock of the selected data rate from the baud rate generator. The RCLK pin must be connected externally to -BAUDOUT when the receiver is operating at the same data rate. Rev. 4.30 5
- 6. ST16C550 SYMBOL DESCRIPTION Symbol Pin Signal Pin Description 40 44 48 type -DDIS 23 26 22 O Drive Disable. This pin goes to a logic 0 when the external CPU is reading data from the ST16C550. This signal can be used to disable external transceivers or other logic func- tions. -OP1 34 38 34 O Output-1 (User Defined) - See bit-2 of modem control register (MCR bit-2). RESET 35 39 35 I Reset. (active high) - A logic 1 on this pin will reset the internal registers and all the outputs. The UART transmitter output and the receiver input will be disabled during reset time. (See ST16C550 External Reset Conditions for initial- ization details.) RCLK 9 10 5 I Receive Clock Input. This pin is used as external 16X clock input to the receiver section. External connection to - Baudout pin is required in order to utilize the internal baud rate generator. -OP2 31 35 31 O Output-2 (User Defined). This pin provides the user a general purpose output. See bit-3 modem control register (MCR bit-3). VCC 40 44 42 Pwr Power Supply Input. XTAL1 16 18 14 I Crystal or External Clock Input - Functions as a crystal input or as an external clock input. A crystal can be connected between this pin and XTAL2 to form an internal oscillator circuit. An external 1 MΩ resistor is required between the XTAL1 and XTAL2 pins (see figure 3). Alternatively, an external clock can be connected to this pin to provide custom data rates (Programming Baud Rate Generator section). XTAL2 17 19 15 O Output of the Crystal Oscillator or Buffered Clock - (See also XTAL1). Crystal oscillator output or buffered clock output. -CD 38 42 40 I Carrier Detect (active low) - A logic 0 on this pin indicates that a carrier has been detected by the modem. Rev. 4.30 6
- 7. ST16C550 SYMBOL DESCRIPTION Symbol Pin Signal Pin Description 40 44 48 type -CTS 36 40 38 I Clear to Send (active low) - A logic 0 on the -CTS pin indicates the modem or data set is ready to accept transmit data from the ST16C550. Status can be tested by reading MSR bit-4. This pin has no effect on the UART’s transmit or receive operation. -DSR 37 41 39 I Data Set Ready (active low) - A logic 0 on this pin indicates the modem or data set is powered-on and is ready for data exchange with the UART. This pin has no effect on the UART’s transmit or receive operation. -DTR 33 37 33 O Data Terminal Ready (active low) - A logic 0 on this pin indicates that the ST16C550 is powered-on and ready. This pin can be controlled via the modem control register. Writing a logic 1 to MCR bit-0 will set the -DTR output to logic 0, enabling the modem. This pin will be a logic 1 after writing a logic 0 to MCR bit-0, or after a reset. This pin has no effect on the UART’s transmit or receive operation. -RI 39 43 41 I Ring Indicator (active low) - A logic 0 on this pin indicates the modem has received a ringing signal from the telephone line. A logic 1 transition on this input pin will generate an interrupt. -RTS 32 36 32 O Request to Send (active low) - A logic 0 on the -RTS pin indicates the transmitter has data ready and waiting to send. Writing a logic 1 in the modem control register (MCR bit-1) will set this pin to a logic 0 indicating data is available. After a reset this pin will be set to a logic 1. This pin has no effect on the UART’s transmit or receive operation. RX 10 11 7 I Receive Data - This pin provides the serial receive data input to the ST16C550. A logic 1 indicates no data or an idle channel. During the local loop-back mode, the RX input pin is disabled and TX data is internally connected to the UART RX Input, internally, see figure 12. TX 11 13 8 O Transmit Data - This pin provides the serial transmit data from the ST16C550, the TX signal will be a logic 1 during reset, idle (no data). During the local loop-back mode, the TX pin is set to a logic 1 and TX data is internally connected to the UART RX Input, see figure 12. Rev. 4.30 7
- 8. ST16C550 GENERAL DESCRIPTION FUNCTIONAL DESCRIPTIONS The ST16C550 provides serial asynchronous receive Internal Registers data synchronization, parallel-to-serial and serial-to- parallel data conversions for both the transmitter and The ST16C550 provides 12 internal registers for receiver sections. These functions are necessary for monitoring and control. These registers are shown in converting the serial data stream into parallel data that Table 3 below. These registers function as data hold- is required with digital data systems. Synchronization ing registers (THR/RHR), interrupt status and control for the serial data stream is accomplished by adding registers (IER/ISR), a FIFO control register (FCR), start and stops bits to the transmit data to form a data line status and control registers, (LCR/LSR), modem character (character orientated protocol). Data integ- status and control registers (MCR/MSR), program- rity is insured by attaching a parity bit to the data mable data rate (clock) control registers (DLL/DLM), character. The parity bit is checked by the receiver for and a user assessable scratchpad register (SPR). any transmission bit errors. The electronic circuitry to provide all these functions is fairly complex especially when manufactured on a single integrated silicon chip. The ST16C550 represents such an integration with greatly enhanced features. The ST16C550 is fabricated with an advanced CMOS process. The ST16C550 is an upward solution that provides 16 bytes of transmit and receive FIFO memory, instead of 1 byte provided in the 16C450. The ST16C550 is designed to work with high speed modems and shared network environments, that require fast data process- ing time. Increased performance is realized in the ST16C550 by the larger transmit and receive FIFO’s. This allows the external processor to handle more networking tasks within a given time. The 4 selectable levels of FIFO trigger provided for maximum data throughput performance especially when operating in a multi-channel environment. The combination of the above greatly reduces the bandwidth requirement of the external controlling CPU, increases performance, and reduces power consumption. The ST16C550 is capable of operation to 1.5Mbps with a 24 MHz crystal or external clock input. With a crystal of 14.7464 MHz and through a software option, the user can select data rates up to 460.8Kbps or 921.6Kbps. Rev. 4.30 8
- 9. ST16C550 Table 2, INTERNAL REGISTER DECODE A2 A1 A0 READ MODE WRITE MODE General Register Set (THR/RHR, IER/ISR, MCR/MSR, LCR/LSR, SPR): 0 0 0 Receive Holding Register Transmit Holding Register 0 0 1 Interrupt Enable Register Interrupt Enable Register 0 1 0 Interrupt Status Register FIFO Control Register 0 1 1 Line Control Register Line Control Register 1 0 0 Modem Control Register Modem Control Register 1 0 1 Line Status Register Reserved 1 1 0 Modem Status Register Reserved 1 1 1 Scratchpad Register Scratchpad Register Baud Rate Generator Registers (DLL/DLM). Accessible only when LCR bit-7 is set to 1. 0 0 0 LSB of Divisor Latch LSB of Divisor Latch 0 0 1 MSB of Divisor Latch MSB of Divisor Latch FIFO Operation The 16 byte transmit and receive data FIFO’s are In this case the ST16C550 FIFO may hold more char- enabled by the FIFO Control Register (FCR) bit-0. acters than the programmed trigger level. Following the With 16C550 devices, the user can set the receive removal of a data byte, the user should recheck LSR bit- trigger level but not the transmit trigger level. The 0 for additional characters. A Receive Time Out will not receiver FIFO section includes a time-out function to occur if the receive FIFO is empty. The time out counter ensure data is delivered to the external CPU. An is reset at the center of each stop bit received or each interrupt is generated whenever the Receive Holding time the receive holding register (RHR) is read (see Register (RHR) has not been read following the load- Figure 10, Receive Time-out Interrupt). The actual time ing of a character or the receive trigger level has not out value is T (Time out length in bits) = 4 X P been reached. (Programmed word length) + 12. To convert the time out value to a character value, the user has to consider the Time-out Interrupts complete word length, including data information length, start bit, parity bit, and the size of stop bit, i.e., When two interrupt conditions have the same priority, 1X, 1.5X, or 2X bit times. it is important to service these interrupts correctly. Receive Data Ready and Receive Time Out have the Example -A: If the user programs a word length of 7, same interrupt priority (when enabled by IER bit-0). with no parity and one stop bit, the time out will be: The receiver issues an interrupt after the number of T = 4 X 7( programmed word length) +12 = 40 bit times. characters have reached the programmed trigger level. The character time will be equal to 40 / 9 = 4.4 characters, or as shown in the fully worked out example: Rev. 4.30 9
- 10. ST16C550 T = [(programmed word length = 7) + (stop bit = 1) + For internal clock oscillator operation, an industry (start bit = 1) = 9]. 40 (bit times divided by 9) = 4.4 standard microprocessor crystal (parallel resonant/ 22 characters. pF load) is connected externally between the XTAL1 and XTAL2 pins, with an external 1 MΩ resistor across Example -B: If the user programs the word length = 7, it. Alternatively, an external clock can be connected to with parity and one stop bit, the time out will be: the XTAL1 pin to clock the internal baud rate generator T = 4 X 7(programmed word length) + 12 = 40 bit times. for standard or custom rates. See figure 3 for crystal Character time = 40 / 10 [ (programmed word length oscillator connection. = 7) + (parity = 1) + (stop bit = 1) + (start bit = 1) = 4 characters. The generator divides the input 16X clock by any divisor from 1 to 216 -1. The ST16C550 divides the Programmable Baud Rate Generator basic crystal or external clock by 16. The frequency of the -BAUDOUT output pin is exactly 16X (16 times) of The ST16C550 supports high speed modem tech- the selected baud rate (-BAUDOUT =16 x Baud Rate). nologies that have increased input data rates by Customized Baud Rates can be achieved by selecting employing data compression schemes. For example the proper divisor values for the MSB and LSB sec- a 33.6Kbps modem that employs data compression tions of baud rate generator. may require a 115.2Kbps input data rate. A 128.0Kbps ISDN modem that supports data compression may Programming the Baud Rate Generator Registers need an input data rate of 460.8Kbps. The ST16C550 DLM (MSB) and DLL (LSB) provides a user capability can support a standard data rate of 921.6Kbps. for selecting the desired final baud rate. The example in Table 3 below shows selectable baud rates when The programmable Baud Rate Generator is capable using a 1.8432 MHz crystal. of accepting an input clock up to 24 MHz, as required for supporting a 1.5Mbps data rate. The ST16C550 can For custom baud rates, the divisor value can be calcu- be configured for internal or external clock operation. lated using the following equation: Divisor (in decimal) = (XTAL1 clock frequency) / (serial data rate x 16) Table 3, BAUD RATE GENERATOR PROGRAMMING TABLE (1.8432 MHz CLOCK): Output User User DLM DLL Baud Rate 16 x Clock 16 x Clock Program Program Divisor Divisor Value Value (Decimal) (HEX) (HEX) (HEX) 50 2304 900 09 00 75 1536 600 06 00 150 768 300 03 00 300 384 180 01 80 600 192 C0 00 C0 1200 96 60 00 60 2400 48 30 00 30 4800 24 18 00 18 7200 16 10 00 10 9600 12 0C 00 0C 19.2k 6 06 00 06 38.4k 3 03 00 03 57.6k 2 02 00 02 115.2k 1 01 00 01 Rev. 4.30 10
- 11. ST16C550 DMA Operation D0-D7. The user optionally compares the received data to the initial transmitted data for verifying error free The ST16C550 FIFO trigger level provides additional operation of the UART TX/RX circuits. flexibility to the user for block mode operation. The user can optionally operate the transmit and receive FIFO’s In this mode , the receiver and transmitter interrupts are in the DMA mode (FCR bit-3). The DMA mode affects fully operational. The Modem Control Interrupts are also the state of the -RXRDY and -TXRDY output pins. The operational. The interrupts are still controlled by the following tables show this: IER. -RXRDY pin: Non-DMA mode DMA mode 1 = FIFO empty 0 to 1 transition when FIFO empties 0 = at least 1 byte 1 to 0 transition when FIFO in FIFO reaches trigger level, or timeout occurs -TXRDY pin: Non-DMA mode DMA mode 1 = at least 1 byte 1 = FIFO is full in FIFO 0 = FIFO empty 0 = FIFO has at least 1 empty location Figure 3, TYPICAL EXTERNAL CRYSTAL OSCILLA- TOR CONNECTION Loop-back Mode The internal loop-back capability allows onboard diag- nostics. In the loop-back mode the normal modem interface pins are disconnected and reconfigured for loop-back internally. In this mode MSR bits 4-7 are also disconnected. However, MCR register bits 0-3 can be used for controlling loop-back diagnostic test- XTAL1 XTAL2 ing. In the loop-back mode -OP1 and -OP2 in the MCR register (bits 0-1) control the modem -RI and -CD R1 inputs respectively. MCR signals -DTR and -RTS (bits 0 -1 2 0 (O p tio n a l) 0-1) are used to control the modem -CTS and -DSR inputs respectively. The transmitter output (TX) and the R2 receiver input (RX) are disconnected from their associ- 1M Y1 ated interface pins, and instead are connected together internally (See Figure 4). The -CTS, -DSR, -CD, and -RI 1 .8 4 3 2 - 2 4 M H z are disconnected from their normal modem control C1 C2 2 2 -4 7 p F 2 2 -4 7 p F inputs pins, and instead are connected internally to - DTR, -RTS, -OP1 and -OP2. Loop-back test data is entered into the transmit holding register via the user data bus interface, D0-D7. The transmit UART serial- izes the data and passes the serial data to the receive UART via the internal loop-back connection. The receive UART converts the serial data back into parallel data that is then made available at the user data interface, Rev. 4.30 11
- 12. ST16C550 Figure 4, INTERNAL LOOP-BACK MODE DIAGRAM VCC T ra n sm it T ra n sm it TX Control Logic F IF O S h ift D 0 -D 7 Data bus R eg isters R eg ister & MCR Bit-4=1 -IO R ,IO R -IO W ,IO W R E SE T R eceive R eceive F IF O S h ift R eg isters R eg ister RX Register Select Logic A 0 -A 2 Inter Connect Bus Lines -A S Control signals C S 0 ,C S 1 -C S 2 & VCC -D D IS -R T S VCC -C T S Interrupt Control Logic -D T R Modem Control Logic IN T -T X R D Y -R X R D Y VCC -D S R -O P 1 C lo ck VCC -R I & B a u d R a te -O P 2 G en erato r -C D -BAUDOUT XTAL1 XTAL2 RCLK Rev. 4.30 12
- 13. ST16C550 REGISTER FUNCTIONAL DESCRIPTIONS The following table delineates the assigned bit functions for the twelve ST16C550 internal registers. The assigned bit functions are more fully defined in the following paragraphs. Table 4, ST16C550 INTERNAL REGISTERS A2 A1 A0 Register BIT-7 BIT-6 BIT-5 BIT-4 BIT-3 BIT-2 BIT-1 BIT-0 [Default] Note *2 General Register Set 0 0 0 RHR [XX] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 0 THR [XX] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 1 IER [00] 0 0 0 0 modem receive transmit receive status line holding holding interrupt status register register interrupt 0 1 0 FCR [00] RCVR RCVR 0 0 DMA XMIT RCVR FIFO trigger trigger mode FIFO FIFO enable (MSB) (LSB) select reset reset 0 1 0 ISR [01] FIFO’s FIFO’s 0 0 INT INT INT INT enabled enabled priority priority priority status bit-2 bit-1 bit-0 0 1 1 LCR [00] divisor set set even parity stop word word latch break parity parity enable bits length length enable bit-1 bit-0 1 0 0 MCR [00] 0 0 0 loopback -OP2 -OP1 -RTS -DTR enable 1 0 1 LSR [60] FIFO trans. trans. break framing parity overrun receive data empty holding interrupt error error error data error empty ready 1 1 0 MSR [X0] CD RI DSR CTS delta delta delta delta -CD -RI -DSR -CTS 1 1 1 SPR [FF] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 Baud Rate Generator Divisor Registers. Accessible when LCR bit-7 is set to logic 1. Note 1* 0 0 0 DLL [XX] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 1 DLM [XX] bit-15 bit-14 bit-13 bit-12 bit-11 bit-10 bit-9 bit-8 Note *1: The BRG registers are accessible only when LCR bit-7 is set to a logic 1. Note *2: The value represents the register’s initialized HEX value. An “X” signifies a 4-bit un-initialized nibble. Rev. 4.30 13
- 14. ST16C550 Transmit and Receive Holding Register B) FIFO status will also be reflected in the user acces- sible ISR register when the FIFO trigger level is reached. The serial transmitter section consists of an 8-bit Both the ISR register status bit and the interrupt will be Transmit Hold Register (THR) and Transmit Shift cleared when the FIFO drops below the trigger level. Register (TSR). The status of the THR is provided in the Line Status Register (LSR). Writing to the THR C) The data ready bit (LSR BIT-0) is set as soon as a transfers the contents of the data bus (D7-D0) to the character is transferred from the shift register to the THR, providing that the THR or TSR is empty. The receive FIFO. It is reset when the FIFO is empty. THR empty flag in the LSR register will be set to a logic 1 when the transmitter is empty or when data is IER Vs Receive/Transmit FIFO Polled Mode Op- transferred to the TSR. Note that a write operation can eration be performed when the transmit holding register empty flag is set (logic 0 = at least one byte in FIFO / When FCR BIT-0 equals a logic 1; resetting IER bits THR, logic 1= FIFO/THR empty). 0-3 enables the ST16C550 in the FIFO polled mode of operation. Since the receiver and transmitter have The serial receive section also contains an 8-bit separate bits in the LSR either or both can be used in Receive Holding Register, RHR. Receive data is the polled mode by selecting respective transmit or removed from the ST16C550 and receive FIFO by receive control bit(s). reading the RHR register. The receive section pro- vides a mechanism to prevent false starts. On the A) LSR BIT-0 will be a logic 1 as long as there is one falling edge of a start or false start bit, an internal byte in the receive FIFO. receiver counter starts counting clocks at 16x clock rate. After 7 1/2 clocks the start bit time should be B) LSR BIT 1-4 will indicate if an overrun error shifted to the center of the start bit. At this time the start occurred. bit is sampled and if it is still a logic 0 it is validated. Evaluating the start bit in this manner prevents the C) LSR BIT-5 will indicate when the transmit FIFO is receiver from assembling a false character. Receiver empty. status codes will be posted in the LSR. D) LSR BIT-6 will indicate when both the transmit Interrupt Enable Register (IER) FIFO and transmit shift register are empty. The Interrupt Enable Register (IER) masks the inter- E) LSR BIT-7 will indicate any FIFO data errors. rupts from receiver ready, transmitter empty, line status and modem status registers. These interrupts would normally be seen on the ST16C550 INT output IER BIT-0: pin. Logic 0 = Disable the receiver ready interrupt. (normal default condition) IER Vs Receive FIFO Interrupt Mode Operation Logic 1 = Enable the receiver ready interrupt. When the receive FIFO (FCR BIT-0 = a logic 1) and IER BIT-1: receive interrupts (IER BIT-0 = logic 1) are enabled, Logic 0 = Disable the transmitter empty interrupt. the receive interrupts and register status will reflect (normal default condition) the following: Logic 1 = Enable the transmitter empty interrupt. A) The receive data available interrupts are issued to IER BIT-2: the external CPU when the FIFO has reached the Logic 0 = Disable the receiver line status interrupt. programmed trigger level. It will be cleared when the (normal default condition) FIFO drops below the programmed trigger level. Logic 1 = Enable the receiver line status interrupt. Rev. 4.30 14
- 15. ST16C550 IER BIT-3: logic 0) and when there are no characters in the transmit Logic 0 = Disable the modem status register interrupt. FIFO or transmit holding register, the -TXRDY pin will be (normal default condition) a logic 0. Once active the -TXRDY pin will go to a logic Logic 1 = Enable the modem status register interrupt. 1 after the first character is loaded into the transmit holding register. IER BIT 4-7: Not used and set to “0”. Receive operation in mode “0”: FIFO Control Register (FCR) When the ST16C550 is in mode “0” (FCR bit-0 = logic 0) or in the FIFO mode (FCR bit-0 = logic 1, FCR bit- This register is used to enable the FIFO’s, clear the 3 = logic 0) and there is at least one character in the FIFO’s, set the transmit/receive FIFO trigger levels, receive FIFO, the -RXRDY pin will be a logic 0. Once and select the DMA mode. The DMA, and FIFO active the -RXRDY pin will go to a logic 1 when there modes are defined as follows: are no more characters in the receiver. DMA MODE: Transmit operation in mode “1”: See description and DMA tables on page 11. When the ST16C550 is in FIFO mode ( FCR bit-0 = logic 1, FCR bit-3 = logic 1 ), the -TXRDY pin will be FCR BIT-0: a logic 1 when the transmit FIFO is completely full. It Logic 0 = Disable the transmit and receive FIFO. will be a logic 0 if one or more FIFO locations are (normal default condition) empty. Logic 1 = Enable the transmit and receive FIFO. This bit must be a “1” when other FCR bits are written to or Receive operation in mode “1”: they will not be programmed. When the ST16C550 is in FIFO mode (FCR bit-0 = logic 1, FCR bit-3 = logic 1) and the trigger level has FCR BIT-1: been reached, or a Receive Time Out has occurred, Logic 0 = No FIFO receive reset. (normal default the -RXRDY pin will go to a logic 0. Once activated, it condition) will go to a logic 1 after there are no more characters Logic 1 = Clears the contents of the receive FIFO and in the FIFO. resets the FIFO counter logic (the receive shift regis- ter is not cleared or altered). This bit will return to a logic 0 after clearing the FIFO. FCR BIT 4-5: Not used. FCR BIT-2: Logic 0 = No FIFO transmit reset. (normal default FCR BIT 6-7: These bits are used to set the trigger level condition) for the receive FIFO interrupt. Logic 1 = Clears the contents of the transmit FIFO and resets the FIFO counter logic (the transmit shift regis- An interrupt is generated when the number of characters ter is not cleared or altered). This bit will return to a in the FIFO equals the programmed trigger level. How- logic 0 after clearing the FIFO. ever the FIFO will continue to be loaded until it is full. FCR BIT-3: Logic 0 = Set DMA mode “0”. (normal default condi- BIT-7 BIT-6 RX FIFO trigger level tion) Logic 1 = Set DMA mode “1.” 0 0 1 0 1 4 Transmit operation in mode “0”: 1 0 8 When the ST16C550 is in the ST16C450 mode 1 1 14 (FIFO’s disabled, FCR bit-0 = logic 0) or in the FIFO mode (FIFO’s enabled, FCR bit-0 = logic 1, FCR bit-3 = Rev. 4.30 15
- 16. ST16C550 Interrupt Status Register (ISR) The ST16C550 provides four levels of prioritized inter- rupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the ISR will provide the user with the highest pending interrupt level to be serviced. No other interrupts are acknowl- edged until the pending interrupt is serviced. Whenever the interrupt status register is read, the interrupt status is cleared. However it should be noted that only the current pending interrupt is cleared by the read. A lower level interrupt may be seen after rereading the interrupt status bits. The Interrupt Source Table 5 (below) shows the data values (bit 0-3) for the four prioritized interrupt levels and the interrupt sources associated with each of these interrupt levels: Table 5, INTERRUPT SOURCE TABLE Priority [ISR] Level Bit-3 Bit-2 Bit-1 Bit-0 Source of the interrupt X 0 0 0 1 No interrupt pending 1 0 1 1 0 LSR (Receiver Line Status Register) 2 0 1 0 0 RXRDY (Received Data Ready) 2 1 1 0 0 RXRDY (Receive Data time out) 3 0 0 1 0 TXRDY ( Transmitter Holding Register Empty) 4 0 0 0 0 MSR (Modem Status Register) Rev. 4.30 16
- 17. ST16C550 ISR BIT-0: Logic 0 = An interrupt is pending and the ISR contents BIT-2 Word length Stop bit may be used as a pointer to the appropriate interrupt length service routine. (Bit time(s)) Logic 1 = No interrupt pending. (normal default condi- tion) 0 5,6,7,8 1 1 5 1-1/2 ISR BIT 1-3: (logic 0 or cleared is the default condition) 1 6,7,8 2 These bits indicate the source for a pending interrupt at interrupt priority levels 1, 2, and 3 (See Interrupt Source Table). LCR BIT-3: Parity or no parity can be selected via this bit. ISR BIT 4-5: Not used and set to “0”. Logic 0 = No parity (normal default condition) Logic 1 = A parity bit is generated during the transmis- ISR BIT 6-7: (logic 0 or cleared is the default condition) sion, receiver checks the data and parity for transmis- These bits are set to a logic 0 when the FIFO is not being sion errors. used. They are set to a logic 1 when the FIFO’s are enabled LCR BIT-4: If the parity bit is enabled with LCR bit-3 set to a logic Line Control Register (LCR) 1, LCR BIT-4 selects the even or odd parity format. Logic 0 = ODD Parity is generated by forcing an odd The Line Control Register is used to specify the number of logic 1’s in the transmitted data. The asynchronous data communication format. The word receiver must be programmed to check the same length, the number of stop bits, and the parity are format. (normal default condition) selected by writing the appropriate bits in this register. Logic 1 = EVEN Parity is generated by forcing an even the number of logic 1’s in the transmitted. The receiver LCR BIT 0-1: (logic 0 or cleared is the default condi- must be programmed to check the same format. tion) These two bits specify the word length to be transmit- LCR BIT-5: ted or received. If the parity bit is enabled, LCR BIT-5 selects the forced parity format. LCR BIT-5 = logic 0, parity is not forced (normal BIT-1 BIT-0 Word length default condition) LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit 0 0 5 is forced to a logical 1 for the transmit and receive 0 1 6 data. 1 0 7 LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit 1 1 8 is forced to a logical 0 for the transmit and receive data. LCR BIT-2: (logic 0 or cleared is the default condition) The length of stop bit is specified by this bit in LCR LCR LCR Parity selection conjunction with the programmed word length. Bit-5 Bit-4 Bit-3 X X 0 No parity 0 0 1 Odd parity 0 1 1 Even parity 1 0 1 Force parity “1” 1 1 1 Forced “0” Rev. 4.30 17
- 18. ST16C550 LCR BIT-6: MCR BIT 5-7: Not used and set to “0”. When enabled the Break control bit causes a break condition to be transmitted (the TX output is forced to a Line Status Register (LSR) logic 0 state). This condition exists until disabled by setting LCR bit-6 to a logic 0. This register provides the status of data transfers Logic 0 = No TX break condition. (normal default between. the ST16C550 and the CPU. condition) Logic 1 = Forces the transmitter output (TX) to a logic LSR BIT-0: 0 for alerting the remote receiver to a line break Logic 0 = No data in receive holding register or FIFO. condition. (normal default condition) Logic 1 = Data has been received and is saved in the LCR BIT-7: receive holding register or FIFO. The internal baud rate counter latch and Enhance Feature mode enable. LSR BIT-1: Logic 0 = Divisor latch disabled. (normal default condi- Logic 0 = No overrun error. (normal default condition) tion) Logic 1 = Overrun error. A data overrun error occurred Logic 1 = Divisor latch and enhanced feature register in the receive shift register. This happens when addi- enabled. tional data arrives while the FIFO is full. In this case the previous data in the shift register is overwritten. Modem Control Register (MCR) Note that under this condition the data byte in the receive shift register is not transfer into the FIFO, This register controls the interface with the modem or therefore the data in the FIFO is not corrupted by the a peripheral device. error. MCR BIT-0: LSR BIT-2: Logic 0 = Force -DTR output to a logic 1. (normal Logic 0 = No parity error (normal default condition) default condition) Logic 1 = Parity error. The receive character does not Logic 1 = Force -DTR output to a logic 0. have correct parity information and is suspect. In the FIFO mode, this error is associated with the character MCR BIT-1: at the top of the FIFO. Logic 0 = Force -RTS output to a logic 1. (normal default condition) LSR BIT-3: Logic 1 = Force -RTS output to a logic 0. Logic 0 = No framing error (normal default condition). Logic 1 = Framing error. The receive character did not MCR BIT-2: have a valid stop bit(s). In the FIFO mode this error is Logic 0 = Set -OP1 output to a logic 1. (normal default associated with the character at the top of the FIFO. condition) Logic 1 = Set -OP1 output to a logic 0. LSR BIT-4: Logic 0 = No break condition (normal default condi- MCR BIT-3: tion) Logic 0 = Set -OP2 output to a logic 1. (normal default Logic 1 = The receiver received a break signal (RX condition) was a logic 0 for one character frame time). In the Logic 1 = Set -OP2 output to a logic 0. FIFO mode, only one break character is loaded into the FIFO. MCR BIT-4: Logic 0 = Disable loop-back mode. (normal default LSR BIT-5: condition) This bit is the Transmit Holding Register Empty indi- Logic 1 = Enable local loop-back mode (diagnostics). cator. This bit indicates that the UART is ready to accept a new character for transmission. In addition, Rev. 4.30 18
- 19. ST16C550 this bit causes the UART to issue an interrupt to CPU when the THR interrupt enable is set. The THR bit is set MSR BIT-2: to a logic 1 when a character is transferred from the Logic 0 = No -RI Change (normal default condition) transmit holding register into the transmitter shift regis- Logic 1 = The -RI input to the ST16C550 has changed ter. The bit is reset to logic 0 concurrently with the from a logic 0 to a logic 1. A modem Status Interrupt loading of the transmitter holding register by the CPU. will be generated. In the FIFO mode this bit is set when the transmit FIFO is empty; it is cleared when at least 1 byte is written to MSR BIT-3: the transmit FIFO. Logic 0 = No -CD Change (normal default condition) Logic 1 = Indicates that the -CD input to the has LSR BIT-6: changed state since the last time it was read. A This bit is the Transmit Empty indicator. This bit is set modem Status Interrupt will be generated. to a logic 1 whenever the transmit holding register and the transmit shift register are both empty. It is reset to MSR BIT-4: logic 0 whenever either the THR or TSR contains a CTS (active high, logical 1). Normally this bit is the data character. In the FIFO mode this bit is set to one compliment of the -CTS input. In the loop-back mode, whenever the transmit FIFO and transmit shift register this bit is equivalent to the RTS bit in the MCR register. are both empty. MSR BIT-5: LSR BIT-7: DSR (active high, logical 1). Normally this bit is the Logic 0 = No Error (normal default condition) compliment of the -DSR input. In the loop-back mode, Logic 1 = At least one parity error, framing error or this bit is equivalent to the DTR bit in the MCR register. break indication is in the current FIFO data. This bit is cleared when there are no remaining LSR errors in the MSR BIT-6: RX FIFO. RI (active high, logical 1). Normally this bit is the compliment of the -RI input. In the loop-back mode Modem Status Register (MSR) this bit is equivalent to the OP1 bit in the MCR register. This register provides the current state of the control MSR BIT-7: interface signals from the modem, or other peripheral CD (active high, logical 1). Normally this bit is the device that the ST16C550 is connected to. Four bits compliment of the -CD input. In the loop-back mode of this register are used to indicate the changed this bit is equivalent to the OP2 bit in the MCR register. information. These bits are set to a logic 1 whenever a control input from the modem changes state. These Scratchpad Register (SPR) bits are set to a logic 0 whenever the CPU reads this register. The ST16C550 provides a temporary data register to store 8 bits of user information. MSR BIT-0: Logic 0 = No -CTS Change (normal default condition) Logic 1 = The -CTS input to the ST16C550 has changed state since the last time it was read. A modem Status Interrupt will be generated. MSR BIT-1: Logic 0 = No -DSR Change (normal default condition) Logic 1 = The -DSR input to the ST16C550 has changed state since the last time it was read. A modem Status Interrupt will be generated. Rev. 4.30 19
- 20. ST16C550 ST16C550 EXTERNAL RESET CONDITIONS REGISTERS RESET STATE IER IER BITS 0-7 = logic 0 ISR ISR BIT-0=1, ISR BITS 1-7 = logic 0 LCR, MCR BITS 0-7 = logic 0 LSR LSR BITS 0-4 = logic 0, LSR BITS 5-6 = logic 1 LSR, BIT 7 = logic 0 MSR MSR BITS 0-3 = logic 0, MSR BITS 4-7 = logic levels of the input signals FCR BITS 0-7 = logic 0 SIGNALS RESET STATE TX Logic 1 -OP1 Logic 1 -OP2 Logic 1 -RTS Logic 1 -DTR Logic 1 -RXRDY Logic 1 -TXRDY Logic 0 INT Logic 0 Rev. 4.30 20
- 21. ST16C550 AC ELECTRICAL CHARACTERISTICS TA=0° - 70°C (-40° - +85°C for Industrial grade packages), Vcc=3.3 - 5.0 V ± 10% unless otherwise specified. Symbol Parameter Limits Limits Units Conditions 3.3 5.0 Min Max Min Max T1w,T2w Clock pulse duration 17 17 ns T3w Oscillator/Clock frequency 16 24 MHz T4w Address strobe width 35 25 ns T5s Address setup time 5 0 ns T5h Address hold time 5 5 ns T6s Address setup time 5 0 ns T6s' Address setup time 10 5 ns see Note 1 T6h Chip select hold time 0 0 ns T7d -IOR delay from chip select 10 10 ns T7w -IOR strobe width 35 25 ns T7h Chip select hold time from -IOR 0 0 ns T7h' Address hold time 5 5 ns see Note 1 T8d -IOR delay from address 10 10 ns T9d Read cycle delay 40 30 ns T11d -IOR to -DDIS delay 15 10 ns 100 pF load T12d Delay from -IOR to data 35 25 ns T12h Data disable time 25 15 ns T13d -IOW delay from chip select 10 10 ns T13w -IOW strobe width 40 25 ns T13h Chip select hold time from -IOW 0 0 ns T14d -IOW delay from address 10 10 ns T15d Write cycle delay 40 30 ns T16s Data setup time 20 15 ns T16h Data hold time 5 5 ns T17d Delay from -IOW to output 50 40 ns 100 pF load T18d Delay to set interrupt from MODEM 40 35 ns 100 pF load input T19d Delay to reset interrupt from -IOR 40 35 ns 100 pF load T20d Delay from stop to set interrupt 1 1 Rclk T21d Delay from -IOR to reset interrupt 45 40 ns 100 pF load T22d Delay from stop to interrupt 45 40 ns T23d Delay from initial INT reset to transmit 8 24 8 24 Rclk start T24d Delay from -IOW to reset interrupt 45 40 ns T25d Delay from stop to set -RxRdy 1 1 Rclk T26d Delay from -IOR to reset -RxRdy 45 40 ns T27d Delay from -IOW to set -TxRdy 45 40 ns T28d Delay from start to reset -TxRdy 8 8 Rclk TR Reset pulse width 40 40 ns N Baud rate devisor 1 216-1 1 216-1 Rclk Note 1: Applicable only when -AS is tied low. Rev. 4.30 21
- 22. ST16C550 ABSOLUTE MAXIMUM RATINGS Supply range 7 Volts Voltage at any pin GND - 0.3 V to VCC +0.3 V Operating temperature -40° C to +85° C Storage temperature -65° C to 150° C Package dissipation 500 mW DC ELECTRICAL CHARACTERISTICS TA=0° - 70°C (-40° - +85°C for Industrial grade packages), Vcc=3.3 - 5.0 V ± 10% unless otherwise specified. Symbol Parameter Limits Limits Units Conditions 3.3 5.0 Min Max Min Max VILCK Clock input low level -0.3 0.6 -0.5 0.6 V VIHCK Clock input high level 2.4 VCC 3.0 VCC V VIL Input low level -0.3 0.8 -0.5 0.8 V VIH Input high level 2.0 2.2 VCC V VOL Output low level on all outputs 0.4 V IOL= 5 mA VOL Output low level on all outputs 0.4 V IOL= 4 mA VOH Output high level 2.4 V IOH= -5 mA VOH Output high level 2.0 V IOH= -1 mA IIL Input leakage ±10 ±10 µA ICL Clock leakage ±10 ±10 µA I CC Avg power supply current 1.3 3 mA CP Input capacitance 5 5 pF Rev. 4.30 22
- 23. ST16C550 T2w T1w EXTERNAL CLOCK T3w -BAUDOUT 1/2 -BAUDOUT 1/3 -BAUDOUT 1/3> -BAUDOUT X450-CK-1 Clock timing Rev. 4.30 23
- 24. ST16C550 T4w -A S T5s T5h V a lid A 0 -A 2 A d d re s s T6h T6s -C S 2 V a lid C S 1 -C S 0 T7d T7w T7h T8d T9d -IO R A c tiv e IO R T11d T11d -D D IS A c tiv e T12d T12h D 0 -D 7 D a ta X 5 5 0 -R D -1 General Read Timing when using -AS signal T4w -AS T5s T5h Valid A0-A2 Address T6h T6s -CS2 Valid CS1-CS0 T13d T13w T13h T14d T15d -IOW Active IOW T16s T16h D0-D7 Data X550-W D-1 General Write Timing when using -AS signal. Rev. 4.30 24
- 25. ST16C550 V alid V alid A 0-A 2 A ddress A ddress T 7h' T 6s' T 7h' T 6s' T 7w -C S A ctive A ctive T 7w T 9d -IO R A ctive T 12d T 12d T 12h T 12h D 0-D 7 D ata General Read Timing when -AS is tied to GND V a lid V a lid A 0 -A 2 A d d re ss A d d re ss T7h' T 6 s' T7h' T 6 s' -C S A ctive A ctive T13w T15d T13w -IO W A ctive T16s T16s T16h T16h D 0 -D 7 D a ta General Write Timing when -AS is tied to GND Rev. 4.30 25
- 26. ST16C550 -IOW Active IOW T17d -RTS Change of state Change of state -DTR -CD -CTS Change of state Change of state -DSR T18d T18d INT Active Active Active T19d -IOR Active Active Active IOR T18d -RI Change of state X450-MD-1 Modem input/output timing Rev. 4.30 26
- 27. ST16C550 START STOP BIT BIT DATA BITS (5-8) RX D0 D1 D2 D3 D4 D5 D6 D7 PARITY NEXT 5 DATA BITS BIT DATA START 6 DATA BITS BIT 7 DATA BITS T20d INT Active T21d -IOR IOR 16 BAUD RATE CLOCK X450-RX-1 Receive timing Rev. 4.30 27
- 28. ST16C550 START STOP BIT BIT DATA BITS (5-8) RX D0 D1 D2 D3 D4 D5 D6 D7 PARITY NEXT BIT DATA START BIT T25d Active -RXRDY Data Ready T26d -IOR Active IOR X550-RX-2 Receive ready timing in non FIFO mode Rev. 4.30 28
- 29. ST16C550 START STOP BIT BIT DATA BITS (5-8) RX D0 D1 D2 D3 D4 D5 D6 D7 PARITY BIT First byte that reaches the trigger level T25d Active -RXRDY Data Ready T26d -IOR Active IOR X550-RX-3 Receive ready timing in FIFO mode Rev. 4.30 29
- 30. ST16C550 S T AR T STOP B IT B IT D A T A B IT S (5-8) TX D0 D1 D2 D3 D4 D5 D6 D7 P AR IT Y 5 D AT A BIT S B IT 6 D AT A BIT S 7 D AT A BIT S T 22d IN T A ctive T X R eady T 23d T 24d IO W / -IO W A ctive A ctiv e 16 BA U D R A T E C LO C K Transmit timing Rev. 4.30 30
- 31. ST16C550 START STOP BIT BIT DATA BITS (5-8) TX D0 D1 D2 D3 D4 D5 D6 D7 PARITY NEXT BIT DATA START BIT -IOW Active IOW T28d BYTE #1 T27d -TXRDY Active Transmitter Transmitter ready not ready X550-TX-2 Transmit ready timing in non FIFO mode Rev. 4.30 31
- 32. ST16C550 START BIT DATA BITS (5-8) STOP BIT TX D0 D1 D2 D3 D4 D5 D6 D7 5 DATA BITS PARITY BIT 6 DATA BITS 7 DATA BITS -IOW Active IOW T28d D0-D7 BYTE #16 T27d -TXRDY FIFO Full X550-TX-3 Transmit ready timing in FIFO mode Rev. 4.30 32
- 33. ST16C550 PACKAGE OUTLINE DRAWING 44LEAD PLASTIC LEADED CHIP CARRIER (PLCC) D C Seating Plane D1 45° x H2 45° x H1 A2 2 1 44 B1 D D1 B D3 D2 e R D3 A1 A Note: The control dimension is the inch column INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.165 0.180 4.19 4.57 A1 0.090 0.120 2.29 3.05 A2 0.020 ----- 0.51 ------ B 0.013 0.021 0.33 0.53 B1 0.026 0.032 0.66 0.81 C 0.008 0.013 0.19 0.32 D 0.685 0.695 17.40 17.65 D1 0.650 0.656 16.51 16.66 D2 0.590 0.630 14.99 16.00 D3 0.500 typ 12.70 typ e 0.50 BSC 1.27BSC H1 0.042 0.056 1.07 1.42 H2 0.042 0.048 1.07 1.22 R 0.025 0.045 0.64 1.14 Rev. 4.30 33
- 34. ST16C550 PACKAGE OUTLINE DRAWING 48 LEAD THIN QUAD FLAT PACK (TQFP) D D1 36 25 37 24 D1 D 48 13 1 1 2 B A2 e C A Seating α Plane A1 L Note: The control dimension is the millimeter column INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.039 0.047 1.00 1.20 A1 0.002 0.006 0.05 0.15 A2 0.037 0.041 0.95 1.05 B 0.007 0.011 0.17 0.27 C 0.004 0.008 0.09 0.20 D 0.346 0.362 8.80 9.20 D1 0.272 0.280 6.90 7.10 e 0.20 BSC 0.50BSC L 0.018 0.030 0.45 0.75 α 0° 7° 0° 7° Rev. 4.30 34
- 35. ST16C550 EXPLANATION OF DATA SHEET REVISIONS: FROM TO CHANGES DATE 4.20 4.30 Added revision history. Added Device Status to front page. Sept 2003 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2003 EXAR Corporation Datasheet September 2003 Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com Reproduction, in part or whole, without prior written consent of EXAR Corporation is prohibited. Rev. 4.30 35
- 36. This datasheet has been download from: www.datasheetcatalog.com Datasheets for electronics components.