Superscalar Execution
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This document discusses the representation of superscalar execution for three code examples. It shows the pipeline stages for instruction fetch, instruction decode, execute, and write back. For each example, it illustrates how multiple instructions can be executed concurrently by different pipeline stages to improve performance through superscalar execution.
Superscalar Execution
- 1. Juan Carlos Sarango UTPL ECC 2008
- 2. Representation of Superscalar Execution of this: I Load R1, @1000 Load R2, @1008 Add R1, @1004 Add R2, @100C Add R1, R2 Store R1, @2000 II Load R1, @1000 Add R1, @1004 Add R1, @1008 Add R1, @100C Store R1, @2000 III Load R1, @1000 Add R1, @1004 Load R2, @1008 Add R2, @100C Add R1, R2 Store R1, @2000
- 3. IF ID OF IF ID OF E IF ID OF IF ID OF E IF ID NA E IF ID NA WB store R1, @2000 Load R2, @1008 add R1, @1004 add R2, @100C add R1, R2 Load R1, @1000 0 2 4 6 8 10
- 4. store R1, @2000 add R1, @1004 Load R1, @1000 add R1, @1008 add R1, @100C IF ID OF E IF ID OF IF ID NA WB 0 2 4 6 8 10 E IF ID OF E IF ID OF
- 5. IF ID OF E IF ID OF IF ID NA WB store R1, @2000 add R1, @1004 Load R1, @1000 0 2 4 6 8 10 E IF ID OF add R2, @100C OF IF ID NA Load R2, @1008 IF ID NA E add R1, R2
- 6. Grama A.,Gupta A., Karypis G., Kumar V. , Introduction to Parallel Computing , Second Edition,Pearson Education,2003