![Total Mark:
Extension certification:
This assignment has been given an extension and is now due on
Signature of Convener:
SWE20004 Assignment 2
5
Sample assignment report:
COS10004 Computer Systems Assignment 1
By: redacted a student )
Student number: [SIMS ID]
Submitted [date]
Due: [date]](https://image.slidesharecdn.com/swinburneuniversityoftechnologyfacultyofsciencee-221026055255-8449ed3c/85/Swinburne-University-of-Technology-Faculty-of-Science-E-docx-10-320.jpg)
![Sample Only
COS10004 Assignment 1
6
Description:
[Glcr n dhbgr sebz gur qbphzrag be gur fhzznel bs na
vagrerfgvat cbvag. Lbh pna cbfvgvba gur grkg obk naljurer va
gur
qbphzrag. Hfr gur Qenjvat Gbbyf gno gb punatr gur sbeznggvat
bs gur chyy dhbgr grkg obk.]
Gur frpbaq uvtuyvtugrq va oyhr fubjf gur crevbq bs
inevnovyvgl. Vs gur frafbe vachg vf npgvingrq jvguva gur
obhaqnevrf bs guvf ertvba, gur nynez jvyy npgvingr ng gur gvzr
fubja. Juvyfg fngvfslvat gur “zber guna sbhe frpbaqf”
erdhverzrag, guvf erfhygf va gur sbyybjvat gvzr inevngvba: 4 <
g < 5 frpbaqf.
Design outline:
My design uses 5 ½ bit adders, 23 registers, half a right-shift
register, and a binary counter, blah blah, blah. If you try to
construct this circuit, it will never work because this doesn't
make sense. Try reading the notes, doing the labs and](https://image.slidesharecdn.com/swinburneuniversityoftechnologyfacultyofsciencee-221026055255-8449ed3c/85/Swinburne-University-of-Technology-Faculty-of-Science-E-docx-11-320.jpg)
![experimenting with CEDAR. Blah blah blah.
Assumptions:
Bapr gur nynez syvc-sybc vf npgvingrq, vgf bhgchg srrqf onpx
vagb vgf vachg (gubhtu na BE tngr) fb nf gb znvagnva
vgf fgnghf. Gur erfrg vachg zhfg or npgvingrq va beqre sbe gur
nynez gb fgbc, juvpu unccraf ng gur evfvat rqtr bs gur
arkg pybpx chyfr. Orybj vf n gehgu gnoyr bs ubj gur nynez
erfrg ybtvp jbexf:
Vs gur erfrg vachg vf npgvir, gur ybj fvtany tbvat gb gur NAQ
tngr nggnpurq gb gur vachg bs rnpu syvc-sybc erfhygf va
gurz vtabevat gur vachg, naq pyrnevat gurzfryirf.
Unresolved Problems:
My circuit cannot fly no matter how hard I try. Maybe
increasing the clock frequency into the MHz (micro seconds)
range will help, but CEDAR does not support this. [Glcr n
dhbgr sebz gur qbphzrag be gur fhzznel bs na vagrerfgvat
cbvag. Lbh pna cbfvgvba gur grkg obk naljurer va gur qbphzrag.
Hfr gur Qenjvat Gbbyf gno gb punatr gur sbeznggvat
bs gur chyy dhbgr grkg obk.]
Vs gur erfrg vachg vf npgvir, gur ybj fvtany tbvat gb gur NAQ
tngr nggnpurq gb gur vachg bs rnpu syvc-sybc erfhygf va](https://image.slidesharecdn.com/swinburneuniversityoftechnologyfacultyofsciencee-221026055255-8449ed3c/85/Swinburne-University-of-Technology-Faculty-of-Science-E-docx-12-320.jpg)
Swinburne University of Technology Faculty of Science, E.docx
- 1. Swinburne University of Technology Faculty of Science, Engineering and Technology Computer Systems COS10004 Assignment 1 – MP3 Player interface This assignment is worth 15% of the unit assessment. Due Date: Wednesday 23 rd September 2015 at 10:30 am 1. Submit a soft copy through https://esp.ict.swin.edu.au -with cookies enabled and *.swin.edu.au added to your trusted internet zone 2. Submit a report by hand at the 10:30 Thursday lecture. Both components must be submitted on time. Introduction: This assignment requires a knowledge of logic gates, flip-flops, counters, controlled gates and input / output. Optional tasks require a knowledge of registers and shift-registers.
- 2. The minimum assignment requirements: Develop and submit an original logic circuit for the user interface of a 5-button MP3 player. The interface must display the volume as an 8-LED bar graph, the track number and Play/Pause indicators (one LED for each). The MP3 player interface must have the following controls and displays: 1. A PLAY/PAUSE button. 2. VOL+ and VOL- buttons 3. <- (prev) and -> (next) buttons 4. An 8-LED bar graph indicating 8 volume settings 5. A 2-digit decimal display -two 7-segment displays (available in the input/output palette in CEDAR) to indicate the track number. 6. One LED which indicates PLAY mode (on) and PAUSE mode (flashing 1Hz) OR Two LEDs - one for each mode. There is no requirement to implement the MP3 playing function, the A-D convertor, audio amplifier or other functions. The MP3 player interface must have the following functionality (minimum requirements): 1. Two states: PLAY and PAUSE. 2. In the PAUSED state, a single press on the PLAY/PAUSE button should change the state to PLAY, and the PLAY LED should be on. If a
- 3. separate PAUSE LED is present it should be off. 3. In both PLAY and PAUSE states the VOL+ and VOL- buttons should increase or decrease the height of the Volume bar graph (8 LEDs). The bar graph must not COS10004 Assignment 1 2 wrap around if the VOL+ button is pressed while 8 LEDS are on or if the VOL- button is pressed and no LEDs are on. 4. In both PLAY and PAUSE states the -> and <- buttons should increase or decrease the track number display. The value must wrap around when it teaches 99 or 00. A screen-shot of your final circuit must be included in a report which you will submit both electronically (through ESP) and on paper. Details of the report are shown below. Parts 1-4 constitute 40% of this assignment and are compulsory. For additional credit:
- 4. 5. Three states: Off, On (PAUSED), ON(PLAY). When in the OFF state all LEDs must be off and all buttons must not respond, except for the PLAY/PAUSE button which should only respond when held down for 5 seconds. 6. When entering the ON state, the player should start in the PAUSED state. The Play LED should be off (if a separate PAUSE LED is present) or flashing. 7. When in the PLAY/PAUSE mode if the PLAY/PAUSE button is held down for 5 seconds, the MP3 player should change to the OFF state, with all LEDs off. The values in the Volume and Track number displays do not have to be stored. Parts 5-7 constitute 30% of this assignment and must be attempted. For a distinction grade or better: 8. When entering the OFF state the values of the volume and Track number displays must be stored in appropriate registers. 9. When entering the PLAY/PAUSE states (from the OFF state) the values in the Volume and Track Number resisters must be loaded into the appropriate displays and counters. 10. Implement a fast forward (FF) state to be entered when the user holds down the ->
- 5. button for 5 seconds. This will cause the PLAY LED to flash quickly (~4Hz). To exit this state hold down the <- button for 5 seconds to resume PLAY mode. Parts 1-4 must be completed successfully to qualify for a pass in COS10004. Parts 5-7 constitute 30% of this assignment, and must be attempted. Parts 8-10 are optional. Marking details: • Each requirement is worth 10% of this assignment or 1.5% of this unit. • In order to get 100% (15% of the unit result) you must complete all 10 requirements. • To "pass" the assignment you must complete requirements 1-4 and attempt parts 5-7 (50%). • To qualify for a pass in the final unit result, you must get at least 35% of this assignment (requirements 1-4). 35-49% is a fail for the assignment, but will not disqualify you from passing the unit. • If you do not complete requirements 1-4 (at least 35%) you will receive a final mark no higher than 44% for this unit.
- 6. • Circuits will be examined using CEDAR. While you may develop in other simulators, your final submission must be a CEDAR file. SWE20004 Assignment 2 3 Hints: • Start with a toggle circuit to switch between PLAY and PAUSE states. Include indicator LEDs and a low-frequency timer for the PAUSE indication (optional). • Construct a decimal counter connected to VOL+ and VOL= buttons. Add logic circuitry to disable the appropriate button when the limits are reach (to prevent wrap-around). • Next, build a binary counter which counts from 0 to 15 (up and down). Add logic circuitry to wrap around from 9 to 0 (with Carry out). Connect Co to the input of a second 0-9 counter. Connect to two 7-segment displays and test. Make sure that when counting backwards the counter goes from 0 to 99. • Create a 5-state countdown counter (4,3,2,1,0) and a 0 detect gate. Add gates to the PR
- 7. pins of the flip-flops to reset the FFs to 5 (101) when not in use. • Use an OR gate to detect if PLAY or PAUSE states are active and use this to enable or disable other buttons and displays. Do not use it to disable the clock – you need that to keep running. • When the user presses PLAY/PAUSE start the countdown timer. If the user releases the button before the counter gets to zero, change state (from PLAY to PAUSE etc.)(if not OFF) and reset the timer. If the timer reaches 0, change state to OFF (or ON) and reset the timer. • THIS ASSIGNMENT IS HARD – START NOW Report format: An example report is shown below. Include a description of your circuit (in terms of functional units, not individual gates), a screen-shot of the final circuit, and explain any design decisions and assumptions you made. Submission: Submissions must be made through ESP before the due date/time. Each submission should be in the form of a .zip file containing: 1. the actual CEDAR file (.cdl source code). o The name of your .cdl file must be your student number. 2. a report (docx or .rtf or .pdf format) containing: • The cover sheet, including your name, student number, the unit code, name
- 8. and your lab session. • a description of the circuit, • an outline of your design (in terms of functional blocks of gates, devices) • any assumptions you made • any unresolved problems with your design • pasted screen shots of the working circuit o use Alt+PrtScr to copy the screen image, o select and use ENTER to copy the output text. o Note that large scans (bigger than 500kB) should be reduced in size and/or colour depth before pasting into Word. Submissions larger than 3MB will not be accepted. COS10004 Assignment 1 4 Swinburne University Of Technology Faculty of Science, Engineering and Technology ASSIGNMENT AND PROJECT COVER SHEET
- 9. Unit Code: COS10004 Unit Title: Computer Systems Assignment number and title: ___1 Digital Timer__________ Due date: _23 rd September 2015 at 10:30am by ESP and by hand (lecture) Lab/tute group: ___ Tutor: Lecturer:J Hamlyn-Harris Family name: Identity no: Other names: Marker's comments:
- 10. Total Mark: Extension certification: This assignment has been given an extension and is now due on Signature of Convener: SWE20004 Assignment 2 5 Sample assignment report: COS10004 Computer Systems Assignment 1 By: redacted a student ) Student number: [SIMS ID] Submitted [date] Due: [date]
- 11. Sample Only COS10004 Assignment 1 6 Description: [Glcr n dhbgr sebz gur qbphzrag be gur fhzznel bs na vagrerfgvat cbvag. Lbh pna cbfvgvba gur grkg obk naljurer va gur qbphzrag. Hfr gur Qenjvat Gbbyf gno gb punatr gur sbeznggvat bs gur chyy dhbgr grkg obk.] Gur frpbaq uvtuyvtugrq va oyhr fubjf gur crevbq bs inevnovyvgl. Vs gur frafbe vachg vf npgvingrq jvguva gur obhaqnevrf bs guvf ertvba, gur nynez jvyy npgvingr ng gur gvzr fubja. Juvyfg fngvfslvat gur “zber guna sbhe frpbaqf” erdhverzrag, guvf erfhygf va gur sbyybjvat gvzr inevngvba: 4 < g < 5 frpbaqf. Design outline: My design uses 5 ½ bit adders, 23 registers, half a right-shift register, and a binary counter, blah blah, blah. If you try to construct this circuit, it will never work because this doesn't make sense. Try reading the notes, doing the labs and
- 12. experimenting with CEDAR. Blah blah blah. Assumptions: Bapr gur nynez syvc-sybc vf npgvingrq, vgf bhgchg srrqf onpx vagb vgf vachg (gubhtu na BE tngr) fb nf gb znvagnva vgf fgnghf. Gur erfrg vachg zhfg or npgvingrq va beqre sbe gur nynez gb fgbc, juvpu unccraf ng gur evfvat rqtr bs gur arkg pybpx chyfr. Orybj vf n gehgu gnoyr bs ubj gur nynez erfrg ybtvp jbexf: Vs gur erfrg vachg vf npgvir, gur ybj fvtany tbvat gb gur NAQ tngr nggnpurq gb gur vachg bs rnpu syvc-sybc erfhygf va gurz vtabevat gur vachg, naq pyrnevat gurzfryirf. Unresolved Problems: My circuit cannot fly no matter how hard I try. Maybe increasing the clock frequency into the MHz (micro seconds) range will help, but CEDAR does not support this. [Glcr n dhbgr sebz gur qbphzrag be gur fhzznel bs na vagrerfgvat cbvag. Lbh pna cbfvgvba gur grkg obk naljurer va gur qbphzrag. Hfr gur Qenjvat Gbbyf gno gb punatr gur sbeznggvat bs gur chyy dhbgr grkg obk.] Vs gur erfrg vachg vf npgvir, gur ybj fvtany tbvat gb gur NAQ tngr nggnpurq gb gur vachg bs rnpu syvc-sybc erfhygf va
- 13. gurz vtabevat gur vachg, naq pyrnevat gurzfryirf. Conclusion: Do not tell me how much you loved doing this assignment. Or how much you have learned. In fact, you don't need a conclusion at all. Gur frpbaq uvtuyvtugrq va oyhr fubjf gur crevbq bs inevnovyvgl. Vs gur frafbe vachg vf npgvingrq jvguva gur obhaqnevrf bs guvf ertvba, gur nynez jvyy npgvingr ng gur gvzr fubja. Juvyfg fngvfslvat gur “zber guna sbhe frpbaqf” erdhverzrag, guvf erfhygf va gur sbyybjvat gvzr inevngvba: 4 < g < 5 frpbaqf. Bapr gur nynez syvc-sybc vf npgvingrq, vgf bhgchg srrqf onpx vagb vgf vachg (gubhtu na BE tngr) fb nf gb znvagnva vgf fgnghf. Gur erfrg vachg zhfg or npgvingrq va beqre sbe gur nynez gb fgbc, juvpu unccraf ng gur evfvat rqtr bs gur arkg pybpx chyfr. Orybj vf n gehgu gnoyr bs ubj gur nynez erfrg ybtvp jbexf: A couple of pages is all you need.