4bit pc report[cse 08-section-b2_group-02]

Bangladesh University of Engineering and Technology
Digital System Design Sessional
CSE 404
Report on Very Simple Computer Design & Implementation
Section: B2 - Group No. : 02
Submitted by :
Md. Abul Hashem
Student Id: 0805092
Sirat Samyoun
Student Id : 0805096
Shibbir Ahmed
Imtiaz Ahmad
Student Id: 0805100
Md. Rashidujjaman Rifat
Date of Submission:
June 22, 2013
Submitted to:
Nashid Shahriar Md. Mustafizur Rahman
Assistant Professor, CSE, BUET Lecturer, CSE, BUET
Shagufta Mehnaz Sarah Masud Preum
Lecturer, CSE, BUET Lecturer, CSE, BUET

Problem Description
A very simple computer system has to be designed and implemented in this assignment. The
Control unit should be micro-programmed. Efficiency of design has to be maintained based on
two principles stated below:
 Firstly, the fewer the T-states of instruction cycle, the better the design.
 Secondly, for architecture, the fewer the MSI(Medium Scale Integrated) or LSI (Large
Scale Integrated) chips requirement, the better the design.
There will some other important specification which has to be maintained to design the 4 bit
computer system. These are stated below:
 The bus will be of 8-bit address bus and 4-bit data bus.
 There will be two independent units inside the processor – Fetch Unit and Execution
Unit. So two stage pipe line will be preferable.
 In addition, programs (comprising instructions from the instruction set assigned) has
to be written on a normal PC and then sent the appropriate machine codes through
communication ports to the microcomputer implemented .
Assigned Instruction Set
Section:B2
Group:02
LDA address; STA address; MOV Acc, B; MOV B, Acc; MOV Acc, immediate; IN;
OUT; ADD B; ADC B; SUB B; SBB B; ADC immediate; SBB immediate; CMP B;
XCHG; JC address; JE address; PUSH; POP; CALL address; RET; JMP; HLT; NOP;
STZ; CLZ; AND immediate; OR [address];

Solution Approach
In order to design our 4 bit computer system we have maintained some specific approaches
stated below:
 For executing 28 instructions maintaining fewer clock cycles on average, the entire
system is designed in such a way that it consists of a 2 stage pipeline – instruction fetch
& decode unit and 4 bit execution unit.
 The execution unit has been designed so that it has a shared 4 bit data bus.
 The memory system is organized as Harvard architecture. That is instruction memory
and data memories are separate units.
Figure: Harvard architecture
 Programs are stored in instruction memory and data in data memory. Data memory also
contains the program stack.
 All instructions are either 1 or 2 bytes long. Some instructions require 1 clock cycle on
average and others require 2 clock cycles on average.
 The computer is designed in such a way that it can also communicate with the external
devices through the input and output port registers.
 As the instruction set contains all types of instructions which generalize the computer to
execute any kind of program. However the 8 bit address bus restricts the program
length to be within 256 Bytes. The 4 bit arithmetic and logic unit can perform addition
and subtraction and several logical operations.

Instruction Set
Instruction Description
LDA address Acc  Memory [address]
STA address Memory [address]  Acc
MOV Acc, B Acc  B
MOV B, Acc B  Acc
MOV Acc, immediate Acc  immediate
IN Acc  input_port
OUT Output_port  Acc
ADD B Acc  Acc + B
ADC B Acc  Acc + B + C (Contents of Carry Flag)
SUB B Acc  Acc – B
SBB B Acc  Acc – B – Bo (Contents of Carry Flag)
ADC immediate Acc  Acc + immediate + C (Contents of Carry Flag)
SBB immediate Acc  Acc – immediate – Bo (Contents of Carry Flag)
CMP B Accumulator will be unchanged. Set flags according to (Acc – B).
XCHG Acc ↔ B (Exchanges contents of Accumulator and B)
JC address Jumps to the address if carry flag is set
JE address Jump if equal
PUSH Pushes the content of Accumulator to the stack
POP Pops off stack to Accumulator
CALL address Calls a subroutine (at the specified address) unconditionally
RET Returns from current subroutine to the caller unconditionally

Instruction Description
JMP address Jumps unconditionally to the address
HLT Halts execution
NOP No Operation
STZ Sets the zero flag
CLZ Clears the zero flag
AND immediate Acc  Acc . immediate
OR [address] Acc  Acc | Memory [address]
Description of Important Component
1. Fetch and decode unit
This unit supplies instructions in program order to the execution unit. It performs the following
functions:
 Fetches instructions that will be executed next 
 Decodes instruction into micro‐instructions 
 Generates micro‐code for executing microinstructions 
I. Program counter register
The program counter register contains the address of the next instruction to be executed. It is
incremented automatically at each clock cycle to contain the next instruction address or
operand address. Sometimes it is directly loaded with address values by JMP, CALL, RET, JE and
JC instructions. The output of the program counter register is directly fed to the input of the
instruction memory.
II. Instruction memory
Instruction memory is a 256X8 RAM. It has 8 address pins and 8 output pins. So it is byte
addressable. Each byte contains the desired instruction. The read signal of instruction memory
is always activated. Since address inputs are directly connected with the outputs of program
counter register, hence the memory output is always available without requiring any extra clock

cycle. As long as program counter outputs are valid, memory outputs are also valid. There is no
need to write the instruction memory. Because we used separate memory for data and
instruction. Data write and stack writes occurs on the data memory. Since program code is read
only, hence write signal of instruction memory is deactivated permanently. Only at the start of
the simulation program code needs to be loaded in the instruction ROM.
III. Instruction register
The instruction register holds the opcode of the instruction that is being executed on the
execution unit. This register is 8 bits long. The instruction register content is directly fed to the
instruction decoder unit to generate the micro‐operations for each instruction.
IV. Instruction memory buffer register
This register is used to hold the content of the second byte for all 2 byte instructions. The first
byte which is the opcode byte is stored in the instruction register. During the first clock cycle
the opcode byte is fetched into the instruction register. During the second clock cycle the
second byte is fetched and stored in the instruction memory buffer register. The instruction
register is not loaded during the second clock cycle.
V. MUX1, Data memory address selector
This MUX controls the input to the data memory address. The possible inputs can be
 SP value, required in PUSH instruction. 
 SP value + 1, required in POP instruction.
 Instruction memory buffer register output, required in indirect data memory access
where data address value is given as second byte of the instruction.
VI. Adder for computing PC + 1 and output buffer
This adder computes the value of current program counter + 1. It is required in CALL instruction
where we need to save the address of next instruction to the stack. The 3 state buffer in front
of the adder for PC + 1 output is necessary so that the adder output does not load the data
memory output bus while data memory is accessed for other purpose.

VII. Bidirectional transceiver
 In some instructions we require that the data memory output is to be passed to the
shared data bus. 
 In some other instructions we require that shared bus output is to be loaded to the data
memory output bus. 
 In other cases the data memory must not load the shared bus while others are using it. 
To meet all the above purposes we require a bi‐directional 3 state buffer. The bus transceiver
does the same. It has a chip select pin. If this pin is in active it does no load the bus on both
sides. When chip select pin inactive, then depending on another pin (data direction pin), it
transfers data from any one side to the other side.
VIII. Instruction decoder unit
Instruction decoder unit decodes each instruction according to their type. This is a ROM that
generates the appropriate micro‐operation depending on the value in the instruction register.
This decoder actually determines the ROM address at which the instruction is to be handled.
The ROM address thus found generates the control signals for handling the execution of the
instruction. However at the next clock cycle, the control ROM address might be selected from
other sources other than instruction decoder output as determined by the instruction type and
length of clock cycle required to execute it. The important thing that it does is that it maps
many instructions to the same initial address (all these instructions have same output from the
control ROM) of the ROM since all those instructions have the same control signals in their first
clock cycle. It reduces number of rows needed for the control ROM thus reducing the ROM size.
2. Execution unit
The execution unit can perform arithmetic and logic operations, transfer values between
general purpose registers and data memory and input and output port registers.
I. Arithmetic and logic unit
This is a 4‐bit arithmetic and logic unit that supports the following operations:
 Arithmetic operations –addition, subtraction, increment, decrement and transfer
operation 
 Logical operations – logical or, xor, and, compliment operations

The operation of arithmetic logic unit is as determined by the function pins are given below:
One operand of the arithmetic logic unit is the accumulator register. The other operand is
selected by MUX2. The two selector pins S1, S0 of MUX2 selects second operand as follows:
S1 S0 Operand
0 0 B register
0 1 1
1 0 Data memory output
1 1 Instruction memory buffer register output
 Immediate operands are selected from instruction memory buffer register output. 

 Memory operands are selected from data memory output. 

 During NEG instruction value 1 is selected. 

 During all other arithmetic and logic instructions B register is the second operand. 


II. Registers
The entire register set consists of:
 Two general purpose registers Accumulator register and B register
 One program status register or flags register 
 One temporary register 

 One input port register 

 One output port register 
III. Functions of each register
 Accumulator : For any arithmetic or logic operation one operand is the default accumulator
register and the result also goes to this register. 


 B register : This works as a general purpose temporary storage register. We can move
values in and out of this register to the accumulator. This register can also be selected as
the second operand for some arithmetic and logic operations. 

 Temp register – The temporary register is used for XCHG instruction. It is used for swapping
the content of the accumulator with the content of B register. 

 Input port register – The input port register is used for interfacing with devices outside the
computer. This register is used to receive input values from devices like keyboard or any
other device. 

 Output port register – the output port register is used to send data to devices external to
the computer. This device can be either a display or anything. 

 Flags register –Stores status of recent arithmetic or logic operation. 
IV. The Status Flags Register
The status flags of the 4‐bit flags register indicate the results of arithmetic and logic operations
such as ADD, SUB, OR, XOR. The status flag functions are:
CF (bit 0) Carry flag – Set if an arithmetic operation generates a carry or a borrow
out of the most significant bit of the result; cleared otherwise. This flag
indicates an overflow for the unsigned‐integer arithmetic.
SF (bit 1) Sign flag – Set equal to the most significant bit of the result which is the
sign bit of the signed integer.
ZF (bit 2) Zero flag – Set it the result is zero; cleared otherwise.
VF (bit 3) Overflow flag – Set if the integer result is too large a positive number or
too small a negative number (excluding the sign bit) to fit in the
destination operand; cleared otherwise. This flag indicates an overflow
for signed integer arithmetic.

Functionalities of the status flag register are given below:
 Arithmetic operations modifies all flags 

 CF and VF are not changed during logic operations. 

 The status flags allow a single arithmetic or logic operation to produce results for two
different data types: unsigned integers and signed integers.
 When performing multiple precision arithmetic on integers, the CF flag is used in
conjunction with add with carry (ADC) and subtract with borrow (SBB) instruction to
propagate a carry or borrow from one computation to the next.
 The conditional branch instructions (such as JE, JC) use one or more of the status flags as
condition codes and test them for branching.

Block Diagram of 4 bit PC Architecture

Description of Control Unit
Control unit consists of five 32K (4K X 8) ROM and one 32 K(4K X 8) ROM and 3 4 x1
MUX for instruction decoder and control circuit . The ROM generates the control
word for each micro‐instruction and the 2 bit flip flop stores the next address selector
value which is fed into a MUX selector pins to select control ROM address.
The full block diagram of control unit is given below:
Figure: Block Diagram of Control ROM

Control State Diagram:
Figure: State Diagram for Control ROM
The working principle of control unit is Stated below :
 For all instructions, at the first clock cycle the control ROM address is selected from
instruction decoder output. 

 The next address selector input from the control ROM output selects the appropriate
next address of the control ROM through the MUX. 

 For some 2 cycle instructions, at the second clock cycle the control ROM address input is
selected from the instruction register output. These instructions have same control
signals in their first clock cycle, however different control signals in their second clock
cycle. 

 For some other 2 cycle instructions, at the second clock cycle control ROM address input
is selected as the constant value 31. This is because all these instruction have same
control signals in their second clock cycle although they have different control signals in
their first clock cycle. 

Instruction Template & Op-codes
Instruction Length (in Byte) OP-Code (in binary) OP-Code (in hex)
Byte 1 Byte 2 Byte 1 Byte 2
ADD B 1 0000 0001 01
ADC B 1 0000 0010 02
SUB B 1 0000 0011 03
SBB B 1 0000 0100 04
CMP B 1 0000 0101 05
MOV Acc ,B 1 0000 0110 06
MOV B ,Acc 1 0000 0111 07
IN 1 0000 1000 08
OUT 1 0000 1001 09
STZ 1 0000 1010 0A
CLZ 1 0000 1011 0B
LDA [addr] 2 0000 1100 addr 0C addr
STA[addr] 2 0000 1101 addr 0D addr
MOV Acc , imm 2 0000 1110 imm 0E imm
ADC imm 2 0000 1111 imm 0F imm
SBB imm 2 0001 0000 imm 10 imm
AND imm 2 0001 0001 imm 11 imm
OR[addr] 2 0001 0010 addr 12 addr
JC addr 2 0001 0011 addr 13 addr
JE addr 2 0001 0100 addr 14 addr
CALL addr 2 0001 0101 addr 15 addr
JMP addr 2 0001 0110 addr 16 addr
XCHG 1 0001 0111 17
RET 1 0001 1000 18
PUSH 1 0001 1001 19
POP 1 0001 1010 1A
NOP 1 0001 1011 1B
HLT 1 0001 1100 1C

Control Matrix Sheet
Control Address Matrix Hex value
0000 00
0001 01
0002 02
0003 03
0004 04
0005 05
0006 06
0007 07
0008 08
0009 09
0010 0A
0011 0B
0012 1E
0013 1E
0014 1E
0015 1E
0016 1E
0017 1E
0018 1E
0019 13
0020 14
0021 15
0022 16
0023 17
0024 18
0025 19
0026 1A
0027 1B
0028 80
0029 00
0030 00
0031 00

Pin Designation & Description of Control Rom
 PCOPS.1:0 – these two bits selects the pc operation at the next clock cycle according to
the following table: 
S1 S0 Operation
0 0 Increment PC
0 1 Load PC
1 0 Load PC if V = 1
1 1 Load PC if Z = 1
 PCINSEL – this pin selects the value to be loaded into the program counter. If 1 loads pc
with the value from instruction memory output; otherwise loads pc from data memory
output.

 IOPCODELOAD – Load instruction register. If 1 loads the instruction register with the
value of instruction memory at the next clock cycle. 

 DM.S1:S0 – these two bit selects the address that will be the input to the data memory
according to the following table: 
S1 S0 Address input to data memory
0 0 Instruction memory buffer register
0 1 SP
1 0 SP+1
1 1 Unused
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
ROM1 Pcops1 Pcops0 pcinsel Iopcodeload Dms1 Dms0 Spcntsel Spcnt
ROM2 Dmdbbirenble Dmdb Accout Accload Dmrws pcnextdm Immout Aluout
ROM3 Alubs1 Alubs0 Baseload Baseout Inout Outload Nss1 Nss0
ROM4 Alus3 Alus2 Alus1 Alus0 Alum ALUCNS0 Zfs0 Tmpout
ROM5 Flagload Tmpload Zfs1

 SPCNTSEL ‐ if 1 increments the stack pointer register at the next clock cycle; otherwise
decrements. Note that this pin is active only when SP.CEN = 1. 
 SPCNT – count enable signal for SP. This pin enables SP.U/D# signal. 

 DMDBBIRENBLE – this pin enables the bus transceiver. 

 DMDB ‐ if 1 the bus transceiver sends data (from data memory to the data bus);
otherwise receives data (from data bus to data memory). 

 ACCOUT – output enable signal for the accumulator register. If active the accumulator
loads the data bus with its contents. 

 ACCLOAD ‐ load signal for the accumulator register. If active accumulator will be loaded
with the value from data bus at the next clock cycle. 

 DMRWS ‐ data memory read/write# signal. If 1 data memory is selected for read
operation; otherwise data memory is selected for write operation. 

 PCNEXTDM ‐ this pin enables the output buffer for PC + 1 output latch. This loads the
output of the data memory output bus. 

 IMMOUT ‐ this pin enables output buffer for instruction memory buffer register. This
loads the data bus with the value of this register. 
 ALUOUT – output enable signal for arithmetic and logic unit

 ALUB.S1:S0 – these two bits selects the second operand for the arithmetic and logic
operation according to the following table:
S1 S0 Operand
0 0 B register
0 1 1
1 0 Data memory output
1 1 Instruction memory buffer register Output
 BASELOAD ‐ load signal for B register. 

 BASEOUT – output enable signal for B register. 


 INOUT‐ output enable signal for input port register 

 OUTLOAD‐ load signal for output port register. 

 NS.S1:S0 – selects next ROM input 

 ALU.S3:S0 – these FOUR bits selects the appropriate ALU operation to be performed. 

 ALUM – selects the mode of ALU operation. If 1 the operation is logic; otherwise
operation will be arithmetic 
 ALUCNS0 – this bit determines the carry in signal for ALU along with some other bits. 

 ZFS0 – clear the Zero flag. 
 ZFS1 – set the Zero flag. 
 TMPOUT – output enable for temp register.
 FLOAD ‐ load signal for flags register.
 TMPLOAD – load signal for temp register.

Contents of Control Rom
Address ROM1 ROM2 ROM3 ROM4 ROM5
0000 11 9C 2C 00 00
0001 11 8D 2C 94 00
0002 11 8D 2C 90 00
0003 11 8D 2C 60 00
0004 11 8D 2C 64 00
0005 11 9C 2C 60 00
0006 11 8C 3C 00 80
0007 11 BC 0C 00 80
0008 11 8C 24 00 80
0009 11 BC 28 00 80
0010 11 9C 00 02 20
0011 11 9C 00 00 20
0012 11 4C 2C 00 80
0013 11 34 2C 00 80
0014 11 8E 2C 00 80
0015 11 8D EC 90 00
0016 11 8D EC 64 00
0017 11 8D EC B8 00
0018 11 4D AC E8 00
0019 A1 9C 2E 00 80
0020 E1 9C 2E 00 80
0021 65 90 2E 00 80
0022 61 9C 2E 00 80
0023 01 8C 3F 00 40
0024 4A 5C 2E 00 80
0025 15 34 2C 00 80
0026 1A 4C 2C 00 80
0027 00 00 00 00 00
0028 00 00 00 00 00
0029 01 9C 0E 01 00
0030 01 AC 2D 00 80
0031 11 9C 2C 00 80

Instructions’ Steps (Timing Diagram)
After power on the computer system starts execution of the program starting at memory
location 0000 of the instruction memory. Hence the first instruction of the program must be
loaded at this address. After then an unconditional jump instruction can be used to run
programs starting at any other address.
The instruction memory must be loaded with the program to be executed. The data memory
should be loaded with initial data values if program requires. The stack pointer (SP register) is
initially loaded with the value FFH at start up. Note that all data values and stack pops fetches
values from data memory. Stack pointer grows from higher end (address FF) of the data
memory to the lower addresses. After start up contents of any other register are undefined.
The entire program must end with the HLT instruction. Otherwise processor will not stop
executing instructions and thus no output can be observed.
The two stage pipeline architecture allows one instruction in executing while another
instruction is fetched from the instruction memory. Some instructions are executed in two clock
cycles (containing 1 fetch cycle and 1 execution cycle) and others require three clock cycles
(containing 2 fetch cycle and 1 execution cycle).
A two cycle instruction execution requires the following steps:
Before the first clock cycle occurs, program counter contains the address of the instruction to
be executed. This address value is directly connected to the input address of instruction
memory. Hence the Op-code value is available at the output of the instruction memory. 

 Clock cycle 1‐ At the first clock cycle (low to high transition) the Op-code value is loaded
in the instruction register. The output of the instruction register is directly fed to the
input of the instruction decoder. Hence decoded output of the decoder is available
before the next clock cycle occurs. The decoded output is fed to the input of the control
ROM which generates the control world before the next clock cycle occurs. 
 Clock cycle 2 – At this clock cycle the instruction is executed. Since control word was
generated before this clock cycle, hence result of arithmetic or logical operation are also
computed before this clock cycle and appears in the shared data bus. Only the output of
the instruction is loaded at the low to high transition of this clock cycle. Fetch of next
instruction also occurs in this clock cycle. 

Clock cycle 1: Clock cycle 2:
Fetches op-code Executes
instruction
Fetches next
instruction
A three cycle instruction execution (except the control transfer instructions) requires the
following steps:
Before the first clock cycle occurs, program counter contains the address of the instruction to
be executed. This address value is directly connected to the input address of instruction
memory. Hence the Op-code value is available at the output of the instruction memory. 

 Clock cycle 1 ‐ At the first clock cycle (low to high transition) the Op-code value (first
byte of the instruction) is loaded in the instruction register. The output of the
instruction register is directly fed to the input of the instruction decoder. Hence
decoded output of the decoder is available before the next clock cycle occurs. The
decoded output is fed to the input of the control ROM which generates the control
world before the next clock cycle occurs. 



 Clock cycle 2‐ At the second clock cycle (low to high transition) second byte of the
instruction is loaded in the instruction memory buffer register (the instruction register
remains unchanged and contains the first byte of this instruction that was loaded at the
previous clock cycle). This can be either an immediate operand or data memory address
operand. 



 Clock cycle 3 – At the third clock cycle the instruction is executed. Since control word was
generated before this clock cycle, hence result of arithmetic or logical operation are also
computed before this clock cycle and appears in the shared databus. Only the output of
the instruction is loaded at the low to high transition of this clock cycle. In this clock
cycle fetch of next instruction also occurs.
Clock cycle 1: Clock cycle 2: Clock cycle 3:
Fetches op-code Fetches operand Executes
value Fetches next
instruction

For control transfer instruction (such as JMP, CALL) the following steps occur:
 Clock cycle 1 – same as others. 



 Clock cycle 2‐ At this clock cycle, the program counter is loaded with address value
selected by MUX3 from either instruction memory ( during JMP, JE, JO, CALL
instructions) or data memory ( during RET instruction). In case of CALL instruction, the
address of the next sequential instruction (current program counter value + 1) is also
stored in the stack (data memory) at this clock cycle. The selector pin S0 determines the
address value that is loaded to the program counter as follows: 
 Clock cycle 3 – At the third clock cycle no operation is performed. Only the fetch of the
next instruction occurs. This can be considered as a pipeline stall. 
Example:
Code Segment for example:
S0 Value
0 Instruction Memory Output
1 Data memory output
Clock cycle 1: Clock cycle 2: Clock cycle 3:
Fetches op-code Executes Fetches the
instruction Op-code for next
instruction
Address Instruction
00 IN
01 ADD B
02 SUB 09
04 PUSH
05 ADD B
06 POP
07 JMP 09

Figure: Actual timing diagram for example program with control signals
Another example for programs that has several pipeline stalls due to JMP, CALL and RET is given
below:
Address Instruction
00 IN
01 ADD B
02 CALL 08
08 RET
04 JMP 0A
10 ADD B

Figure: Time Line diagram for the example program
F1 Fetch op-code
F2 Fetch operand
E Execution
E1 Execution & Load PC
S Stall of execution pipeline
C Clock Cycle

Average CPI
In order to calculate average CPI (Cycles per Instruction) we have to consider separate clock
cycles for each instruction. For 2 cycle instructions, due to pipeline architecture clock cycle 2 (of
current instruction executing) and clock cycle 1(of next instruction) are performed parallel in
only 1 clock cycle. For 3 cycle instructions clock cycle 3 (of current instruction executing) and
clock cycle 1(of next instruction) are performed parallel in only 1 clock cycle This reduces the
average clock cycle required for each instruction executed. The following table shows the
required number of clock cycles for each instruction (considering pipelined architecture):
So, Average CPI = ((13*2)+15) = 1.46428
No. Instruction Clock cycles
1 ADD B 1
2 ADC B 1
3 SUB B 1
4 SBB B 1
5 CMP B 1
6 MOV Acc ,B 1
7 MOV B ,Acc 1
8 IN 1
9 OUT 1
10 STZ 1
11 CLZ 1
12 LDA [addr] 2
13 STA[addr] 2
14 MOV Acc , imm 2
15 ADC imm 2
16 SBB imm 2
17 AND imm 2
18 OR[addr] 2
19 JC addr 2
20 JE addr 2
21 CALL addr 2
22 JMP addr 2
23 XCHG 2
24 RET 2
25 PUSH 1
26 POP 1
27 NOP 1
28 HLT 1

IC used for 4-bit PC Design
IC Number Name Pcs
74126 Quadruple Bus Buffer Gate With Tristate
Outputs
8
74194 4-Bit Bidirectional Universal Shift Registers 6
74LS181 ALU/ Function Generators 2
7404 Hex inverter 4
74LS86 Quadruple 2-input Exclusive-OR Gates 1
4002 Dual 4-Input NOR Gate 1
74153 Dual 1-of-4 Data Selectors/Multiplexers 11
6116 16K (2K X 8) Static RAM 1
74LS245 Octal Bus Transceivers with Tristate
Outputs
1
7408 Quadruple 2-input Positive-AND Gates 2
4555 Dual 1-to-4 Line Decoder/ Demultiplexer 1
Counter_8 Universal Counter Digital Primitive Model
With Up/Down Clock
2
7483 4- bit Binary Full Adder With Fast Carry 4
2732 32K (4K X 8) EPROM 7
74157 Quadruple 1-of-2 Data
Selectors/Multiplexers
2
74198 8-bit Bidirectional Universal Shift Register
With Asynchronous Reset
2
Total IC used 55

How to simulate our 4-bit PC
1. At first, the assembler.cpp program has to be compiled and build which has been
written for generating the binary file with hex value from the instruction set in input.txt
file.
Figure: Compiling assembler.cpp
2. After compiling and executing the program, ‘out.bin’ has been created in the same
directory where ‘in.txt’ has been located.
Figure: Input Code Segment & Corresponding Generated output Hex value

3. We have used Proteus Design Suite [©Labcenter Electronics 1989-2009] Release 7.7 SP2
(Build 9089) with Advanced Simulation Tool for designing the 4-bit PC. Here, after
completing the design, all 7 ROM has been loaded with binary file. Among them , 5
binary files for Control Rom, 1 binary file for Control Matrix and last of all , generated
output binary file from given input code segment has been loaded into the Instruction
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M
]
.
F
Figure: Loading .bin file before starting the simulation
4. Then the simulation has been started and the 4-bit PC has been executing each
instruction one by one in the estimated clock cycle.
Figure: Our 4-bit PC successfully execute the given code segment

Discussion
 As , we have used Proteus Design Suite which is very user friendly and convenient for
designing the 4-bit PC , any modification in the design can be easily manipulated . We
have designed the circuit diagram with easy to handle wireless terminal method by
giving label and marking the important components with marker, for this anyone can
easily understand the circuit diagram from block diagram.
 We have separated the data memory from instruction memory. This reduced number
of average clock cycles for those instructions to be nearly to one. We have easily
manipulated writing to data memory by using 16K (2K X 8) Static RAM.
 The design contains 4-bit data bus, there is no need for address bus in our design as
address has not been needed to be shared like the data. There is two independent units
inside the processor – Fetch unit and Execution unit, so two stage pipe line has been
successfully implemented.
 Average CPI is calculated 1.46428 and the number of IC used is 55 only. So it can be
stated that , our 4-bit PC design both satisfies the condition of lowering the T-states of
instruction cycle and using the fewer MSI/LSI chips for the design.
The Circuit Diagram (.DSN file), assembler (.cpp file), block diagram (.pptx file) and other
necessary (.bin) files are available for anyone for further usage and modification at following
link:
4-bit PC Contents Available Here for You.

4bit pc report[cse 08-section-b2_group-02]

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4bit pc report[cse 08-section-b2_group-02]