synthesis_0501 in digital vlsi design.ppt

Specification Architectural design
Prototype & Testing
Fabrication
Functional & Logic design
Circuit design
Physical design
Physical Verification

Front end design
Architectural design
Prototype & Testing
Fabrication
Circuit design
Physical design
Behavioral Description
HDL Description
Functional simulation
Logic synthesis
Post synthesis simulation
Specification
Front end design
Architectural design
Prototype & Testing
Fabrication
Circuit design
Physical design
Behavioral Description
HDL Description
Functional simulation
Logic synthesis
Post synthesis simulation

Specification Architectural design
Prototype & Testing Fabrication
Circuit design
Physical design
Partitioning
Floorplan
Placement
Clock Tree Synthesis
Routing & Timing Check
Physical design-
Back-end design

RTL description
Functional
simulation
Logic
Synthesis
Post Synthesis
simulation
Design partition
Logic Optimization
Initial gatelevel netlist
RTL development
RTL integration
Translation
Unoptimized Boolean
representation
Technology Maping & Opt.
Timing Check
Optimized
Netlist
Post synthesis
sim.

What is Synthesis?
Synthesis is the process that converts RTL into a technology specific gate-level netlist
optimized for a set of pre-defined constraints.
You start with: A behavioural RTL design,A standard cell library, a set of design
constraints
You finish with :A gate-level netlist, mapped to the standard cell library, optimized for
area, speed and power
Synthesis
RTL design Standard cell library Design constraints
Optimized gate level netlist
Mapped to standard library
(ASIC)
LUT,FF (PGA)

Different types of synthesis
X=a+b+c;
Y=M*X
module foo
(a,b,c,Y);
input [3:0] a;
…

RTL code Gate level netlist
Library file .lib
Design constraint (.sdc)
Synthesis

What is logic synthesis?
Logic synthesis is the process of optimizing logic representations with the final goal of:
• Speeding up a circuit
• Reducing its area and manufacturing cost
• Reducing the energy consumption
(c) Giovanni De Micheli 9

Why perform logic synthesis?
Automatically manages many details of the design process:
Fewer bugs
Improves productivity
Abstracts the design data (HDL description) from any particular implementation technology
Designs can be re-synthesized targeting different chip technologies;
E.g.: first implement in FPGA then later in ASIC
In some cases, leads to a more optimal design than could be achieved by manual means (e.g.: logic
optimization)

module foo (a,b,s0,s1,f);
input [3:0] a;
input [3:0] b;
input s0,s1;
output [3:0] f;
reg f;
always @ (a or b or s0 or s1)
if (!s0 && s1 || s0)
f=a;
else
f=b;
endmodule

Goals
Minimize area
• In terms of literal count, cell count…
Minimize Power
Maximize Performance
• Clock frequency- synchronous systems
• Throughput – Asynchronous systems
Any combinations of the above..Minimize area for a clock frequency >200 MHz
Note: Performance indicators are conflictive- trade-off is the key!!

How does it work?
Instantiation
• Maintains a library of primitive modules (AND, OR, etc.) and user defined modules
Macro Expansion
• A large set of language operators (+, -, Boolean operators, etc.) expand to special circuits
Inference:
• Special patterns are detected in the language description and treated specially (e.g.,: inferring memory blocks from variable
declaration and read/write statements, FSM detection and generation from always@(posedge clk) blocks)
Logic Optimization
• Boolean operations are grouped and optimized with logic minimization techniques
Structural reorganization: move FF

Synthesis Flow
Syntax analysis
• Read HDL files and check for syntax errors.
Library definition
• Provide standard cells and IP Libraries.
Elaboration and Binding
• Convert RTL into Boolean structure.
• State reduction, encoding, register inferring
• Bind all leaf cells provided by libraries
Constraint definition
• Define clock frequency and other design constraints
Syntax
Analysis
Library
definition
Elaboration
& Binding
Logic
optimization
Technology
mapping
Post mapping
Optimization
Report

Synthesis flow
Logic Optimization:
• Map to generic cells and perform additional heuristics
Technology mapping:
• Map generic logic to technology libraries
Post mapping optimization:
• Iterate over design, changing gate sizes, Boolean literals,
• architectural approaches to try and meet constraints.
Report
• Report final result , move to timing analysis
Syntax
Analysis
Library
definition
Elaboration
& Binding Logic
optimization
Technology
mapping
Post mapping
Optimization
Report

Syntax analysis
Compilation is the process of reading the source code and analyzing the source
code for syntax and semantic errors.
Syntax
Analysis

The library definition stage tells the synthesizer where to look for
leaf cells for binding and the target library for technology mapping.
• We can provide a list of paths to search for libraries in:
• And we have to provide the name of a specific library, usually characterized for a single corner
• We also need to provide .lib files for IPs, such as memory macros, I/Os, and others.
• We can provide a list of paths to search for Verilog code in:
• Name of the Verilog file
Add design constraints (.sdc)
Library
definition
read_libs “TT1V25C.lib”
set_db init_lib_search_path “/design/data/my_fab/digital/lib/”

Standard cell Library
A standard cell library is a collection of well defined and appropriately characterized(in terms of area,
speed and power) logic gates that can be used to implement a digital design
Therefore, a standard cell library is collection of files
• with all the information required by the foundry.
Library
definition

Example
NAND standard cell layout
• •Cell height
• •Cell width
• •Voltage rails
• •Well definition
• •Pin Placement
• •PR Boundary
• •Metal layers
Library
definition

What cells are in a standard cell
library?
Combinational logic cells (NAND, NOR, INV, etc.):
• Variety of drive strengths for all cells.
• Complex cells (AOI, OAI, etc.)
• Diffèrent Fan-in
Buffers/Inverters
• Larger variety of drive strengths
• Clock cells
• Delay cells
• Level shifters
Sequential logic cells
• Latches , FF of different characteristics (posedge,negedge, reset….)
Physical cells (Filler cell, DeCap, Tie cell, anteena cell……we will talk later !!)
Library
definition

Level shifter
Level shifter cells are placed between voltage domains to pass signals from one voltage to another.
INH OUTL
VDDH
VSS
INL
VDDL
OUTH
VDDH
VSS
HL shifter
LH shifter
Physical cell: we will discuss later
Library
definition

Clock Cells
 General standard cells are optimized for speed.
• Not balanced---- gives clock skew !!!!
Special “clock cells” are designed with balanced rising/falling delays to minimize skew.
• Not optimized for data!! Only used for clock net
Library
definition

Sequentials
Flip Flops
Latches
Synh reset, asynch reset,
Posedge, negedge…
Library
definition

What files are in a standard cell
library?
Behavioral Views:
• Verilog description used for simulation, logic equivalence.
Physical Views:
• Layout of the cells (GDSIIformat) for DRC, LVS, Custom Layout.
• Abstract of the cells (LEFformat) for P&R, RC extraction.
Transistor Level:
• Spice/Spectrenetlist for LVS, transistor-level simulation.
• Often provided both with parasitics(post-layout) and without.
Timing/Power:
• Libertyfiles with characterization of timing and power for STA.
Behavioral (.v)
Abstract (.lef)
Layout (.gds)
Spice (.spi, .cdl)
Timing (.lib)
Library
definition

LEF –Library Exchange format
LEF (Readable in ASCII format)
• Technology LEF: A technology LEF contains all the placement and routing design rules, process information of the
technology, information about metal layer, via, design rules, geometry, abstract view, Direction, pitch, width (spacing
between same type of layer), spacing between different metal layer, unit resistance
• Cell LEF: Cell name. cell class (core/pad), cell size (width by height: height is constant), symmetry (x y xy), Details of each
pin, direction, layer etc..
Abstract description of the layout for P&R:
• Readable ASCII Format.
• Contains detailed PIN information for connecting.
• Does not include front-end of the line (poly, diffusion, etc.) data.
Library
definition

Abstract views only contain the following:
Outline of the cell (size and shape)
Pin locations and layer (usually on M1)
Metal
Pins
A B
Y
NAND_1
GND
VDD
Abstract View
Layout View
A B
VDD
GND
Y
Library
definition

Liberty timing files .lib
.lib is basically a timing model contains cell delays, transition, setup and hold time requirements.
For Library
• Library name (TSMC,..)and Technology (CMOS, FinFET..)
• PVT corners (max,min, Typical delay), wireload model, lookup table
• Cell specific informations, leakage power, area
For each pin:
• Pin direction, capacitance, Fan out load, rise capacitance, fall capacitance,
How do we know the delay through a gate in a logic path?
• •Running SPICE is way too complex.
• •Instead, create a timing modelthat will simplify the calculation.
Library
definition

Goal:
• •For every timing arc, calculate:
• •Propagation Delay (tpd)
• •Output transition (trise, tfall)
•Based on:
• •Input net transition (trise, tfall)
• •Output Load Capacitance (Cload)
Library
definition

© Adam Teman, 2018
Mapping
Post-mapping
Optimization
Report and
export
Liberty (.lib): Timing Models
• Non-Linear Delay Model (NLDM)
• Driver model:
• Ramp voltage source
• Fixed drive resistance
• Receiver model:
• Min/max rise/fall input caps
• Very fast
• Doesn’t model cap variation during transition.
• Loses accuracy beyond 130nm
lu_table_template(delay_template_5x5) {
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0");
index_2 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0");
}
cell (INVX1) {
pin(Y) {
timing() {
cell_rise(delay_template_5x5) {
values (
"0.147955, 0.218038, 0.359898, 0.922746, 1.76604",
"0.224384, 0.292903, 0.430394, 0.991288, 1.83116",
"0.365378, 0.448722, 0.584275, 1.13597, 1.97017",
"0.462096, 0.551586, 0.70164, 1.24437, 2.08131",
"0.756459, 0.874246, 1.05713, 1.62898, 2.44989"); }
Library
definition

• How do you estimate the parasitics (RC) of a net
before placement and routing?
• Wire Load Models estimate the parasitics based on the fanout of a net.
library (myLib) {
wire_load(“WLM1”)
resistance: 0.0006 ; // R per unit length
capacitance: 0.0001 ; // C per unit length
area : 0.1 ; // Area per unit length
slope : 1.5 ; // Used for linear extrapolation
fanout_length(1, 0.002) ; // for fo=1, Lwire=0.002
}
} /* end of library */
Wireload model Library
definition

Story so far:
• •We have loaded our design into the synthesizer.
• •And we have loaded our standard cell library and IPs.
Lets discuss actual synthesis process.
During the next step of logic synthesis, the tool:
• Compiles the RTL into a Boolean data structure (elaboration)
• Binds the non-Boolean modules to leaf cells (binding), and
• Optimizes the Boolean logic (minimization).
• The resulting design is mapped to generic, technology independent logic gates.
Syntax
Analysis
Library
definition
Elaboration &
Binding
Logic
optimization
Technology
mapping
Post mapping
Optimization
Report

During the next step of logic synthesis, the tool:
• Compiles the RTL into a Boolean data structure (elaboration)
• Binds the non-Boolean modules to leaf cells (binding), and
• Optimizes the Boolean logic (minimization).
The resulting design is mapped to generic, technology independent logic gates.
Then logic optimization, and technology mapping follows, Verification, STA
Background: Boolean algebra
Elaboration &
Binding

Elaboration is the process that occurs between parsing and simulation. It binds
modules to module instances, builds the model hierarchy, computes parameter
values, resolves hierarchical names, establishes net connectivity, and prepares
all of this for simulation.
 Elaboration is responsible to translate the design into a database of
interlinked generic elements which are independent of design language. All
the parameters in the design are processed. Also the linked design is checked
for missing port connections and report it in the logs.

Boolean Algebra
Boolean Algebra- K- map – studied earlier
Many different data structures are used to represent the Boolean function: Truth table, cube, Binary
Decision Diagram etc
K-map is not sufficient for real design, when number of variables > 6
We need different approach to handle it, may be different algorithm, different computational approach
Lets see two computational approaches to handle Boolean function
• Decomposition strategies: Breaking into smaller pieces
• Computational strategies: techniques to manipulate the function

Take an example of calculating exp(x). It can be decomposed into
exp(x)=1+x+x2
/2!+x3
/3!....,,
so if you have pieces like 1, x, x2
…its enough to compute exp(x)
Like this we have Taylor expansion, Fourier expansion in calculus.
Any thing for Boolean algebra? !!! Shanon Expansion
1916-2001

Shannon Expansion theorem
Suppose we have a function F(x1,x2,x3…xn), define new function setting for one of the variable xi=constant (either 1 or 0)
Example: F(x1,x2,x3…xi=1, …..xn), or F(x1,x2,x3…xi=0, …..xn).
For F(xyz)=xy+xz’+y(x’z+z’)
F(x=1,yz)=(1.y+1.z’+y(0.z+z’)
• =y+z’+yz’
F(x1,x2,x3…xi=1, …..xn) can be written as F(Xi=1) or Fxi termed as positive cofactor
F(x1,x2,x3…xi=0, …..xn) can be written as F(Xi=0) or Fxi’ termed as negative cofactor
So what????

Given any Boolean function F(x1,x2,x3…xn), and for any xi
F(x1,x2,x3… xi ….xn)= xi . F(x1,x2,x3…xi=1, …..xn) + x’i F(x1,x2,x3…xi=0, …..xn)

Data structure in Boolean
algebra:BDDVery efficient data structure Efficient manipulation routines
Shannon’s expansion theorem states that
F = xi’ f(xi=0) + xi f(xi=1)
= xi’ fi
0
+ xi fi
1
F= (xi+fi
0
). (x’i +fi
1
)
This leads to the formation of a BDD
f = ac + bc + a’b’c’
= a’ (b’c’ + bc) + a (c + bc)
= a’ (b’c’ + bc) + a (c)
b’c’ + bc c
a
f

Motivation
Efficient way to represent logic functions
History
• Original idea for BDD due to Lee (1959) and Akers (1978)
• Refined, formalized and popularized by Bryant (1986)
• Smaller memory footprint
• Canonical form – each distinct function correspond to a unique distinct diagram

 Each logic function has a unique representation
 Truth table
 Sum of minterms
Canonical forms - review
a b c F
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
a’bc+ab’c+abc

Terminology
A Binary Decision Diagram (BDD) is a directed acyclic graph
• Graph: set of vertices connected by edges
• Directed: edges have direction
• Acyclic: no path in the graph can lead to a cycle
Often abbreviated as DAG
• Simplest model:
• Two leaves (Boolean constants 0 and 1)
• One root
• Can degenerate to a tree

BDD - Example
F = (a + b) c
0 1
a
0
0
0 1
b b
0 1
0 1
c c
c
b
1
1
0
0
0 1 0 1
0 1 0 1
a b c F
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
1. Each vertex represents a decision on a variable
2. The value of the function is found at the leaves
3. Each path from root to leaf corresponds to a
row in the truth table

1. BDD
BDDs that represent the truth table of a given function f(x1,x2,x3)
0 1
1 0
0 1 0 1
0 1 0
x1
x2 x2
x3 x3
f(x ,x ,x )
1 2 3
~(x x )
2 3 x ~x
2 3
~x3
~x3
x3 x3
1
1 0
1
0 0
1
0
0 1 1
f(x , x , x ) = ~x ~x ~x + ~x ~x x + ~x x ~x + x x ~x
1 2 3 1 2 3 1 2 3 1 2 3 1 2 3
x x x
1 2 3 f(x x x )
1 2 3
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 1

Boolean function to tree structure
x x x
1 2 3 f(x x x )
1 2 3
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1
1 1 1
Variable ordering in the ordering by which the decisions are made
0 1
0 1
0 1 0 1
0 1 0
x1
x2 x2
x3 x3
f(x ,x ,x )
1 2 3
x3 x3
0
0 1
0
0 1
1
0
0 1 1
Vertex represents variable
edge represents decision
--- for 0, for 1
A constant vertex at the bottom of the tree, output of the function
Its too big to be useful

Different variable ordering
Its possible!!!
0 1
0 1
0 1 0 1
0 1 0
x1
x2 x2
x3 x3
f(x ,x ,x )
1 2 3
x3 x3
0
0 1
0
0 1
1
0
0 1 1
0 1
0 1
0 1 0 1
0 1 0
x1
x2 x3
x3 x2
f(x ,x ,x )
1 2 3
x3 x2
0
0 1
1
0 0
1
0
0 1 1

BDD
Each path from root to leave traverses in the same order
Each such path corresponds to a row in the truth table.
If we don’t specify any order, Its not unique representation for a function f. So its not canonical!!!.
Its too big!!!
Canonical: Representation that does not depend on the gate level implementation of a Boolean function
Same function of same variable always produce same representation
• Ex. Truth table
Canonical representation is required. Small tree is required

2. Ordering
Restrict global variable ordering:Every path from root to leaves follows the SAME variable order
You can omit some variable (redundancy!!!!!)
Assign some ordering to variables: x1<x2<x3
• Variables must obey the same ordering in all path, its ok to skip some.
1
x
2
3
3
x
x
x
1
x
2
x
1
3
x
x

Two diagram same function
0 1
0 1
0 1 0 1
0 1 0
x1
x2 x2
x3 x3
f(x ,x ,x )
1 2 3
x3 x3
0
0 1
0
0 1
1
0
0 1 1
0 1
0 1
0 1 0 1
0 1
x1
x2 x3
x3
f(x ,x ,x )
1 2 3
x3
0
0
0 1
0 1

3. Reduce the BDD
Throughout redundancy. If order is fixed, always get the same BDD for a given function. Becomes
canonical!!
Identify Redundancies in the graph, that can remove some unnecessary nodes and edges.
Advantages:
• Size will be small
• Canonical (same function, same variable order, unique graph representation)

Reduction Rule 1: Merge equivalent leaves
a
a a
0 1
0 1
0 1 0 1
0 1 0
x1
x2 x2
x3 x3
f(x ,x ,x )
1 2 3
x3 x3
0
0 1
0
0 1
1
0
0 1 1
0 1
0 1 0 1
x1
x2 x2
x3 x3
f(x ,x ,x )
1 2 3
x3 x3
1
0

Reduction Rule 2: Merge isomorphic nodes: 2 nodes with same variable and
identical children
y
x
z
x
y
x
z
x
0 1
0 1 0 1
x1
x2 x2
x3 x3
f(x ,x ,x )
1 2 3
x3 x3
1
0
0 1
0
1
0
1
x1
x2 x2
x3
f(x ,x ,x )
1 2 3
x3
1
0

ROBDD
Reduction Rule 3:Elliminate Redundant Tests:
 Children go to same node
y
x
y
0 1
0
1
0
1
x1
x2 x2
x3
f(x ,x ,x )
1 2 3
x3
1
0
0 1
0
1
x1
x2
x3
f(x ,x ,x )
1 2 3
1
0
0
0
Two functions are identical if
their ROBDD are same
It is canonical for same var
ordering!!!

1. Merge equivalent sub-trees
0 1
a
0 1
0 1
c
b
b
0 1
c
1
0
0 1
0 1
a
1
0
0 1
c c
0 1
0 1
c c
b
b
1
0
0
0
0 1 0 1
0 1 0 1
before after

2. Remove node with identical children
0 1
a
0 1
0 1
c
b
b
0 1
c
1
0
0 1
before after
0 1
a
0 1
b
c
1
0
0 1

BDD semantics
Constant nodes
0 1
x
0 1
ITE(x,F1,F0)
then edge
else edge
0-cofactor 1-cofactor
F0 F1
Cofactor(F,x): the function you obtain when you substitute 1 for x in F

F =ACB’+DEF’+A’BCF+…
F =C’B’+D’GH’+A’FG’+…
Inferred Registers
x x x
1 2 3 f(x x x )
1 2 3
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 1
Boolean Logic
Two-level Logic
During elaboration, primary inputs and outputs (ports) are
inferred and sequential elements (flip-flops, latches)
Input ports and register outputs are inputs to the logic
Output ports and register inputs are the outputs of the logic
The outputs can be described as Boolean functions of the inputs
The goal of Boolean minimization is to reduce the number of literals in the output functions

Definitions
Scalar function:
• ON-set
• Subset of the domain such that f is true
• OFF-set
• Subset of the domain such that f is false
• DC-set
• Subset of the domain such that f is a don’t care
Multiple-output function:
• ON, OFF, DC-sets defined for each component

Cubical representation

Cubical representation of minterms and
implicants
 f1 = a’b’c’ + a’b’c + ab’c + abc +abc’
 f2 = a’b’c + ab’c
111
f1
c
b
a
000
001
110
101
α
β
γ
δ
f2
001
101
β

Definitions
Boolean variables
Boolean literals:
• Variables and their complement
Product or cube:
• Product of literals
Implicant:
• Product implying a value of the function (usually 1)
Minterm:
• Product of all input variables implying a value of the function (usually 1)

Tabular representations
Truth table
• List of all minterms of a function
Implicant table or cover
• List of implicants sufficient to define a function
Note:
• Implicant tables are smaller in size as compared to truth tables

Representations
Visual representations
• Cubical notation
• Karnaugh maps
Computer-oriented representations
• Matrices
• Sparse
• Various encoding
• Binary-decision diagrams
• efficiency

65
Lets talk about implementation &
minimization
We will learn
• Two-level logic optimization
• Multilevel logic optimization

Programmable logic arrays
Macro-cells with rectangular structure
• Implement any multi-output function
Programmable
• Old technology using fuses
• Grandfather of FPGAs
Programmed
• Layout generated by module generators
• Fairly popular in the seventies/eighties
Advantages
• Simple, predictable timing
Disadvantages
• Less flexible than cell-based realization
• Dynamic operation in CMOS

Programmable logic array
 f1 = a’b’ + bc’ + ab; f2 = bc’
Each literal translates to 2
transistors

Two-level minimization
Assumptions
• Primary goal is to reduce the number of implicants
• All implicants have the same cost
• Secondary goal is to reduce the number of literals
Rationale
• Implicants correspond to PLA rows
• Literals correspond to transistors

Definitions
Prime implicant
• Implicant not contained by any other implicant
Prime cover
• Cover of prime implicants
Essential prime implicant
• There exist some minterm covered only by that prime implicant
• Needs to be included in the cover
Each product term is called as a “Cube” or “implicant “ or
“product term”
Literal: An instance of variable ex. (ab+ab’) has 4 literals
Biggest “cube” as far as possible - “primes” or prime implicants:
A cube for which no literal can be removed
“Irredundant”- absolutely required

Two-level logic minimization
Exact methods
• Compute minimum cover
• Often difficult/impossible for large functions
• Based on Quine-McCluskey method
Heuristic methods
• Compute minimal covers (possibly minimum)
• Large variety of methods and programs
• MINI, PRESTO, ESPRESSO

Logic optimization: It, is the process of finding an equivalent representation of the specified
logic circuit under one or more specified constraints. Generally the circuit is constrained to minimum
chip area meeting a prespecified delay. [Wikipedia]
Two-level minimization
Logic optimization
Multi level minimization

Two level minimization
Two level realization: It has two stage, 1st
stage AND gates, 2nd
stage OR gate (SOP)/ Vice versa
(POS)
In SOP, Many AND gates 1 OR gate or vice versa
Example F= BC’+BD’+A’C’D’+A’CD’
• Has 4 AND gates , 10 literals
The goal is to minimize number of AND gates
The goal is to minimize the number of wires
• Essentially minimize number of AND gates and number of literals
Logic
optimization

Two level optimization
Earlier methods
• Boolean algebra: Difficult to optimize/minimize for larger number of variables
• K-map: Same For n inputs, the map contains 2n
entries (difficult to automate)
• Tabular methods - Quine-McCluskey- High computational complexity
Can we think about some methods that will give good solution but not the best!!
Can we think about getting solution iteratively (refining the previous solution). Current solution is
better than previous solution, till no further improvement
Yes, possible!!!

Same function may give best solution, good solution
The cost associated with global best solution is minimum
The cost associated with other solution is not global best,
• So is it possible to get good solutions quickly!!!
A heuristic method to get not perfect solution but good solutions iteratively by refining the previous
solution- ESPRESSO

Example
1 1
1 1 1 1
1 1
1 1 1 1
ab
cd 00 01 11 10
00
01
11
10
a b c d F
0 * 0 * 1 P
0 * 1 0 1 Q
1 0 0 1 1 R
1 1 0 1 1 S
1 * 1 * 1 T
P
Q
T
R
S
Each row defines a cube, may not be prime

Expand each cube to be prime
Make each cube as big as possible.: different ways in different direction.
1 1
1 1 1 1
1 1
1 1 1 1
cd 00 01 11 10
00
01
11
10
R
S
P
Q
T
1 1
1 1 1 1
1 1
1 1 1 1
cd 00 01 11 10
00
01
11
10
R
S
T
Q
P

Remove redundant cube
1 1
1 1 1 1
1 1
1 1 1 1
00 01 11 10
00
01
11
10
R
S
T
Q
P 1 1
1 1 1 1
1 1
1 1 1 1
00 01 11 10
00
01
11
10
R
T
Q
P
It s a prime cover,, and minimal,
Can not remove another cube without
Breaking it.
A cube is redundant if by removing it also, all its
1 s are covered by other cube
ab
S is one redundant cube, there maybe other cube also as T, take any one, say S

Reduce the prime cover
R
1 1
1 1 1 1
1 1
1 1 1 1
00 01 11 10
00
01
11
10
T
Q
P
Shrink each cube as far as possible
But do not uncover any 1
1 1
1 1 1 1
1 1
1 1 1 1
00 01 11 10
00
01
11
10
T
Q
P
R
When we expand it again, we may get a
Better solution, we can try
ab ab

Expand
1 1
1 1 1 1
1 1
1 1 1 1
00 01 11 10
T
Q
P
R
1 1
1 1 1 1
1 1
1 1 1 1
00 01 11 10
T
Q
P
R
T is redundant
ab ab
00
01
11
10 10
00
11
01

irredundant
1 1
1 1 1 1
1 1
1 1 1 1
00 01 11 10
T
Q
P
R
ab
10
00
11
01
1 1
1 1 1 1
1 1
1 1 1 1
00 01 11 10
Q
P
R
ab
10
00
11
01
It is better, its prime, its minimal, irredundant solution

1 1
1 1 1 1
1 1
1 1 1 1
00 01 11 10
00
01
11
10
T
Q
P
R
1 1
1 1 1 1
1 1
1 1 1 1
00 01 11 10
00
01
11
10
T
Q
P
R
Reduce
Irredundant
Expand
ab
ab

ESPRESSO(F) {
do {
reduce(F);
expand(F);
irredundant(F);
} while (fewer terms in F);
verify(F);
}
Start with an SOP solution.
Reduce
Expand
Irredundant
Its good idea but every piece of logic (industrial design) can not be implemented using
two level logic implementation style.
So what next?? We need to think different model!!

Multilevel logic implementation
2 level implementations has two planes.
Area: Number of gates + literal (wires)
Delay :Maximum level of logic gates required to compute the function
Area
Delay
2 –level fastest but more area
Multi-level - slow but less area
TRADE OFF
Multi logic is technology independent

For higher number of inputs, two level logic need more number of gates
Example 1000 variables AND gate block of logic!!! 1000 fan in gate????
If we think it can be implemented using different stages, then number of gates will reduce. We can
have better control in fan in .
To handle multilevel logic implementation , we need to know different Boolean model known as
Boolean logic network.

Boolean logic network
a
b
c
x
y
a
b
c
x=ab
y=xc
Each bubble can take 2-level Boolean function in SOP form
Goal is to make DAG simpler and faster!!!
Internal vertices
Primary
inputs
Primary
outputs

Example: what to optimize? #literal count
• Given the following logic set:
t = a + bc;
t = d + e;
1
2
t = ab + d;
t = t t + fg;
t = t h + t t ;
F = t ’;
3
4 1 2
5 4 2 3
5
d+e
a+bc
t’
5
t t + fg
1 2
F
ab+d
t h + t t
4 2 3
17
Literals
Count each variable of each equation right hand side of “=“ sign (true
or complement form both

Three major steps:
Simplify network nodes: no change in number of bubbles, just simplify inside SOP,
• This is two level synthesis ESPRESSO!!
• a+ab+bc = a+bc
Remove network nodes: Remove too small nodes, take them to next node.
z=ab x=qz+.. x=qab+..
y=cdz+.. y=cdab+..
Add new networking nodes: Factoring!!, Take big/complex node- split into smaller nodes
• Try to find factors that can be used many times (common subexpression)

Q
Factoring:
X=pq+c+r
Y=pqd+cd
Z=pqrs+crs
Q=pq+c
X=Q r
Y=Q d
Z=Q rs
Q is divisor
Identify divisor, factor them, connect them as fan in
More delay, more level, but less literals 16-10

# Literal vs area
 By factoring number of literals reduced so
number of MOS, and area.
 Hence factoring is good choice for logic
minimization.
x=ac+bc+bd
(a+b)c+d
x=(a+b)c+d

Algebaric vs Boolean Division
Algebaric division: Use rule of Algebra (no Boolean Law can be used)
Boolean Division: Use rules of Boolean Algebra
F=ad+bcd+e
G=a+b (G does not divide F under Algebaric rule but divide using Boolean rule)
Q=F/G=(a+c)d
F=GQ+R= (a+b)(a+c)d+e=(aa+ac+ab+bc)d+e=(a+bc)d+e=ad+bcd+e

How to factor?- Boolean Algebraic
model
Boolean expressions behave like polynomials of real numbers
New operator : Algberic division (weak division)
Boolean Algebra:
a.b=b.a a+a’=1
a+b=b+a a.a=a
a.(b.c)=(a.b).c a+1=1;
a+(b+c)=(a+b)+c a+(b.c)=(a+b).(a+c)
a.(b+c)=(a.b)+(a.c)
a.1=a; a.0=0
a+0=a

Factoring
F= D.Q+R
• D=divisor, Q= Quotient, R=Reminder
• Example : X=ac+ad+bc+bd+e
Y=a+b ; Y =divisor
X/Y= c+d ; c+d= Quotient
X=(c+d) Y +e; e = reminder
 If reminder =0, we can say the Divisor as a factor
Different types of factor
 Cubes (easy) and Kernel (hard to find but
better factroing),


F=ac+ad+bc+bd+e; F=D.Q+R
Ex2: F=ad+bcd+e; D=a+b; Q=(a+c)d; R=e????
D Q R Is it factor?
ac+ad+bc+bd+e 1 0 yes
a+b c+d e no
c+d a+b e no
a c+d bc+bd+e no
e 1 ac+ad+bc+bd No

Example- cube method
F=axc+axd+axe+bc+bd+de D=ax+b, find Quotient and Reminder
F cube d cube (ax) d cube (b)
axc c --
axd d --
axe e --
bc -- c
bd -- d
de -- -
c+d+e c+d
Q=(c+d+e) ∩ (c+d)
Q=c+d
Reminder= F-Q.D
Q.D= (ax+b).(c+d)
= axc+axd+bc+bd
R= F-Q.D= axe+de

Caution1. : True and complement form of variable need to be treated different
Example: F=ab’c’+ab+ac+bc D=ab+c’
Substitute: x=b’c’, y =c’
Then, F= ax+ab+ac+bc, D= ab+y
Now you can proceed for F/D
Caution 2: F should not have any redundant cube;
Summary: For a signle F, and given D, we can find Q and R.
• In real time, many functions are there how to find a common factor?

Some definitions
Cube: product term
Literal: an instance of variable or its complement form ex. a+a’b has three literals
Prime implicant (cube): cube for which no literals can be removed
Essential implicant: Prime cube that must be used because there is a member on-set that no other
cube covers.
Kernel:
Cokernel:

synthesis_0501 in digital vlsi design.ppt

F=D.Q+R c.K+R, F=abc+abd+bcd
Many kernels!!!
in F

What to do with these kernels?
Brayton McMullen Theorem:
F and G have a common multiple cube divisor d iff
There are kernels K1 in F, K2 in G, such that d = K1∩K2 and d is expression with minimum 2 cubes.
Look at the intersection of their kernels. If you get the intersection, then the intersection is d only. If
you find more than 2 cubes, then done!! You got the common divisor for F and G.

Example
F=ae+be+cde+ab G=ad+ae+bd+be+bc

How to find kernel? Kernel algorithm
F=ace+bce+de+g
No more
processing
Because
only one
cube with
“a”
No more
processing
Because
only one
cube with
“b”
i. Cubes with “c”=
ace, bce
ii.Cokernel=“ce
iii. Divide F with
cofactor- Kernel
=“a+b” (only
quotient)
No more
processing
Because
only one
cube with
“d”
Cubes with
e=ace, bce,de
Co=e
Divide F with e
=ac+bc+d
(only quotient)
No more
processing
Because
only one
cube with
“g”
b c d
No more
work, no
common
variable
a
e
g
b c d
Cokernel= ce
Kernel= a+b

ac+bc+d
a
e
g
b
c d
No more
work, no
common
variable
No more
work, no
common
variable
Co=c
F/c= (a+b)
No more
work, no
common
variable
No more
work, no
common
variable
No more
work, no
common
variable
No more
work, no
common
variable
Cokernel= ce
(by ANDing all up tree)
Kernel= a+b

For a given two functions, F and G
When you are looking for single cube divisor “d”, look into co-kernels
When you are looking for multiple cube divisor “d”, look into kernels
F
G
d
F=d.Q1+R1
G=d.Q2+R2

Summary
Elaboration: converts RTL into Boolean Expression
Logic optimization- converts the Boolean into optimized Boolean expression
• Two level- ESPRESSO
• Multi level- Three operators- simplify, remove and Add
Add requires factoring
• Algebaric model
• Algebaric division
• Cube based
• Kernel based
• Recursive kernel algorithm to find divisor for multiple Boolean function.
Syntax
Analysis
Library
definition
Elaboration
& Binding Logic
optimization
Technology
mapping

Constraint Definition
Following Elaboration, the design
is loaded into the synthesis tool
and stored inside a data structure.
Logic optimization performed area
optimization
For timing analysis .SDC file
(constraint file) is input to the
synthesizer
read_sdc –verbose sdc/constraints.sdc

How a synthesized multi-level logic network gets turned into actual gate level netlist?
Technology mapping is the phase of logic synthesis when gates are selected from a technology library
to implement the circuit. – Actual gate level netlist
Why Technology mapping?
• Gates in the library are pre-designed, they are usually optimized in terms of area, delay, power, etc.
• Foundry specific
Basic Concept:
• During logic synthesis, map portions of the netlist to “cells” available in the cell library
• Standard library (NAND, NOR, NOT, AOI, etc)
Objectives:
• Minimize area, delay, power
• Should be fast
Technology mapping

Example: Library has inv, NAND gates only
F(a,b,c)=a’bc + abc + d
Logic synthesis: each vertex of MLS
bc + d
b
c
d
Technology mapping
b
c
d
Library will have same gate different characteristics in terms of speed, fanout;
Fastest gates along the critical path, area-efficient gates (combination) off the critical path
Technology
independent logic
Technology
dependent logic

Problem definition
Suppose library has the following gates
AND2 OR2 OA21
X=a+b
Z=dX
Y=cX
Map it to the gate level
netlist in terms of gates
available in library

Extension:
Now draw the gate level netlist file in terms of gates available in the library , with an optimized cost.
Report the cost!!! Cost may be associated with area or time
What is Technology mapping?
• Maps output of synthesis in technology independent form to gates available in library with optimized cost.
AND2: cost =3 OR2:cost 3 OA21: cost 5

Technology mapping algorithm
Using a recursive tree-covering algorithm, we can optimally, map a logic network to
a technology library. Logic network is a tree of simple gates.
It has three steps:
• 1. Map netlist and tech library to simple gates
• Describe the logic network (tech independent) in terms of 2input NAND and NOT gate
• Describe the library in terms of 2 input NAND and NOT gate , and the associated cost
Cover the tree with minimum cost set of gates from the library
• 2. Tree-ifying: split the trees with fanout >2
• 3. Minimum cost tree matching

Example- before MLS - unoptimized
Set of Boolean function to describe
the function F.
t1 = a + bc;
t2 = d + e;
t3 = ab + d;
t4 = t1t2 + fg;
t5 = t4h + t2t3;
F = t5’;
• Number of literals= 16
d+e
a+bc
t5’
t1t2 + fg
F
ab+d
t4h+ t2t3

Using technology independent optimization, these equations are optimized using
only 13 literals:
t1 = d + e;
t2 = b + h;
t3 = at2 + c;
t4 = t1t3 + fgh;
F = t4’;
d+e b+h
t4’
at2 +c
t1t3 + fgh
F

Step 1: Simple gate mapping
Apply De Morgan laws to your Boolean function to make it a collection of NAND2 and NOT gates.
t1
t2
t3
t4
(fgh)’
base

Implement this network using a set of gates which form a library. Each gate has a cost (i.e. its area, delay,
etc.)
We need to define the gates with the same NAND2/NOT set:
inv(1) nand3 (3)
nor2(2)
nor3 (3)
nand2(2)
aoi21 (3)
xor (5)
oai22 (4)

Tree-ifying
To apply a tree covering algorithm, we must work on a tree
Is any given logic network a tree?- No
We must break the tree at any node with fanout>2
We get 3 trees

Example
A B
C D
F
I
N
A
I N
N
B
C D
f
w
z
y
x
I N N
I N
I
I
I
N
I
N
I
NOT NAND2 AND2 NOR2 AOI21
6
6
4
3
2
f: NOT 2 + min(w) = 2 + 11 = 13
AND2 4 + min(y)+min(z) = 4 + 2 + 6 = 12
AOI21 6 + min(x) = 6 + 3 = 9
w: NAND2 3 + min(y)+min(z) = 3 + 2 + 6 = 11
y: NOT 2
z: NAND2 3 + min(x) = 3 + 3 = 6
x: NAND2 3
AOI21
NAND2

https://www.coursera.org/learn/vlsi-cad-logic by Rob Rutenbar

Timing Optimization
Post mapping/ Timing
Optimization
RTL development
Technology maping
Partition
RTL integration & Const.
check
Translation
Logic Optimization
Timing analysis
Remapping of cell
Change in circuit
Correction in constraints
Repartitioning of RTL
Change in logic
Y
Pass

synthesis_0501 in digital vlsi design.ppt

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