SPICE MODEL of TC74ACT245F in SPICE PARK
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The document is a device modeling report for the CMOS digital integrated circuit part number TC74ACT245F, manufactured by Toshiba Bee Technologies Inc. It includes truth tables, circuit simulation results, timing evaluations, and performance measurement data, detailing various operational characteristics and performance metrics of the device. Copyright information is also noted, indicating the document is owned by Bee Technologies Inc. from 2005.
SPICE MODEL of TC74ACT245F in SPICE PARK
- 1. Device Modeling Report COMPONENTS : CMOS DIGITAL INTEGRATED CIRCUIT PART NUMBER : TC74ACT245F MANUFACTURER : TOSHIBA Bee Technologies Inc. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 2. Truth Table Circuit simulation result U1:GBAR 0 U1:DIR 0 U1:B1 1 U1:B2 1 U1:B3 1 U1:B4 1 U1:B5 1 U1:B6 1 U1:B7 1 U1:B8 1 U1:A1 1 U1:A2 1 U1:A3 1 U1:A4 1 U1:A5 1 U1:A6 1 U1:A7 1 U1:A8 1 0s 0.5us 1.0us Time Evaluation circuit U1 DIR VCC LO __ A1 G LO A2 B1 IN_B A3 B2 A4 B3 A5 B4 R1 V1 A6 B5 1MEG A7 B6 DSTM1 5 A8 B7 CLK GND B8 ONTIME = .2uS OFFTIME = .2uS 74ACT245 0 Comparison table Function : A BUS = OUTPUT, B BUS = INPUT Input Output %Error G DIR Measurement Simulation L L A=B A=B 0 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 3. Truth Table Circuit simulation result U1:GBAR 0 U1:DIR 1 U1:A1 1 U1:A2 1 U1:A3 1 U1:A4 1 U1:A5 1 U1:A6 1 U1:A7 1 U1:A8 1 U1:B1 1 U1:B2 1 U1:B3 1 U1:B4 1 U1:B5 1 U1:B6 1 U1:B7 1 U1:B8 1 0s 0.5us 1.0us Time Evaluation circuit U1 HI DIR VCC __ A1 G IN_A LO A2 B1 A3 B2 A4 B3 A5 B4 R1 V1 A6 B5 1MEG CLK A7 B6 5 DSTM1 A8 B7 ONTIME = .2uS OFFTIME = .2uS GND B8 74ACT245 0 Comparison table Function : A BUS = INPUT, B BUS = OUTPUT Input Output %Error G DIR Measurement Simulation L H B=A B=A 0 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 4. Truth Table Circuit simulation result U1:GBAR 1 U1:DIR 1 U1:A1 Z U1:A2 Z U1:A3 Z U1:A4 Z U1:A5 Z U1:A6 Z U1:A7 Z U1:A8 Z U1:B1 Z U1:B2 Z U1:B3 Z U1:B4 Z U1:B5 Z U1:B6 Z U1:B7 Z U1:B8 Z 0s 0.5us 1.0us Time Evaluation circuit U1 DSTM1 CLK DIR VCC __ ONTIME = .2uS A1 G HI OFFTIME = .2uS A2 B1 A3 B2 A4 B3 A5 B4 R1 V1 A6 B5 1MEG A7 B6 5 A8 B7 GND B8 74ACT245 0 Comparison table Function : A BUS and B BUS = HIGH IMPEDANCE Input Output %Error G DIR Measurement Simulation H X Z Z 0 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 5. High Level and Low Level Input Voltage Circuit simulation result 5.0V (540.006u,2.0003) Output 2.5V Input (515.983u,799.166m) 0V 0s 0.5ms 1.0ms 1.5ms 2.0ms V(OUT) V(V1:+) Time Evaluation circuit U2 DIR VCC LO __ A1 G OUT LO A2 B1 A3 B2 A4 B3 V2 A5 B4 V1 = 0 R2 A6 B5 V2 = 5 V1 5 TD = 0.5m 1G A7 B6 TR = 0.1m TF = 0.1m A8 B7 PW = 1m PER = 2m GND B8 74ACT245 0 Comparison table VCC = 5V Measurement Simulation %Error VIH (V) 2 2 0 VIL (V) 0.8 0.799166 -0.104 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 6. High Level and Low Level Output Voltage Circuit simulation result 5.0V 2.5V Output SEL>> 0V Input V(OUT) 5.0V 2.5V 0V 0s 5ms 10ms V(V1:+) Time Evaluation circuit U1 DIR VCC LO __ A1 G OUT LO A2 B1 A3 B2 A4 B3 V2 A5 B4 V1 = 0 R1 A6 B5 V2 = 4.5 V1 4.5 TD = 0.5m 0.09MEG A7 B6 TR = 3n TF = 3n A8 B7 PW = 1m PER = 2m GND B8 74ACT245 0 Comparison table VCC = 4.5V Measurement Simulation %Error VOH (V) 4.5 4.4987 -0.029 VOL (V) 0 0 0 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 7. Propagation Delay Time Circuit simulation result 5.0V 3.0V 1 2 Output Input 2.5V 1.5V >> 0V 0V 0s 0.5us 1.0us 1 V(TPLH_TPHL) 2 V(U1:B1) Time Evaluation circuit U1 DIR VCC LO tplh_tphl __ A1 G LO A2 B1 A3 B2 A4 B3 V2 A5 B4 R1 C1 V1 = 0 A6 B5 V2 = 3 5 500 50p TD = 0.2u V1 A7 B6 TR = 3.8n TF = 3.8n A8 B7 PW = 0.5u PER = 1u GND B8 74ACT245 0 Comparison table CL = 50 pF, RL = 500 tr = tf =3 ns Measurement Simulation %Error tPLH (ns) 5 5.0128 0.256 tPHL (ns) 5 5.014 0.280 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 8. Output enable time, high impedance (off) to high output (tPZH) Output disable time, high to high impedance (off) output (tPHZ) Circuit simulation result 5.0V 3.0V 1 2 Output Input 2.0V 2.5V 1.0V >> 0V 0V 0s 0.5us 1.0us 1 V(TPZH_TPHZ) 2 V(U1:GBAR) Time Evaluation circuit U1 DIR VCC LO tpzh_tphz __ A1 G A2 B1 HI A3 B2 A4 B3 V2 A5 B4 R2 R1 C1 V1 = 0 V1 A6 B5 V2 = 3 5 500 500 50p TD = 0.2u A7 B6 TR = 3.8n TF = 3.8n A8 B7 PW = 0.5u PER = 1u GND B8 74ACT245 0 Comparison table CL = 50 pF, RL = 500 tr = tf =3 ns Measurement Simulation %Error tPZH (ns) 7.3 7.3756 1.036 tPHZ (ns) 6.3 6.3548 0.870 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 9. Output enable time, high impedance (off) to low output (tPZL) Output disable time, low to high impedance (off) output (tPLZ) Circuit simulation result 5.0V 3.0V 1 2 Output Input 2.5V 1.5V >> 0V 0V 0s 0.5us 1.0us 1 V(TPZL_TPLZ) 2 V(V1:+) Time Evaluation circuit U1 DIR VCC LO R2 tpzl_tplz __ A1 G 500 A2 B1 LO A3 B2 A4 B3 V2 R1 C1 A5 B4 V3 V1 = 0 V1 500 50p A6 B5 V2 = 3 10 TD = 0.2u A7 B6 TR = 3.8n 5 TF = 3.8n A8 B7 PW = 0.5u PER = 1u GND B8 74ACT245 0 Comparison table CL = 50 pF, RL = 500 tr = tf =3 ns Measurement Simulation %Error tPZL (ns) 7.3 7.3644 0.882 tPLZ (ns) 6.3 6.3547 0.868 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005