Testing ddr memory with ict
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This document discusses challenges in testing DDR memory and provides recommendations. It notes complexity in memory instructions, high data rates, differences between manufacturers, and lack of direct access. It recommends testing just the data strobes first without writing or reading, disabling the DLL to run at low speed, using boundary scan if no direct access, and employing dual stage fixturing to minimize clock noise. The document also discusses test modes that simplify testing and the importance of direct clock access even in test modes.
Testing ddr memory with ict
- 1. Testing DDR memory with ICT
- 2. Problems Complexity High data rates Differences between manufacturers Lack of access
- 3. Complexity Many instructions needed before the device can be Written to or Read from. CK/CK_bar crosspoint needs to be set carefully using a dedicated logic family for the clock pins. Burst modes need to be understood, writing 0xA to location 0 and then 0x5 to location 1 is pointless.
- 5. High Data Rates Devices may have a Minimum speed Can be overridden by disabling DLL Sometimes get unpredictable behaviour
- 6. Differences between manufacturers Samsung may support CAS Latency (CL) of 2,3,4 Hynix may support CAS Latency (CL) of 3,4,5
- 7. Lack of access Use Bscan but need access to clocks otherwise long test times and long compilation times. Long refresh times mean data can be lost. Problem with noise on clocks.
- 8. Test Development Process and Debug Methodology DQS testing DLL disabling Silicon Nail testing (Boundary Scan). Dual stage fixturing Test modes
- 9. DQS testing DQS (if available) always works. The device does not need any data written to it. The device should be setup via the mode registers. A read command can then be issued and just the DQS pins checked. This allows the engineer to verify that the Mode register programming is working, before trying to write and read from the device.
- 11. DLL Disabling If the DLL is enabled then the device may have a minimum clock speed which precludes it being tested at ICT. Some devices allow the disabling of the DLL to allow the device to run at low speed. DLL disabling may cause odd behaviour of the device’s CAS latency which may or may not be documented.
- 13. Silicon nail testing If there is no access then Silicon nails can be used BUT depending on scan chain length data may be lost. The memory needs to be refreshed on a minimum time interval, if this interval is exceeded then the memory will forget what was programmed. Try testing the data strobe instead as this a logic function of the part, not a memory function Sometimes Data strobes are not used/not available.
- 14. Silicon nail testing cont’d Direct access to clocks is very useful as without it compile times and run times can be excessive, resulting in a lack of the will to live on behalf of the test engineer. A 20 minute compile time is NOT conducive to test debug. If the clocks are accessible then in a conventional fixture they can be subject to noise from other parts of the board such as switched mode power supplies, resulting in an intermittent test.
- 15. Dual stage fixturing Directly clocking the device may result in intermittent tests caused by the clock probes being affected by noise from other parts of the board, such as switched mode power supplies. If clocking the device directly consider using a dual stage fixture to minimize noise on the clocks.
- 16. Test modes Some GDDR3 devices have a Jedec defined test mode. This test mode converts the device’s IO pins to a parallel in, serial out shift register. This greatly simplifies test development and debug. It is still important to have direct access to the clock input of the shift register when the device is in its test mode. This is NOT the same as the memory clock input. Dual stage fixtures are beneficial to eliminate noise on this clock input.
- 19. Test modes continued New IEEE standard for test modes on memories. P1581
- 20. Memory Test Development If you have multiple device manufacturers and no way of knowing what’s loaded on the board then don’t even start. If limited access get access to the clocks, if only for debug. Disable the DLL so you can run at low speed Just test the data strobes, don’t worry about writing and reading yet. If the device has a test mode, use it.