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SOFICS © 2020 Proprietary & Confidential 8
65nm SOI
Diode perimeter: 80um
~9-10mA/um
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65nm Bulk
Diode perimeter: 92um
~33mA/um](https://image.slidesharecdn.com/2020-03soficstalk-esd-fdsoi-200421082319/85/Optimizing-I-O-s-and-ESD-protection-to-reduce-power-consumption-in-SOI-applications-8-320.jpg)
![Diode – Reverse Leakage
SOFICS © 2020 Proprietary & Confidential 9
• Reverse diode are low leakage
– Measured in 65nm bulk
– Similar for all technologies
• Leakage @ 1.8V
– ~10pA for 25°C
– ~200pA for 125°C
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induced noise
1.8V](https://image.slidesharecdn.com/2020-03soficstalk-esd-fdsoi-200421082319/85/Optimizing-I-O-s-and-ESD-protection-to-reduce-power-consumption-in-SOI-applications-9-320.jpg)
![GGNMOS Measurements
SOFICS © 2020 Proprietary & Confidential slide 16
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It2 ~ 6 mA/um
• Bulk NMOS much higher It2
– Bulk: 5-10 mA/um
– SOI: 1-3 mA/um
• Voltages comparable
– SOI devices slightly lower trigger and holding voltage
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90nm SOI process
It2 ~ 2.4 mA/um](https://image.slidesharecdn.com/2020-03soficstalk-esd-fdsoi-200421082319/85/Optimizing-I-O-s-and-ESD-protection-to-reduce-power-consumption-in-SOI-applications-16-320.jpg)
![Protection Device Example (1/3) – 1.2V in 90nm SOI
Proprietary & Confidential -- Sarnoff © 2005 slide 22
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W=8x30um
Vt1 = 3.2V
• SCR based power clamp in SOI
– Vhold = 2V
– Vmax = 6.4V
– Imax=7.5 mA/um
– Ron = 586.7 Ohm.um
• Leakage ~ 0.5nA/um @ 25°C](https://image.slidesharecdn.com/2020-03soficstalk-esd-fdsoi-200421082319/85/Optimizing-I-O-s-and-ESD-protection-to-reduce-power-consumption-in-SOI-applications-22-320.jpg)
Optimizing I/O’s and ESD protection to reduce power consumption in SOI applications
- 1. SOFICS © 2020 Proprietary & Confidential 1 BENJAMIN VAN CAMP -SOFICS OPTIMIZING I/O’S AND ESD PROTECTION TO REDUCE POWER CONSUMPTION IN SOI APPLICATIONS D&R IP-SOC DAYS
- 2. An IC through the eyes of an ESD engineer SOFICS © 2020 Proprietary & Confidential 2 GND VDD Output Input
- 3. I/O ESD architectures SOFICS © 2020 Proprietary & Confidential 3 Leakage I/O to GND Leakage I/O to VDD Leakage VDD to GND VDD GND I/O
- 4. I/O ESD architectures SOFICS © 2020 Proprietary & Confidential 4 … Leakage I/O to GND Leakage I/O to VDD Leakage VDD to GND VDD GND I/O VDD GND I/O VDD GND I/O VDD GND I/O
- 5. Dual diode Protection SOFICS © 2020 Proprietary & Confidential 5 • ESD protection implications – Simplest architecture – For large design windows • Signal voltage implications – VI/O > GND - 0.3V – VI/O < VDD + 0.3V • Leakage – I/O - > GND: Through reverse junction of diode – I/O - > VDD: Through reverse junction of diode – VDD -> GND: Determined by power clamp VDD GND I/O Leakage I/O to GND Leakage I/O to VDD Leakage VDD to GND
- 6. Diode Cross Sections SOFICS © 2020 Proprietary & Confidential 6 Bulk SOI STI diode Gated Diode
- 7. Diode characteristics SOFICS © 2020 Proprietary & Confidential 7 • Current capability: – Forward: 20-50mA/um – Reverse: 0.5mA/um • Parasitics – PNP to substrate – Diode from substrate to cathode • Current capability: – Forward: 5-10mA/um – Reverse: 0.2mA/um • No Parasitics Bulk SOI
- 8. 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0 1 2 3 4 5 Voltage [V] Current [A] Diode measurements SOFICS © 2020 Proprietary & Confidential 8 65nm SOI Diode perimeter: 80um ~9-10mA/um 0 0.5 1 1.5 2 2.5 3 3.5 0 0.5 1 1.5 2 2.5 3 Voltage [V] Current [A] 65nm Bulk Diode perimeter: 92um ~33mA/um
- 9. Diode – Reverse Leakage SOFICS © 2020 Proprietary & Confidential 9 • Reverse diode are low leakage – Measured in 65nm bulk – Similar for all technologies • Leakage @ 1.8V – ~10pA for 25°C – ~200pA for 125°C 10 -12 10 -10 10 -8 10 -6 10 -4 0 2 4 6 8 10 12 14 16 Voltage [V] Current [A] 25°C 125°C Thermochuck induced noise 1.8V
- 10. I/O ESD architectures SOFICS © 2020 Proprietary & Confidential 10 … Leakage I/O to GND Leakage I/O to VDD Leakage VDD to GND VDD GND I/O VDD GND I/O VDD GND I/O VDD GND I/O
- 11. Secondary Protection SOFICS © 2020 Proprietary & Confidential 11 • ESD protection implications – Simple architecture Diodes take most of ESD current Secondary protection limits voltage – Secondary protection can be small – For smaller design windows – CDM sensitive pins • Signal voltage implications – VI/O > GND - 0.3V – VI/O < VDD + 0.3V Leakage I/O to GND Leakage I/O to VDD VDD GND I/O Leakage VDD to GND
- 12. Secondary Protection SOFICS © 2020 Proprietary & Confidential 12 • Leakage 1. I/O - > GND: Path 1: Through reverse junction of diode Path 2: Through Secondary clamp -> Assume small ggNMOS 2. I/O - > VDD: Path 1: Through reverse junction of diode Path 2: Through Secondary clamp -> Assume small ggNMOS 3. VDD -> GND: Determined by power clamp + Sum of secondary clamps Typically negligible Leakage I/O to GND Leakage I/O to VDD Leakage VDD to GND VDD GND I/O
- 13. NMOS in Snapback – one slide explanation SOFICS © 2020 Proprietary & Confidential 13 1. Gate Grounded – Voltage increases – No current flow 2. Breakdown voltage drain-substrate reached – Avalanching at drain – Small current flow from drain to GND 3. Voltage built up over substrate resistance – Substrate- Source reaches 0.7V – NPN turns on – Avalanching voltage lowered Snapback I V I V I V 1 2 3
- 14. NMOS in bulk technology – cross section SOFICS © 2020 Proprietary & Confidential 14 • NMOS in bulk technology has a shared p-substrate – Large volume for Heat dissipation – This shared p-substrate will help to trigger all the fingers
- 15. SOI MOS SOFICS © 2020 Proprietary & Confidential slide 15 • SOI MOS – Less volume for heat dissipation – Body regions are isolated No body coupling between fingers A A’
- 16. GGNMOS Measurements SOFICS © 2020 Proprietary & Confidential slide 16 0 0.5 1 1.5 2 2.5 0 1 2 3 4 5 6 current [A] voltage [V] 90nm bulk process It2 ~ 6 mA/um • Bulk NMOS much higher It2 – Bulk: 5-10 mA/um – SOI: 1-3 mA/um • Voltages comparable – SOI devices slightly lower trigger and holding voltage 0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5 3 3.5 4 current [A] voltage [V] 90nm SOI process It2 ~ 2.4 mA/um
- 17. SOI MOS devices - Degradation SOFICS © 2020 Proprietary & Confidential 17 • Often degradation is seen – Don’t use these devices Factor 10 ESD SOI MOS Seen in many MOS devices in SOI
- 18. SOI MOS Variation SOFICS © 2020 Proprietary & Confidential 18 130nm SOI Foundry ESD Solution Measured over multiple samples Leakage ~few nA or lower
- 19. I/O ESD architectures SOFICS © 2020 Proprietary & Confidential 19 … Leakage I/O to GND Leakage I/O to VDD Leakage VDD to GND VDD GND I/O VDD GND I/O VDD GND I/O VDD GND I/O
- 20. I/O signal conditions SOFICS © 2020 Proprietary & Confidential 20 • ESD protection implications – Local Clamp required Takes all of ESD current Needs to limit voltage – Local clamp large – For smallest design windows – CDM sensitive pins • Local clamp options – ggNMOS – SCR Leakage I/O to GND Leakage I/O to VDD Leakage VDD to GND VDD GND I/O
- 21. I/O signal conditions SOFICS © 2020 Proprietary & Confidential 21 • Conditions that require (semi) local protection – VI/O > VDD + 0.3V – Supply can be powered down Energy Saving mode Cold Spare – CMRR: no I/O – VDD capacitance allowed • Leakage 1. I/O - > GND: Path 1: Through reverse junction of diode Path 2: Through local clamp 2. I/O - > VDD: None 3. VDD -> GND: Determined by power clamp Leakage I/O to GND Leakage I/O to VDD Leakage VDD to GND VDD GND I/O
- 22. Protection Device Example (1/3) – 1.2V in 90nm SOI Proprietary & Confidential -- Sarnoff © 2005 slide 22 0 0.5 1 1.5 2 0 1 2 3 4 5 6 7 10 -12 10 -11 10 -10 10 -9 10 -8 10 -7 10 -6 voltage [V] leakage current [A] @ 1.32V current[A] W=8x30um Vt1 = 3.2V • SCR based power clamp in SOI – Vhold = 2V – Vmax = 6.4V – Imax=7.5 mA/um – Ron = 586.7 Ohm.um • Leakage ~ 0.5nA/um @ 25°C
- 23. Protection Device Example (2/3) - 22nm SOI SOFICS © 2020 Proprietary & Confidential 23 • SCR Based clamps for different domains 1.2V-1.8V – 125°C 0.8V - 125°C 0.8V – 25°C 1.2V-1.8V –25°C Leakage ESD performance
- 24. Protection Device Example (3/3) - 3.3V in 130nm SOI SOFICS © 2020 Proprietary & Confidential 24 • Specialized ggNMOS based clamp – To lower leakage – To avoid variation 11nA, FF, 125°C 200pA, TT, 25°C same process
- 25. I/O ESD architectures SOFICS © 2020 Proprietary & Confidential 25 … Leakage I/O to GND Leakage I/O to VDD Leakage VDD to GND VDD GND I/O VDD GND I/O VDD GND I/O VDD GND I/O
- 26. Power protection - Leakage SOFICS © 2020 Proprietary & Confidential 26 • Choice of power clamp is important – Dependent on leakage/power specifications – Dependent on power up/down strategy – Dependent on temperature range 22nm SOI Clamp type 25°C 125°C 0.8V Rail clamp 80nA 6uA 1.8V Rail clamp 100nA uA 0.8V SCR based <0.5nA 20nA 1.8V SCR based <0.5nA 20nA 0.8V ggNMOS 2nA 1.8V ggNMOS 10nA Leakage VDD to GND VDD GND I/O
- 27. Conclusion - Leakage SOFICS © 2020 Proprietary & Confidential 27 • I/O to GND – Low leakage • I/O to VDD – Low leakage IF Vsignal < VDD at all times • VDD to I/O – Depends on power clamp – < 1nA @ RT possible • I/O to GND – Depends on local clamp – < 1nA @ RT possible • I/O to VDD – Low leakage IF Vsignal < VDD at all times • VDD to I/O – Depends on power clamp – < 1nA @ RT possible • I/O to GND – Depends on local clamp – < 1nA @ RT possible • I/O to VDD – Low leakage IF Vsignal < VDD at all times • VDD to I/O – Depends on power clamp – < 1nA @ RT possible VDD GND I/O VDD GND I/O VDD GND I/O
- 28. Contact us SOFICS © 2019 Proprietary & Confidential 28 • Sofics contact Koen Verhaege Benjamin Van Camp Bart Keppens info@sofics.com engineering office Sint-Godelievestraat 32 9880 Aalter, Belgium