testing purpose for ic testing and othettastinng

SN65HVD0x, SN75HVD0x High Output RS-485 Transceivers
1 Features
• Minimum differential output voltage of 2.5 V Into a
54-Ω load
• Open-circuit, short-circuit, and idle-bus failsafe
receiver
• 1/8th Unit-load option available (Up to 256 nodes
on the bus)
• Bus-pin ESD protection exceeds 16 kV HBM
• Driver output slew rate control options
• Electrically compatible with ANSI TIA/EIA-485-A
standard
• Low-current standby mode: 1 µA typical
• Glitch-free power-up and power-down
protection for hot-plugging applications
• Pin compatible with industry standard SN75176
2 Applications
• Data transmission over long or lossy lines or
electrically noisy environments
• Profibus line interface
• Industrial process control networks
• Point-of-sale (POS) networks
• Electric utility metering
• Building automation
• Digital motor control
3 Description
The SN65HVD05, SN75HVD05, SN65HVD06,
SN75HVD06, SN65HVD07, and SN75HVD07
combine a 3-state differential line driver and
differential line receiver. They are designed for
balanced data transmission and interoperate with
ANSI TIA/EIA-485-A and ISO 8482E standard-
compliant devices. The driver is designed to provide
a differential output voltage greater than that required
by these standards for increased noise margin. The
drivers and receivers have active-high and active-
low enables respectively, which can be externally
connected together to function as direction control.
The driver differential outputs and receiver differential
inputs connect internally to form a differential input/
output (I/O) bus port that is designed to offer minimum
loading to the bus whenever the driver is disabled or
not powered. These devices feature wide positive and
negative common-mode voltage ranges, making them
suitable for party-line applications.
1
2
3
4
8
7
6
5
R
RE
DE
D
VCC
B
A
GND
D OR P PACKAGE
(TOP VIEW)
Figure 3-1. Differential Output Voltage vs
Differential Output Current
1
2
3
4
6
7
A
B
R
RE
DE
D
LOGIC DIAGRAM
(POSITIVE LOGIC)
SN75HVD05, SN75HVD06, SN75HVD07
SLLS533F – MAY 2002 – REVISED MARCH 2023
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Specifications.................................................................. 3
5.1 Absolute Maximum Ratings........................................ 3
5.2 Recommended Operating Conditions.........................3
5.3 Thermal Information....................................................4
5.4 Package Dissipation Ratings...................................... 4
5.5 Driver Electrical Characteristics..................................5
5.6 Driver Switching Characteristics................................. 6
5.7 Receiver Electrical Characteristics............................. 7
5.8 Receiver Switching Characteristics.............................8
5.9 Typical Characteristics................................................9
Parameter Measurement Information.............................12
6 Function Tables............................................................. 16
6.1 Receiver Failsafe...................................................... 16
7 Equivalent Input and Output Schematic Diagrams....17
8 Application and Implementation..................................18
Typical Application.......................................................... 18
9 Device and Documentation Support............................19
9.1 Receiving Notification of Documentation Updates....19
9.2 Support Resources................................................... 19
9.3 Trademarks...............................................................19
9.4 Electrostatic Discharge Caution................................19
9.5 Glossary....................................................................19
10 Mechanical, Packaging, and Orderable
Information.................................................................... 19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (August 2009) to Revision F (March 2023) Page
• Deleted the Ordering Information table...............................................................................................................1
• Added the Thermal Information table................................................................................................................. 4
• Changed the Typical Characteristics ................................................................................................................. 9
Changes from Revision D (July 2006) to Revision E (August 2009) Page
• Added IDLE Bus to the Receivers Function Table............................................................................................16
• Added the Receiver Failsafe paragraph........................................................................................................... 16
SLLS533F – MAY 2002 – REVISED MARCH 2023 www.ti.com
2 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated
Product Folder Links: SN75HVD05 SN75HVD06 SN75HVD07 SN65HVD05 SN65HVD06 SN65HVD07

5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range unless otherwise noted(1) (2)
Supply voltage range, VCC –0.3 V to 6 V
Voltage range at A or B –9 V to 14 V
Input voltage range at D, DE, R or RE –0.5 V to VCC + 0.5 V
Voltage input range, transient pulse, A and B, through 100 Ω (see Figure 6-11) –50 V to 50 V
Receiver output current, IO –11 mA to 11mA
Electrostatic discharge
Human body model(3)
A, B, and GND 16 kV
All pins 4 kV
Charged-device model(4) All pins 1 kV
Continuous total power dissipation See Dissipation Rating Table
(1) Stresses beyond those listed under "absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under" recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A.
(4) Tested in accordance with JEDEC Standard 22, Test Method C101.
5.2 Recommended Operating Conditions
MIN NOM MAX UNIT
Supply voltage, VCC 4.5 5.5 V
Voltage at any bus terminal (separately or common mode) VI or VIC –7(1) 12 V
High-level input voltage, VIH D, DE, RE 2 V
Low-level input voltage, VIL D, DE, RE 0.8 V
Differential input voltage, VID (see Figure 6-7) –12 12 V
High-level output current, IOH
Driver –100
mA
Receiver –8
Low-level output current, IOL
Driver 100
mA
Receiver 8
Operating free-air temperature, TA
SN65HVD05
–40 85 °C
SN65HVD06
SN65HVD07
SN75HVD05
0 70 °C
SN75HVD06
SN75HVD07
(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
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Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3

5.3 Thermal Information
THERMAL METRIC(1)
D (SOIC)
SN65
Variation
D (SOIC)
SN75
Variation
P (PDIP)
UNIT
8 PINS 8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 116.7 175.4 125 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 56.3 53.6 34.9 °C/W
RθJB Junction-to-board thermal resistance 63.4 45.1 23.7 °C/W
ψJT Junction-to-top characterization parameter 8.8 10.1 12.1 °C/W
ψJB Junction-to-board characterization parameter 62.6 44.4 23.6 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
5.4 Package Dissipation Ratings
(See Figure 5-1 and Figure 5-2)
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR(1)
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
D(2) 710 mW 5.7 mW/°C 455 mW 369 mW
D(3) 1282 mW 10.3 mW/°C 821 mW 667 mW
P 1000 mW 8.0 m W/°C 640 mW 520 mW
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
(2) Tested in accordance with the Low-K thermal metric definitions of EIA/JESD51-3
(3) Tested in accordance with the High-K thermal metric definitions of EIA/JESD51-7

5.5 Driver Electrical Characteristics
over operating free-air temperature range unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
VIK Input clamp voltage II = –18 mA –1.5 V
|VOD| Differential output voltage
No Load VCC
V
RL = 54 Ω, See Figure 6-4 2.5
Vtest = –7 V to 12 V, See Figure 6-2 2.2
Δ|VOD|
Change in magnitude of differential output
voltage
See Figure 6-4 and Figure 6-2 –0.2 0.2 V
VOC(SS) Steady-state common-mode output voltage
See Figure 6-3
2.2 3.3 V
ΔVOC(SS)
Change in steady-state common-mode
output voltage
–0.1 0.1 V
VOC(PP)
Peak-to-peak common-mode
output voltage
HVD05
See Figure 6-3
600
mV
HVD06 500
HVD07 900
IOZ High-impedance output current See receiver input currents
II Input current
D –100 0
μA
DE 0 100
IOS Short-circuit output current –7 V ≤ VO ≤ 12 V –250 250 mA
C(diff) Differential output capacitance VID = 0.4 sin (4E6πt) + 0.5 V, DE at 0 V 16 pF
ICC Supply current
RE at VCC,
D and DE at VCC,
No load
Receiver disabled
and driver enabled
9 15 mA
RE at VCC,
D at VCC DE at 0 V,
No load
Receiver disabled
and driver disabled
(standby)
1 5 μA
RE at 0 V,
D and DE at VCC,
No load
Receiver enabled
and driver enabled
9 15 mA
(1) All typical values are at 25°C and with a 5-V supply.
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5.6 Driver Switching Characteristics
tPLH Propagation delay time, low-to-high-level output
HVD05
RL = 54 Ω, CL = 50 pF,
See Figure 6-4
6.5 11
ns
HVD06 27 40
HVD07 250 400
tPHL Propagation delay time, high-to-low-level output
HVD05 6.5 11
ns
HVD06 27 40
HVD07 250 400
tr Differential output signal rise time
HVD05 2.7 3.6 6
ns
HVD06 18 28 55
HVD07 150 300 450
tf Differential output signal fall time
HVD05 2.7 3.6 6
ns
HVD06 18 28 55
HVD07 150 300 450
tsk(p) Pulse skew (|tPHL - tPLH|)
HVD05 2
ns
HVD06 2.5
HVD07 10
tsk(pp)
(2) Part-to-part skew
HVD05 3.5
ns
HVD06 14
HVD07 100
tPZH1
Propagation delay time, high-impedance-to-high-
level output
HVD05
RE at 0 V, RL = 110 Ω,
See Figure 6-5
25
ns
HVD06 45
HVD07 250
tPHZ
Propagation delay time, high-level-to-high-
impedance output
HVD05 25
ns
HVD06 60
HVD07 250
tPZL1
Propagation delay time, high-impedance-to-low-level
output
HVD05
RE at 0 V, RL = 110 Ω,
See Figure 6-6
15
ns
HVD06 45
HVD07 200
tPLZ
Propagation delay time, low-level-to-high-impedance
output
HVD05 14
ns
HVD06 90
HVD07 550
tPZH2 Propagation delay time, standby-to-high-level output
RL = 110Ω , RE at 3 V,
See Figure 6-5
6 μs
tPZL2 Propagation delay time, standby-to-low-level output
RL = 110 Ω, RE at 3 V,
See Figure 6-6
6 μs
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.

5.7 Receiver Electrical Characteristics
VIT+
Positive-going input
threshold voltage
IO = –8 mA –0.01
V
VIT-
Negative-going input
threshold voltage
IO = 8 mA –0.2
Vhys
Hysteresis voltage
(VIT+ - VIT-)
35 mV
VIK Enable-input clamp voltage II = –18 mA –1.5 V
VOH High-level output voltage VID = 200 mV, IOH = –8 mA, See Figure 6-7 4 V
VOL Low-level output voltage VID = -200 mV, IOL = 8 mA, See Figure 6-7 0.4 V
IOZ
High-impedance-state
output current
VO = 0 or VCC RE at VCC –1 1 μA
II Bus input current
HVD05 Other inputat 0 V
VA or VB = 12 V 0.23 0.5
mA
VA or VB = 12 V, VCC = 0 V 0.3 0.5
VA or VB = –7 V –0.4 0.13
VA or VB = –7 V, VCC = 0 V –0.4 0.15
HVD06
HVD07
Other inputat 0 V
VA or VB = 12 V 0.06 0.1
mA
VA or VB = 12 V, VCC = 0 V 0.08 0.13
VA or VB = –7 V –0.1 0.05
VA or VB = –7 V, VCC = 0 V –0.05 0.03
IIH High-level input current, RE VIH = 2 V –60 26.4 μA
IIL Low-level input current, RE VIL = 0.8 V –60 27.4 μA
C(diff)
Differential input
capacitance
VI = 0.4 sin (4E6πt) + 0.5 V, DE at 0 V 16 pF
ICC Supply current
RE at 0 V, D and DE at
0 V, No load
Receiver enabled and driver disabled 5 10 mA
RE at VCC, DE at 0 V,
D at VCC, No load
Receiver disabled and driver disabled
(standby)
1 5 μA
RE at 0 V,
D and DE at VCC,
No load
Receiver enabled and driver enabled 9 15 mA
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5.8 Receiver Switching Characteristics
tPLH Propagation delay time, low-to-high-level output 1/2 UL HVD05
VID = –1.5 V to 1.5 V,
CL = 15 pF,
See Figure 6-8
14.6 25 ns
tPHL Propagation delay time, high-to-low-level output 1/2 UL HVD05 14.6 25 ns
tPLH Propagation delay time, low-to-high-level output 1/8 UL
HVD06 55 70
ns
HVD07 55 70
tPHL Propagation delay time, high-to-low-level output 1/8 UL
HVD06 55 70
ns
HVD07 55 70
tsk(p) Pulse skew (|tPHL – tPLH|)
HVD05 2
ns
HVD06 4.5
HVD07 4.5
tsk(pp)
(2) Part-to-part skew
HVD05 6.5
ns
HVD06 14
HVD07 14
tr Output signal rise time CL = 15 pF,
See Figure 6-8
2 3
ns
tf Output signal fall time 2 3
tPZH1 Output enable time to high level
CL = 15 pF,
DE at 3 V,
See Figure 6-9
10
ns
tPZL1 Output enable time to low level 10
tPHZ Output disable time from high level 15
tPLZ Output disable time from low level 15
tPZH2 Propagation delay time, standby-to-high-level output CL = 15 pF, DE at 0,
See Figure 6-10
6
μs
tPZL2 Propagation delay time, standby-to-low-level output 6
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.

5.9 Typical Characteristics
Figure 5-1. HVD05 Maximum Recommended Still-Air Operating
Temperature vs Signaling Rate (D-Package)
Figure 5-2. HVD06 Maximum Recommended Still-Air Operating
Temperature vs Signaling Rate (D-Package)
Figure 5-3. HVD05 RMS Supply Current vs Signaling Rate
Figure 5-4. HVD06 RMS Supply Current vs Signaling Rate
Figure 5-5. HVD07 RMS Supply Current vs Signaling Rate Figure 5-6. BUS Input Current vs BUS Input Voltage
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5.9 Typical Characteristics (continued)
Figure 5-7. Driver High-Level Output Current vs High-Level
Output Voltage
Figure 5-8. Driver Low-Level Output Current vs Low-Level
Output Voltage
Figure 5-9. Differential Output Voltage vs Free-Air Temperature
Figure 5-10. Driver Output Current vs Supply Voltage
Figure 5-11. Differential Output Voltage vs Differential Output
Current
Figure 5-12. Enable Time vs Common-Mode Voltage
(See Figure 5-13)

5.9 Typical Characteristics (continued)
60 W
1%
±
50 W
375 W 1%
±
-7 V < V < 12 V
(TEST)
VOD
V (low)
OD
t (diff)
pZL
t (diff)
pZH
V
0 or 3 V
375 W 1%
±
50%
0 V
1.5 V
D
Z
DE
Y
-1.5 V
V (high)
OD
Input
Generator
Figure 5-13. Driver Enable Time From DE to VOD
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Parameter Measurement Information
IOA
VOD 54 Ω ±1%
0 or 3 V
VOA
VOB
IOB
DE
VCC
II
VI
A
B
Figure 6-1. Driver VOD Test Circuit and Voltage and Current Definitions
60 Ω ±1%
VOD
0 or 3 V
_
+ -7 V < V(test)
< 12 V
DE
VCC
A
B
D
375 Ω ±1%
375 Ω ±1%
Figure 6-2. Driver VOD With Common-Mode Loading Test Circuit
VOC
27 Ω ± 1%
Input
A
B
VA
VB
VOC(PP) ∆VOC(SS)
VOC
27 Ω ± 1%
CL = 50 pF ±20%
D
A
B
DE
VCC
Input: PRR = 500 kHz, 50% Duty Cycle,tr<6ns, tf<6ns, ZO = 50 Ω
CL Includes Fixture and
Instrumentation Capacitance
Figure 6-3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
VOD
RL = 54 Ω
± 1%
50 Ω
Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω
tPLH tPHL
1.5 V 1.5 V
3 V
≈ 2 V
≈ –2 V
90%
10%
0 V
VI
VOD
tr tf
CL = 50 pF ±20%
CL Includes Fixture
and Instrumentation
Capacitance
D
A
B
DE
VCC
VI
Input
Generator
90%
0 V
10%
0 V
Figure 6-4. Driver Switching Test Circuit and Voltage Waveforms

RL = 110 Ω
± 1%
Input
Generator 50 Ω
3 V
S1
0.5 V
3 V
0 V
VOH
≈ 0 V
tPHZ
tPZH(1 & 2)
1.5 V 1.5 V
VI
VO
CL = 50 pF ±20%
CL Includes Fixture
and Instrumentation
Capacitance
D
A
B
DE
VO
VI
2.3 V
Figure 6-5. Driver High-Level Enable and Disable Time Test Circuit and Voltage Waveforms
Input
Generator 50 Ω
3 V VO
S1 1.5 V 1.5 V
tPLZ
2.3 V
0.5 V
≈ 3 V
0 V
VOL
VI
VO
RL = 110 Ω
± 1%
CL = 50 pF ±20%
CL Includes Fixture
and Instrumentation
Capacitance
D
A
B
DE
VI
tPZL(1 & 2)
VCC
VCC
Figure 6-6. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
VID
VA
VB
IO
A
B
IB VO
R
IA
VIC
VA + VB
2
Figure 6-7. Receiver Voltage and Current Definitions
Input
Generator 50 Ω
VO
1.5 V
0 V
1.5 V 1.5 V
3 V
VOH
VOL
1.5 V
10%
1.5 V
tPLH tPHL
tr tf
90%
VI
VO
CL = 15 pF ±20%
CL Includes Fixture
and Instrumentation
Capacitance
A
B
RE
VI
R
0 V
90%
10%
Figure 6-8. Receiver Switching Test Circuit and Voltage Waveforms
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50 Ω
Generator: PRR = 100 kHz,
50% Duty Cycle,
tr <6 ns, tf <6 ns, Zo = 50 Ω
VO
RE
VCC
0 V or 3 V
1.5 V 1.5 V
tPZH(1) tPHZ
1.5 V
VOH –0.5 V
3 V
0 V
VOH
≈ 0 V
VO
CL = 15 pF ±20%
VI
DE
D
1 kΩ ± 1%
VI
A
B
S1
D at 3 V
S1 to B
tPZL(1) tPLZ
1.5 V
VOL +0.5 V
VOL
VO
D at 0 V
S1 to A
Input
Generator
R
3 V
A
B
VCC
Figure 6-9. Receiver Enable and Disable Time Test Circuit and Voltage Waveforms With Drivers Enabled

1.5 V
tPZH(2)
1.5 V
3 V
0 V
VOH
GND
VI
VO
0 V or 1.5 V
1.5 V or 0 V
A at 1.5 V
B at 0 V
S1 to B
tPZL(2)
1.5 V
VOL
VO
A at 0 V
B at 1.5 V
S1 to A
50 Ω
Generator: PRR = 100 kHz,
50% Duty Cycle,
tr <6 ns, tf <6 ns, Zo = 50 Ω
VO
RE
CL = 15 pF ±20%
VI
DE
1 kΩ ± 1%
A
B
S1
Input
Generator
R
0 V
A
B
VCC
VCC
Figure 6-10. Receiver Enable Time From Standby (Driver Disabled)
Pulse Generator,
15 µs Duration,
1% Duty Cycle
tr, tf ≤ 100 ns
100 Ω
± 1%
_
+
A
B
R
D
DE
RE
0 V or 3 V
NOTE: This test is conducted to test survivability only. Data stability at the R output is not specified.
3 V or 0 V
Figure 6-11. Test Circuit, Transient Over Voltage Test
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6 Function Tables
Table 6-1. DRIVER
INPUT ENABLE OUTPUTS
D DE A B
H
L
X
Open
X
H
H
L
H
Open
H
L
Z
H
Z
L
H
Z
L
Z
Table 6-2. RECEIVER
DIFFERENTIAL INPUTS(1) ENABLE OUTPUT
VID = VA – VB RE R
VID ≤ –0.2 V
–0.2 V < VID < –0.01 V
–0.01 V≤ VID
X
Open Circuit
Short Circuit
IDLE Bus
X
L
L
L
H
L
L
L
Open
L
?
H
Z
H
H
H
Z
(1) H = high level; L = low level; Z = high impedance; X = irrelevant;
? = indeterminate
6.1 Receiver Failsafe
The differential receiver is “failsafe” to invalid bus states caused by:
• open bus conditions such as a disconnected connector,
• shorted bus conditions such as cable damage shorting the twisted-pair together, or
• idle bus conditions that occur when no driver on the bus is actively driving
In any of these cases, the differential receiver outputs a failsafe logic High state, so that the output of the
receiver is not indeterminate.
Receiver failsafe is accomplished by offsetting the receiver thresholds so that the “input indeterminate” range
does not include zero volts differential. To comply with the RS-422 and RS-485 standards, the receiver output
must output a High when the differential input VID is more positive than +200 mV, and must output a Low when
the VID is more negative than -200 mV. The receiver parameters which determine the failsafe performance
are VIT+ and VIT- and VHYS. As seen in the Receiver Electrical Characteristics table, differential signals more
negative than -200 mV will always cause a Low receiver output. Similarly, differential signals more positive than
+200 mV will always cause a High receiver output.
When the differential input signal is close to zero, it will still be above the VIT+ threshold, and the receiver output
is High. Only when the differential input is more negative than VIT- will the receiver output transition to a Low
state. So, the noise immunity of the receiver inputs during a bus fault condition includes the receiver hysteresis
value VHYS (the separation between VIT+ and VIT- ) as well as the value of VIT+.

7 Equivalent Input and Output Schematic Diagrams
9 V
1 kΩ
100 kΩ
Input
VCC
D and RE Inputs
9 V
1 kΩ
100 kΩ
Input
VCC
DE Input
16 V
16 V
100 kΩ R3
R1
R2
Input
A Input
16 V
16 V
100 kΩ
R3
R1
R2
Input
B Input
16 V
16 V
VCC
A and B Outputs
9 V
VCC
R Output
5 Ω
Output
VCC
SN65HVD05
SN65HVD06
SN65HVD07
R1/R2
9 kΩ
36 kΩ
36 kΩ
R3
45 kΩ
180 kΩ
180 kΩ
VCC
Output
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
Typical Application
RT RT
Device
HVD05
HVD06
HVD07
Number of Devices on Bus
64
256
256
NOTE: The line should be terminated at both ends with its characteristic impedance (RT = ZO).
Stub lengths off the main line should be kept as short as possible.
Figure 8-1. Typical Application Circuit

9 Device and Documentation Support
9.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
9.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
9.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
9.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.5 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
www.ti.com

PACKAGE OPTION ADDENDUM
www.ti.com 23-Feb-2024
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN65HVD05D NRND SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VP05
SN65HVD05DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VP05 Samples
SN65HVD05P ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 65HVD05 Samples
SN65HVD06DG4 NRND SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VP06
SN65HVD07P ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 65HVD07 Samples
SN75HVD05D NRND SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 VN05
SN75HVD06D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 VN06 Samples
SN75HVD06DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 VN06 Samples
SN75HVD07D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 VN07 Samples
SN75HVD07DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 VN07 Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
Addendum-Page 1

PACKAGE OPTION ADDENDUM
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2

PACKAGE MATERIALS INFORMATION
TAPE AND REEL INFORMATION
Reel Width (W1)
REEL DIMENSIONS
A0
B0
K0
W
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Dimension designed to accommodate the component width
TAPE DIMENSIONS
K0 P1
B0 W
A0
Cavity
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Pocket Quadrants
Sprocket Holes
Q1 Q1
Q2 Q2
Q3 Q3
Q4 Q4 User Direction of Feed
P1
Reel
Diameter
*All dimensions are nominal
Device Package
Type
Package
Drawing
Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
SN65HVD05DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN65HVD06DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN65HVD07DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN75HVD06DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN75HVD07DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
Pack Materials-Page 1

TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L H
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65HVD05DR SOIC D 8 2500 356.0 356.0 35.0
SN65HVD06DR SOIC D 8 2500 356.0 356.0 35.0
SN65HVD07DR SOIC D 8 2500 356.0 356.0 35.0
SN75HVD06DR SOIC D 8 2500 340.5 336.1 25.0
SN75HVD07DR SOIC D 8 2500 340.5 338.1 20.6

TUBE
L - Tube length
T - Tube
height
W - Tube
width
B - Alignment groove width
Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
SN65HVD05D D SOIC 8 75 507 8 3940 4.32
SN65HVD05P P PDIP 8 50 506 13.97 11230 4.32
SN65HVD06D D SOIC 8 75 507 8 3940 4.32
SN65HVD06DG4 D SOIC 8 75 507 8 3940 4.32
SN65HVD07D D SOIC 8 75 507 8 3940 4.32
SN65HVD07P P PDIP 8 50 506 13.97 11230 4.32
SN75HVD05D D SOIC 8 75 507 8 3940 4.32
SN75HVD06D D SOIC 8 75 507 8 3940 4.32
SN75HVD07D D SOIC 8 75 507 8 3940 4.32

www.ti.com
PACKAGE OUTLINE
C
.228-.244 TYP
[5.80-6.19]
.069 MAX
[1.75]
6X .050
[1.27]
8X .012-.020
[0.31-0.51]
2X
.150
[3.81]
.005-.010 TYP
[0.13-0.25]
0 - 8
.004-.010
[0.11-0.25]
.010
[0.25]
.016-.050
[0.41-1.27]
4X (0 -15 )
A
.189-.197
[4.81-5.00]
NOTE 3
B .150-.157
[3.81-3.98]
NOTE 4
4X (0 -15 )
(.041)
[1.04]
SOIC - 1.75 mm max height
D0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
1
8
.010 [0.25] C A B
5
4
PIN 1 ID AREA
SEATING PLANE
.004 [0.1] C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800

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EXAMPLE BOARD LAYOUT
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
(.213)
[5.4]
6X (.050 )
[1.27]
8X (.061 )
[1.55]
8X (.024)
[0.6]
(R.002 ) TYP
[0.05]
D0008A
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EXPOSED
METAL
OPENING
SOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED
METAL
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SYMM
1
4
5
8
SEE
DETAILS
SYMM

www.ti.com
EXAMPLE STENCIL DESIGN
8X (.061 )
[1.55]
8X (.024)
[0.6]
6X (.050 )
[1.27]
(.213)
[5.4]
(R.002 ) TYP
[0.05]
D0008A
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
SYMM
SYMM
1
4
5
8

testing purpose for ic testing and othettastinng

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