TrueFalse Verilog is case-insensitive TF Verilog has constructs.pdf
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The document discusses true/false statements regarding Verilog, explaining its case sensitivity, support for hardware concurrency, hierarchical decomposition, and nested modules. It also addresses the conversion of the decimal number -13.5625 into IEEE single precision floating point format, providing both binary and hexadecimal representations. Additionally, it includes a design question for a left bit shifter for 8-bit numbers.
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TrueFalse Verilog is case-insensitive TF Verilog has constructs.pdf
- 1. True/False Verilog is case-insensitive T/F Verilog has constructs that model hardware concurrency T/F Verilog HDL does not support hierarchical decomposition of a design T/F It is alright to define a module within a module T/F Data-Flow constructs with delay specifications are synthesizable T/F Short Questions Write -13.5625 as an IEEE single precision floating point number. You may write your 32-bit answer in binary or hexadecimal, but it must conform to the single-precision IEEE 754 floating point standard? (4) Design the hardware for a left shifter that shifts an 8-bit number 2 bit to the left. For example if A = 00011111, A Shifted = 01111100? Solution Answers: Question 1 1)False Explanation:Verilog is a case-sensitive language. All keywords are in lowercase. 2)True Explanation:and Verilog HDL opening concurrent contexts: Fork-Join in Verilog that are used in modeling on to concurrent hardware 3)False Explanation:Verilog HDL supports a top-down design approach of hierarchical decomposition 4)True Explanation: It is safe to use nested module 5)True Explanation: Verilog code using synthesizable constructs of the language. Question 2 1)the decimal representation of numbers like "-13.5625" . The conversion is IEEE 754 Converter Binary Representation:11000001010110010000000000000000 Hexadecimal Representation:0xc1590000